MOTOROLA MCC14LC5004

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14LC5003
MC14LC5004
128 Segment LCD Drivers
CMOS
•
•
•
•
•
•
52
1
ORDERING INFORMATION
MC14LC5003FU
MC14LC5004FU
MCC14LC5003
MCC14LC5004
QFP
QFP
BARE DIE
BARE DIE
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
BP1
BP2
BP3
BP4
A0
A1
A2
ENB
NC
PIN ASSIGNMENT
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
Din
DCLK
NC
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
NC
FP19
FP18
FP17
FP16
FP15
VLCD
VSS
FP14
FP13
FP12
FP11
NC
•
Drives 128 Segments Per Package
May Be Used with the Following LCDs: Segmented Alphanumeric,
Bar Graph, Dot Matrix, Custom
Quiescent Supply Current: 30 A @ 2.7 V VDD
Operating Voltage Range: 2.7 to 5.5 V
Operating Temperature Range: - 40 to 85C
Separate Access to LCD Drive Section’s Supply Voltage to Allow for Temperature Compensation
See Application Notes AN1066 and AN442
QFP
FU SUFFIX
CASE 848B
NC
OSC1
OSC2
VDD
The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The two devices are functionally the same except for their data input
protocols. The MC14LC5003 uses a serial interface data input protocol. The
device may be interfaced to the MC68HCXX product families using a minimal
amount of software (see example). The MC14LC5004 has a IIC interface and
has essentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eight-bit byte is received.
MC14LC5004 also has a “read mode”, whereby data sent to the device may
be retrieved via the IIC bus.
The MC14LC5003/MC14LC5004 drives the liquid-crystal displays in a multiplexed-by-four configuration. The device accepts data from a microprocessor or other serial data source to drive one segment per bit. The chip does
not have a decoder, allowing for the flexibility of formatting the segment data
externally.
Devices are independently addressable via a two-wire (or three-wire) communication link which can be common with other peripheral devices.
The MC14LC5003/MC14LC5004 are low cost version of MC145003 and
MC145004 without cascading function.
BLOCK DIAGRAM
VLCD
OSC1
OSC2
BP1-BP4
FRAME
SYNC
GENERATOR
A2
ENB
DATA AND ADDRESS
A1
CONTROL AND TIMING
POR
A0
FP1-FP32
OSCILLATOR
DRIVERS
DCLK
Din
NC=NO CONNECTION
LCD VOLTAGE
WAVEFORM
AND TIMING
GENERATOR
DRIVERS
128 - 32
MULTIPLEX
128-BIT LATCH
128-BIT SHIFT REGISTER
REV 2
10/96
MOTOROLA
MC14LC5003 • MC14LC5004
3–3
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Vin
Input Voltage, Din, and Data Clock
Vin osc
Input Voltage, OSCin of Master
Value
Unit
- 0.5 to + 6.5
V
- 0.5 to 15
V
- 0.5 to VDD + 0.5
V
± 10
mA
Iin
DC Input Current, per Pin
TA
Operating Temperature Range
- 40 to + 85
°C
Storage Temperature Range
- 65 to + 150
°C
Tstg
This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high-impedance circuit. This
device may be light sensitive. Caution
should be taken to avoid exposure of this
device to any light source during normal operation. This device is not radiation protected.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA= 25C)
Symbol
VDD
V
VLCD
V
Min
Typical
Max
VO = 0.15 V
IFH
IFL
5
5
2.7
2.7
260
260
—
—
—
—
VO = 2.65 V
IFH
IFL
5
5
2.7
2.7
-240
-240
—
—
—
—
VO = 1.72 V
IFH
IFL
5
5
2.7
2.7
-40
—
—
—
—
-1.5
VO = 1.08 V
IFH
IFL
5
5
2.7
2.7
40
—
—
—
—
2
VO = 0.15 V
IFH
IFL
5
5
5.5
5.5
600
600
—
—
—
—
VO = 5.35 V
IFH
IFL
5
5
5.5
5.5
-520
-520
—
—
—
—
VO = 3.52 V
IFH
IFL
5
5
5.5
5.5
-35
—
—
—
—
-1.5
VO = 1.98 V
IFH
IFL
5
5
5.5
5.5
55
—
—
—
—
1
Supply Standby Currents (No Clock)
IDD = Standby @ Iout = 0 µA
ILCD = Standby @ Iout = 0 µA
IDD = Standby @ Iout = 0 µA
ILCD = Standby @ Iout = 0 µA
IDDS
ILCDS
IDDS
ILCDS
2.7
—
5.5
—
—
2.7
—
5.5
—
—
—
—
—
—
—
—
30
800
50
1500
Supply Currents (fOSC) = 110 kHz
IDD = Quiescent @ Iout = 0 µA, no loading
IDD = Quiescent @ loading = 270pF
IDD = Quiescent @ Iout = 0 µA, no loading
IDD = Quiescent @ loading = 270pF
ILCD = Quiescent @ Iout = 0 µA, no loading
ILCD = Quiescent @ Iout = 0 µA, no loading
IDDQ
IDDQ
IDDQ
IDDQ
ILCDQ
ILCDQ
2.7
2.7
5.5
5.5
—
—
—
—
—
—
2.7
5.5
—
—
—
—
—
—
30
—
170
—
—
—
—
70
—
400
40
70
Input Current
Iin
—
—
-0.1
—
0.1
µA
Input Capacitance
Cin
—
—
—
—
7.5
pF
Characteristic
Unit
µA
Output Drive Current — Frontplanes
µA
µA
(continued)
MC14LC5003 • MC14LC5004
3–4
MOTOROLA
ELECTRICAL CHARACTERISTICS (Continued)
Symbol
VDD
V
VLCD
V
Min
Typical
Max
Unit
fOSC2
fBP
fOSC2
5
5
5
5
5
5
100
100
23
—
—
—
150
150
33
kHz
Hz
kHz
Average DC Offset Voltage (BP Relative to FP)
VOO
5
2.8
-50
—
+50
mV
Input Voltage
“0” Level
VIL
VIL
2.8
5.5
5
5
—
—
—
—
0.85
1.65
V
“1” Level
VIH
VIH
2.8
5.5
5
5
2
3.85
—
—
—
—
Output Drive Current — Backplanes VO = 2.65 V
IBH*
IBL
5
5
2.8
2.8
-240
-240
—
—
—
—
VO = 0.15 V
IBH
IBL
5
5
2.8
2.8
260
260
—
—
—
—
VO = 1.08V
IBH
IBL
5
5
2.8
2.8
40
—
—
—
—
2
VO = 1.72 V
IBH
IBL
5
5
2.8
2.8
-40
—
—
—
—
-1
VO = 5.35 V
IBH
IBL
5
5
5.5
5.5
-520
-520
—
—
—
—
VO = 0.15 V
IBH
IBL
5
5
5.5
5.5
600
600
—
—
—
—
VO = 1.98 V
IBH
IBL
5
5
5.5
5.5
55
—
—
—
—
1
VO = 3.52 V
IBH
IBL
5
5
5.5
5.5
-35
—
—
—
—
-1
Pulse Width, Data Clock
(Figure 1)
tw
5
3
50
100
—
—
—
—
ns
DCLK Rise/Fall Time
(Figure 1)
tr, tf
5
3
—
—
—
—
20
120
µs
Setup Time, Din to DCLK
(Figure 2)
tsu
5
3
0
0
—
—
—
—
ns
Hold Time, Din to DCLK
(Figure 2)
th
5
3
30
60
—
—
—
—
ns
DCLK Low to ENB High
(Figure 3)
th
5
3
10
20
—
—
—
—
ns
ENB High to DCLK High
(Figure 3)
trec
5
3
10
20
—
—
—
—
ns
ENB High Pulse Width
(Figure 3)
tw
5
3
50
100
—
—
—
—
ns
ENB Low to DCLK High
(Figure 3)
tsu
5
3
10
20
—
—
—
—
ns
Characteristic
Frequencies
OSC2 Frequency @ R1; R1 = 200 kΩ
BP Frequency @ R1
OSC2 Frequency @ R2; R2 = 996 kΩ
µA
NOTE: Timing for Figures 1, 2, and 3 are design estimates only.
* For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to
allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change.
MOTOROLA
MC14LC5003 • MC14LC5004
3–5
SWITCHING WAVEFORMS
VALID
tf
tr
GND
tsu
GND
tw
tw
VDD
50%
Din
VDD
90%
CLK 50%
10%
th
VDD
CLK
50%
Figure 1.
GND
Figure 2.
tw
ENB
tw
VDD
50%
tsu
GND
th
trec
CLK
50%
FIRST
CLK
LAST
CLK
VDD
GND
Figure 3.
MC14LC5003 • MC14LC5004
3–6
MOTOROLA
FUNCTIONAL DESCRIPTION
The MC14LC5003/MC14LC5004 has essentially two sections which operate asynchronously from each other; the data
input and storage section and the LCD drive section. The LCD
drive and timing is derived from the oscillator, while the data
input and storage is controlled by the Data In (Din), Data Clock
(DCLK), Address (A0, A1, A2), and Enable (ENB) pins.
Data is shifted serially into the 128-bit shift register and arranged into four consecutive blocks of 32 parallel data bits. A
time-multiplex of the four backplane drivers is made (each
backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the
corresponding block of 32 bits is made available at the frontplane drivers. A high input to a plane driver turns the driver
on, and a low input turns the driver off.
Figure 4 shows the sequence of backplanes. Figure 5 shows
the possible configurations of the frontplanes relative to the
backplanes. When a backplane driver is on, its output switches
from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD
to 2/3 VLCD. When a frontplane driver is on, its
output switches from 0 V to VLCD, and when it is off, it switches
from 2/3 VLCD to 1/3 VLCD.
The LCD drive and timing section provides the multiplex signals and backplane driver input signals and formats the frontplane and backplane waveforms.
The address pins are used to uniquely distinguish LCD driver
from any other chips on the same bus and to define LCD driver
as the “master” in the system. There must be one master in any
system.
The enable pin may be used as a third control line in the
communication bus. It may be used to define the moment
when the data is latched. If not used, then the data is latched
after 128 bits of data have been received.
TIME FRAME
VLCD
2/3 (VLCD)
1/3 (VLCD)
BP1
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
BP2
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
BP3
0V
VLCD
2/3 (VLCD)
1/3 (VLCD)
BP4
0V
Figure 4. Backplane Sequence
MOTOROLA
MC14LC5003 • MC14LC5004
3–7
TIME FRAME
TIME FRAME
VLCD
VLCD
BP1
BP1
0V
FP DATA
BITS
4321
0000
1000
0100
1100
0010
1010
0110
1110
VLCD
0V
VLCD
FP DATA
BITS
4321
0001
2/3 (VLCD)
1/3 (VLCD)
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
1001
2/3 (VLCD)
1/3 (VLCD)
2/3 (VLCD)
1/3 (VLCD)
0V
0V
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
0101
2/3 (VLCD)
1/3 (VLCD)
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
1101
2/3 (VLCD)
1/3 (VLCD)
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
0011
2/3 (VLCD)
1/3 (VLCD)
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
1011
2/3 (VLCD)
1/3 (VLCD)
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
0111
2/3 (VLCD)
1/3 (VLCD)
0V
0V
VLCD
VLCD
2/3 (VLCD)
1/3 (VLCD)
1111
0V
2/3 (VLCD)
1/3 (VLCD)
0V
Figure 5. Frontplane Combinations
MC14LC5003 • MC14LC5004
3–8
MOTOROLA
A0-A2
Address Inputs (Pins 42-44)
The devices have to receive a correct address before they
will accept data. Three address pins (A2, A1, A0) are used to
define the states of the three programmable bits of
MC14LC5003/MC14LC5004’s 8-bit address.
The address is 0111vwxy where v, w, x represent A2, A1,
and A0 respectively. Where v, w, x=0, then A2, A1, and A0
should be tied to 0 V. Where v, w, x=1, then A2, A1, and A0
should be tied to VDD.
The address pins must be tied to VDD. This defines the
device as a master.
EXTERNAL RESISTOR VALUE
PIN DESCRIPTIONS
10 M
1M
100 k
10 k
1k
10 k
100 k
1M
10 M
OSCILLATOR FREQUENCY
NOTE
Note: In applications where the circuit will be isolated from
external manual interference the system designer may take
advantage of the self-programming feature. Upon power-on,
address pins which are left open-circuit will be charged to VDD.
However, care must be taken not to inadvertently discharge
the pins after power-on since the address may then be lost. A
similar feature is also available on the ENB pin.
CAUTION
The configuration A0, A1, A2 = 000 should not be used. This
does not give a valid address and is reserved for Motorola’s
use only. All three address pins should never be tied to 0 V
simultaneously.
ENB
Enable Input (Pin 41)
If the ENB pin is tied to V DD, the MC14LC5003/
MC14LC5004 will always latch the data after 128 bits have
been received. The latched data is multiplexed and fed to the
frontplane drivers for display. If external control of this latching
function is required, then the ENB pin should be held low,
followed by one high pulse on ENB when data display is required. (This may be useful in a system where one MC145003/
MC145004 is permanently addressed and only the last 128
bits of data sent are required to be latched for display). The
pulse on the ENB pin must occur while DCLK is high.
DCLK, Din
Data Clock and Data Input (Pins 38, 39)
Address input and data input controls. See Data Input Protocol sections for relevant option.
OSC1, OSC2
Oscillator Pins (Pins 51, 50)
To use the on-board oscillator, an external resistor should
be connected between OSC1 and OSC2. Optionally, the
OSC1 pin may be driven by an externally generated clock
signal.
A resistor of 680 k connected between OSC1 and OSC2
pins gives an oscillator frequency of about 30 kHz, giving
approximately 30 Hz as seen at the LCD driver outputs. A
resistor of 200 k gives about 100 kHz, which results in 100Hz
at the driver outputs. LCD manufacturers recommend an LCD
drive frequency of between 30 Hz and 100 Hz. See Figure 6.
MOTOROLA
Figure 6. Oscillator Frequency vs. Load Resistance
(Approximate)
FP1-FP32
Frontplane Drivers (Pins 36-27, 25-22, 19-15, 13-1)
Frontplane driver outputs.
BP1-BP4
Backplane Drivers (Pins 48-45)
Backplane driver outputs.
VLCD
LCD Driver Supply (Pin 20)
Power supply input for LCD drive outputs. May be used to
supply a temperature-compensated voltage to the LCD drive
section, which can be separate from the logic voltage supply,
VDD.
VDD
Positive Power Supply (Pin 49)
This pin supplies power to the main processor interface and
logic portions of the device. The voltage range is 2.7 to 5.5 V
with respect to the VSS pin.
For optimum performance, VDD should be bypassed to
VSS using a low inductance capacitor mounted very closely
to these pins. Lead length on this capacitor should be minimized.
VSS
Ground (Pin 21)
Common ground.
DATA INPUT PROTOCOL
Two-wire communication bus DCLK, Din; three-wire communication bus DCLK, Din, ENB.
MC14LC5003 — SERIAL INTERFACE DEVICE (FIGURE 7)
Before communication with an MC14LC5003 can begin, a
start condition must be set up on the bus by the transmitter.
To establish a start condition, the transmitter must pull the
data line low while the clock line is high. The “idle” state for
the clock line and data line is the high state.
After the start condition has been established, an eight-bit
address should be sent by the transmitter. If the address sent
corresponds to the address of the MC14LC5003 then on each
MC14LC5003 • MC14LC5004
3–9
successive clock pulse, the addressed device will accept a
data bit.
If the ENB pin is permanently high, then the addressed
MC14LC5003’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the
control of this latch function may be overridden by holding the
ENB line low until the new data is required to be displayed,
then a high pulse should be sent on the ENB line. The high
pulse must be sent during DCLK high (clock idle).
To end communication with an MC14LC5003, a stop condition should be set up on the bus (or another start condition
may be set up if another communication is desired). Note that
the communication channel to an addressed device may be
left open after the 128 data bits have been sent by not setting
up a stop or a start condition. In such a case, the 129th rising
DCLK edge, which normally would be used to set up the stop
or start condition, is ignored by the MC14LC5003 and data
continues to be received on the 130th rising DCLK. The latch
function continues to work as normal (i.e., data is be latched
either after each block of 128 data bits has been received or
under external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
MC14LC5004 — IIC DEVICE (FIGURE 8)
Before communication with an MC14LC5004 can begin, a
start condition must be set up on the bus by the controller. To
establish a start condition, the controller must pull the data
line low while the clock line is high.
After the start condition has been established, an eight-bit
address should be sent by the controller followed by an extra
clock pulse while the data line is left high. In this option, only
the seven most significant bits of the address are used to
uniquely define devices on the bus, the least significant bit is
used as a read/write control: if the least significant bit is 0,
then the controller writes to the LCD driver; if it is 1, then the
MC14LC5003 • MC14LC5004
3–10
controller reads from the LCD driver’s 128-bit shift register on
a first-in first-out basis. If the seven most significant address
bits sent correspond to the address of the LCD driver then the
addressed LCD driver responds by sending an “acknowledge”
bit back to the controller (i.e., the LCD driver pulls the data line
low during the extra clock pulse supplied by the controller). If
the least significant address bit was 0, then the controller
should continue to send data to the LCD driver in blocks of
eight bits followed by an extra ninth clock pulse to allow the
LCD driver to pull the data line Din low as an acknowledgment.
If the least significant address bit was 1, then the LCD driver
sends data back to the controller (the clock is supplied by the
controller). After each successive group of eight bits sent, the
LCD driver leaves the data line high for one pulse.
If the ENB pin is permanently high, then the addressed
MC14LC5004’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise the
control of this latch function may be overridden by holding the
ENB line low until the new data is required to be displayed,
then a high pulse should be sent on the ENB line. The high
pulse must be sent during DCLK high (clock idle).
To end communication with an MC14LC5004, a stop condition should be set up on the bus (or another start condition
may be set up if another communication is desired). Note that
the communication channel to an addressed device may be
left open after the 128 data bits have been sent by not setting
up a stop or a start condition. In such a case the rising DCLK
edge which comes after all 128 data bits have been sent and
after the last acknowledge-related clock pulse has been made
is ignored; data continues to be received on the following
DCLK high. The latch function continues to work as normal
(i.e., data is latched either after each block of 128 data bits
has been received or under external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
MOTOROLA
Figure 7. MC14LC5003(SERIAL INTERFACE DEVICE)
MOTOROLA
MC14LC5003 • MC14LC5004
3–11
ENB
(IF USED)
DCLK
D
in
START
A1
A0
FP1
FP2
x: 1→(BPi, FPj) ON
0 →(BPi, FPj) OFF
FP1
FP4
FP5
FP6
Figure 7b. Serial 128 Bits Data
FP3
FP32
4 3 2 1
128-BITS DATA
FP2
BP3 BP2 BP1 BP4 BP3 BP2 BP1
Figure 7a. Data Input—MC14LC5003
BP4
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
Din x
BP
8-BITS ADDRESS
A2
ENABLE PULSE MAY OCCUR AS REQUIRED
BUT MUST BE DURING DCLK HIGH.
START
129TH DCLK HIGH:
(DOES NOT SHIFT DATA)
Figure 8 . Data Input MC14LC5004 (IIC Device)
MC14LC5003 • MC14LC5004
3–12
MOTOROLA
START
D in
(FROM LCD
DRIVER)
DCLK
D in
(FROM
CONTROLLER)
START
READ FROM LCD DRIVER
ENB
(IF USED)
D in
(FROM LCD
DRIVER)
DCLK
D in
(FROM
CONTROLLER)
WRITE TO LCD DRIVER
A1
A0
8-BITS ADDRESS
ENTIRE CLK FOR
ACKNOWLEDGE
PULLED LOW BY DRIVER
ENTIRE CLK FOR
ACKNOWLEDGE
BP1
BP4
8-BITS DATA
8-BITS DATA
BP2
FP1
BP4 BP3
LEFT HIGH
BY CONTROLLER
ADDRESS ACKNOWLEDGED BY DRIVER
(LOW-ORDER BIT=1)
8-BITS ADDRESS
A2
(LOW-ORDER BIT 02=0)
BP3
LAST DCLK PULSE
(DOES NOT SHIFT DATA)
ENTIRE CLK FOR
ACKNOWLEDGE
LEFT HIGH BY DRIVER
LEFT HIGH BY DRIVER
STOP
LAST DCLK PULSE
(DOES NOT SHIFT DATA)
CONTINUES TO CLOCK DATA AND ACKNOWLEDGE
ENTIRE CLK FOR
ACKNOWLEDGE
ENABLE PULSE MAY OCCUR AS REQUIRED;
BUT MUST BE DURING DCLK HIGH.
STOP
CONTINUES TO CLOCK DATA AND ACKNOWLEDGE
ENTIRE CLK FOR
ACKNOWLEDGE
BP1
LEFT HIGH
BY CONTROLLER
PULLED LOW BY DRIVER
BP2
FP2
MOTOROLA
FP2
FP25
FP5
FP24
FP6
FP23
FP7
FP22
FP8
FP21
FP9
CONTROLLER
VDD
VLCD
VSS
FP28
DATA
FP1
CLOCK
FP11
FP12
FP13
FP14
FP29
LCD DRIVER
FP26
VLCD
VSS
FP27
FP15
FP16
FP17
FP18
ENB
A2
A1
A0
BP4
BP3
BP2
BP1
V DD
OSC2
OSC1
BP1-BP4
680 k
ON BUS
BP1-BP4
FP1-FP32
FP1-FP32
FP31
STROBE
FP20
FP19
LIQUID CRYSTAL DISPLAY
FP32
Din
DCLK
FP30
FP3
FP4
FP10
Figure 9. Application Example
MC14LC5003 • MC14LC5004
3–13
APPLICATION INFORMATION
Figure 10 shows an interface example.
Example shows a semi-automatic SPI Mode (only start and stop conditions are done in non-SPI Mode). It contains the software
to use HC11 with MC14LC5003 in manual SPI Mode.
VDD
VDD
1k
A0
A2
OSC1
MOSI
MC68HC11
A1
Din
SCK
R = 470 k
MC14LC5003
OSC2
DCLK
ENB
SS
FP1-FP32
BP1-BP4
1/4 MUX DISPLAY
Figure 10. Interface Example Between MC68HC11 and MC14LC5003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
0000
0000
0000
0000
0000
0000
0000
T
T
T
T
T
T
T
;=======CONSTANTS=================================================
extram
equ
$A000
;$A000 for 8K RAM
stack
equ
$00FF
;last RAM byte
intofs
equ
$1000
;Internal Registers
data
equ
$08
clock
equ
$10
enable
equ
$20
portd
equ
8
A000
A000
A003
A005
A008
A00A
A00D
A010
T
N
M
T
M
N
T
T
8E00FF
8638
B71009
C611
CEA05E
BDA010
;=======PROGRAM BEGIN=============================================
org
extram
;Program into RAM
cold
lds
#stack
;set stack pointer
ldaa
#$38
;set of MOSI,SS,SCK
staa
$1009
;DDRD
ldab
#17
ldx
#send
jsr
spi
end
cold
A010
A014
A018
A01B
A01D
A020
A025
A026
A027
A029
A02D
A030
U
J
T
X
T
L
H
H
R
J
T
H
18CE1000
181D0820
BDA031
A600
B7102A
181F2980FB
08
5A
26F2
181C0820
BDA04C
39
A031
A033
M
T
8633
B71028
MC14LC5003 • MC14LC5004
3–14
spi
again
start
ldy
bclr
jsr
ldaa
staa
brclr
inx
decb
bne
bset
jsr
rts
ldaa
staa
#intofs
portd,y #enable
start
0 , x
$102A
$29,y,#$80,*
;EN = 0
;start condition
;SPI Mode Use
;SPDR
;next DATA
again
portd,y #enable
stop
;stop condition
#$33
$1028
;Normal Mode
;SPCR
MOTOROLA
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
A036
A03A
A03E
A042
A046
A048
A04B
A04C
A04E
A051
A055
A059
A05D
J
J
J
J
M
T
H
M
T
J
J
J
H
181C0808
181C0810
181D0808
181D0810
8673
B71028
39
8633
B71028
181D0808
181C0810
181C0808
39
A05E
A05F
A060
A061
A062
A063
A064
A065
A066
A067
A068
A069
A06A
A06B
A06C
A06D
A06E
A06F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
H
7E
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
F0
39
stop
send
bset
bset
bclr
bclr
ldaa
staa
rts
ldaa
staa
bclr
bset
bset
rts
portd,y
portd,y
portd,y
portd,y
#$73
$1028
#data
#clock
#data
#clock
;DATA = 1
;CLK = 1
;DATA = 0
;CLK = 0
;SPI Mode
;SPCR
#$33
$1028
portd,y #data
portd,y #clock
portd,y #data
;Normal Mode
;SPCR
;DATA = 0
;CLK = 1
;DATA = 0
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
rts
$007E
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
$00f0
;LCD Driver Address
;Data to sent
;=======PROGRAM END===============================================
Example 1. Semi-Automatic SPI Method
Figure 11 shows another interface example.
Example 2 contains the software to use HC05 with MC14LC5003 in serial data interface.
VDD
VDD
1k
A0
DOUT
MC68HC05
SCK
STROBE
A1
A2
OSC1
Din
R = 470 k
MC14LC5003
DCLK
OSC2
ENB
BP1-BP4
FP1-FP32
1/4 MUX DISPLAY
Figure 11. Interface Example Between MC68HC05 and MC14LC5003
MOTOROLA
MC14LC5003 • MC14LC5004
3–15
PORTC
DDRC
SEN
SCL
SDA
DOUT
W1
COUNT
EQU
EQU
EQU
EQU
EQU
EQU
$02
$06
$07
$06
$05
$FF
ORG
$0050
RMB
RMB
1
1
ORG
FCB
FCB
$1FFE
#$01
#$00
PORTC
PORTDC
ENABLE PIN, PC7
CLOCK PIN, PC6
DATA PIN, PC5
OUTPUT DATA
ADDRESS OF RESET VECTOR OF MC68HC805C4
RESET VECTOR
*** Main Program start at 0100 ***
START
ORG
LDA
STA
$0100
#DOUT
DDRC
LDX
BSET
BSET
#$00
SDA,PORTC
SCL,PORTC
BSET
LDA
STA
BCLR
SEN,PORTC
#$11
W1
SDA,PORTC
CLC
LDA
STA
LDA
INCX
#$08
COUNT
SEND,X
SET DATA LINE OUTPUT
AGAIN
READY
LBYTE
LBIT
DZERO
CLKHI
STOP
IDLE STATE
CLOCK AND DATA ARE HIGH
EN=1
SET ADDRESS AND 8 CHARACTERS
START CONDITION, DATA LOW WHILE CLOCK HIGH
8 BITS TO SHIFT
GET A BYTE
BCLR
ROLA
BCC
BSET
JMP
BCLR
BSET
DEC
BNE
DEC
BNE
SCL,PORTC
CLOCK LOW
DZERO
SDA,PORTC
CLKHI
SDA,PORTC
SCL,PORTC
COUNT
LBIT
W1
LBYTE
DATA BIT=0 ?
NO, BIT=1 AND DATA HIGH
BCLR
BCLR
BSET
BSET
BCLR
RTS
SCL,PORTC
SDA,PORTC
SCL,PORTC
SDA,PORTC
SEN,PORTC
DATA LOW
CLOCK HIGH
LAST BYTE ?
STOP CONDITION
DATA GOES HIGH WHILE CLOCK HIGH
EN=0
*** End of Program ***
*** LCD Address and Data ***
SEND
FCB
FCB
FCB
RTS
$7E
$FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF
$FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF
LCD DRIVER ADDRESS
DATA TO SENT
Example 2. Serial Data Interface Method
MC14LC5003 • MC14LC5004
3–16
MOTOROLA
PACKAGE DIMENSIONS
QFP
FU SUFFIX
CASE 848B-02
L
B
DETAIL A
52
V
0.20 (0.008) M C A-B S
L
0.20 (0.008) M H A-B S
-D-
-A-
0.05 (0.002) A-B
D S
26
40
D S
27
39
14
B
13
1
B
-DB
0.20 (0.008) M H A-B S
0.05 (0.002) A-B
D S
-A,B,DDETAIL A
V
0.20 (0.008) M C A-B S
D S
F
DETAIL C
M
C
E
J
-H-
-CH
SEATING
PLANE
N
DATUM
PLANE
BASE METAL
0.10 (0.004)
G
D
M
D S
0.02 (0.008) M C A-B S
SECTION B-B
MILLIMETERS
U
T
DATUM
PLANE
-H-
R
K
W
X
DETAIL C
Q
NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.
3.DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY
AT THE BOTTOM OF THE PARTING LINE.
4.DATUMS -A-, -B- AND -D- TO BE DETERMINED
AT DATUM PLANE -H-.
5.DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6.DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7.DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE
FOOT.
MIN
9.90
MAX
10.10
MIN
MX
0.390 0.398
B
9.90
10.10
0.390 0.398
C
2.10
2.45
0.083 0.096
D
0.22
0.38
0.009 0.015
E
2.00
2.10
0.079 0.083
F
0.22
0.33
0.009 0.013
G
0.65 BSC
H
--
0.25
J
0.13
0.23
0.005 0.009
K
0.65
0.95
0.026 0.037
L
7.80 REF
M
5˚
10˚
N
0.13
0.17
0.026 BSC
--
0.010
0.307 REF
5˚
10˚
0.005 0.007
Q
0˚
7˚
R
0.13
0.30
0.005 0.012
S
12.95
13.45
0.510 0.530
T
0.13
--
0.005
--
U
0˚
--
0˚
--
V
12.95
13.45
0.510 0.530
W
0.35
0.45
0.014 0.018
X
MOTOROLA
INCHES
DIM
A
1.6 REF
0˚
7˚
0.063 REF
MC14LC5003 • MC14LC5004
3–17
BOND PAD LAYOUT
-X
+X
PIN 1
+Y
-Y
©
HONG KONG I.C.
DESIGN CENTER
Die size : 78 x 119 mil2
(1 mil ~ 25.4m)
BOND PAD COORDINATES
COORDINATES
COORDINATES
PIN NO.
PIN NO.
PIN NAME
X
PIN NAME
X
Y
Y
1
FP32
-736.002
929.199
27
FP10
735.998
-837.201
2
FP31
-736.002
781.999
28
FP9
735.998
-690.001
3
FP30
-736.002
634.799
29
FP8
735.998
-542.801
4
FP29
-736.002
487.599
30
FP7
735.998
-395.601
5
FP28
-736.002
340.399
31
FP6
735.998
-248.401
6
FP27
-736.002
193.199
32
FP5
735.998
-101.201
7
FP26
-736.002
45.999
33
FP4
735.998
45.999
8
FP25
-736.002
-101.201
34
FP3
735.998
193.199
9
FP24
-736.002
-248.401
35
FP2
735.998
340.399
10
FP23
-736.002
-395.601
36
FP1
735.998
487.599
11
FP22
-736.002
-542.801
37
NC
736.000
634.800
12
FP21
-736.002
-690.001
38
DCLK
736.000
782.000
13
FP20
-736.002
-837.201
39
DIN
736.000
929.200
14
NC
N/A
N/A
40
NC
N/A
N/A
15
FP19
-736.002
-1205.601
41
ENB
736.000
1205.600
16
FP18
-588.802
-1205.601
42
A2
588.800
1205.600
17
FP17
-441.602
-1205.601
43
A1
441.600
1205.600
18
FP16
-294.402
-1205.601
44
A0
294.400
1205.600
19
FP15
-147.202
-1205.601
45
BP4
147.198
1205.599
20
VLCD
0.000
-1205.600
46
BP3
-0.002
1205.599
21
VSS
147.200
-1205.600
47
BP2
-147.202
1205.599
22
FP14
294.398
-1205.601
48
BP1
-294.402
1205.599
23
FP13
441.598
-1205.601
49
VDD
-441.600
1205.600
24
FP12
588.798
-1205.601
50
OSC2
-588.800
1205.600
25
FP11
735.998
-1205.601
51
OSC1
-736.000
1205.600
26
NC
N/A
N/A
52
NC
N/A
N/A
Dimemsions in m
MC14LC5003 • MC14LC5004
3–18
MOTOROLA