AZM AZ12001K Phase-locked loop clock generator Datasheet

ARIZONA MICROTEK, INC.
AZ12000, AZ12001
Phase-Locked Loop Clock Generator
FEATURES
•
•
•
•
•
•
•
•
•
PACKAGE AVAILABILITY
PECL (AZ12000) or LVDS
(AZ12001) Outputs
Operating Range 3.0V to 5.5V
Internal Crystal Oscillator Driver
Internal Edge-Matching
Phase/Frequency Detector
Internal Charge-Pump and
Integrator Amplifier
Internal or External VCO
Divide by 4, 8, 16, 32
RF Bipolar Design for Low Phase
Noise
Available in a 4x4mm MLP Package
PACKAGE
PART NO.
MLP 24 (4x4)
AZ12000K
MLP 24 (4x4)
AZ12001K
DIE
DIE
AZ12000XP
AZ12001XP
1
MARKING
NOTES
AZ12000
<Date Code>
AZ12001
<Date Code>
N/A
N/A
1,2
1,2
3
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
Waffle Pack
2
3
DESCRIPTION
The AZ12000/AZ12001 contains all of the functional elements necessary to implement a Phase-Locked Loop
for clock multiplication at frequencies up to 800 MHz. A reference crystal oscillator driver operates at frequencies
up to 200 MHz providing support for 4 times multiplication. The dynamic properties of the PLL are under the
control of the user through selection of the desired external components.
BLOCK DIAGRAM
CPPOL CPREF CPOUT
INTREF INTSUM
INTOUT
INTEGRATOR
OUTPT
DRVR
REFOUT
4mA
CHARGE
PUMP
V EE
REFIN
INPUT
RCVR
470 Ω
VBB
VCC
VCOVCC
VEE
VCO
PHASE/
FREQ
DETECT
MUX
MUX
VCO
OUTPUT
Q
BUFFER
VBB
DIVIDE BY
4,8,16,32
DS2 DS1
EXTVCO
TANK
EXTVCO
VCOSEL
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
Q
AZ12000
AZ12001
VCOVCC TANK VCOSEL N/C
24
23
22
21
VCC
VCC
20
19
EXTVCO 1
18
Q
EXTVCO 2
17
Q
16
VEE
15
VBB
DS1
3
DS2
4
VEE
5
14 CPPOL
REFOUT 6
13 INTOUT
Pinout:
AZ12000, AZ12001
(24 Pin MLP, Top View)
7
8
9
10
11
12
REFIN CPOUT CPREF INTREF INTSUM VEE
Bottom Center pad may be left open or tied to VEE.
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
IOUT
TA
TSTG
Characteristic
Power Supply
(VEE = GND)
Input Voltage
(VEE = GND)
— Continuous
ECL/PECL Output Current
— Surge
Operating Temperature Range
Storage Temperature Range
January 2005 * REV - 3
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2
Rating
0 to +6.0
0 to +6.0
40
80
-40 to +85
-65 to +150
Unit
Vdc
Vdc
mA
°C
°C
AZ12000
AZ12001
AZ12000 FUNCTIONAL PIN DESCRIPTIONS
Pin No
Pin Name
Functional Description
Reference Crystal Resonator Input This pin includes an on-chip 470 Ω pull
REFIN
down resistor to VBB. The input from the resonator circuit should be AC
coupled.
Crystal Resonator Output Drive This pin is an inverted and amplified version
of the signal on the REFIN pin. The gain from REFIN to REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ is
REFOUT
¯¯¯¯¯¯¯
approximately 20. The IC includes a 4 ma on-chip current source. If more
current is needed, the REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ pin may be connected to VEE through a resistor
to provide up to 8 ma additional current.
Charge Pump Reference Output The pin voltage is nominally 1.2 volts below
CPREF
VCC. If an external integrator is used, CPREF should be connected to the
integrator reference input through a bias current cancellation network.
Charge Pump Output The charge pump output voltage is V(CPREF) ±0.3V
during a phase correction pulse. When there is no correction pulse the output
CPOUT
goes high impedance. If an external integrator is used, CPOUT should be
connected to the input integrator resistor.
Charge Pump Polarity Logic LOW on this pin causes CPOUT to go low
when the VCO frequency is too low, and go high when the VCO frequency is
too high. Logic HIGH on this pin causes CPOUT to go low when the VCO
CPPOL
frequency is too high, and go high when the VCO frequency is too low. This
pin should be LOW when the internal VCO is used.
INTREF
INTSUM
INTOUT
VCOSEL
TANK
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
DS2
DS1
Q
Q̄
N/C
VBB
VCC
VCOVCC
VEE
If this pin is left open it is pulled to the HIGH condition.
Integrator Reference Input This pin should be connected to CPREF through a
bias current cancellation network
Integrator Summing Junction This pin is the summing junction for the
integrator amplifier
Integrator Output
Internal/External VCO Select Logic HIGH on this pin enables the internal
VCO. Logic LOW on this pin disables the internal VCO and allows use of the
EXTVCO inputs.
If this pin is left open it is pulled to the HIGH condition.
VCO Tank The tank components connect between this pin and VCC.
External VCO Input The external VCO input pins should be driven
differentially for best performance.
Divide Select VCO divide ratios are selected as shown:
DS1
Ratio
DS2
LOW
LOW
÷4
LOW
HIGH
÷8
HIGH
LOW
÷16
HIGH
HIGH
÷32
If the pins are left open they are pulled to the HIGH condition.
Clock Output These pins are the main (multiplied) clock output.
No Connect This pin is used during factory test. It mist be left open.
Reference Voltage Output This pin is used to bias the REFIN signal. It must
be bypassed externally to the VEE pins with a 0.01 µF capacitor.
Positive Supply +3.0 to +5.5 V for PECL mode, Ground for ECL mode.
VCO Positive Supply +3.0 to +5.5 V for PECL mode, Ground for ECL mode.
Negative Supply Ground for PECL mode, –3.0 to –5.5 V for ECL mode.
January 2005 * REV - 3
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3
Logic Level
ECL/PECL
CMOS/TTL
compatible
CMOS/TTL
compatible
ECL/PECL
CMOS/TTL
compatible
ECL/PECL
AZ12000
AZ12001
AZ12001 FUNCTIONAL PIN DESCRIPTIONS
Pin No
Pin Name
Functional Description
Reference Crystal Resonator Input This pin includes an on-chip 470 Ω pull
REFIN
down resistor to VBB. The input from the resonator circuit should be AC
coupled.
Crystal Resonator Output Drive This pin is an inverted and amplified version
of the signal on the REFIN pin. The gain from REFIN to REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ is
REFOUT
¯¯¯¯¯¯¯
approximately 20. The IC includes a 4 ma on-chip current source. If more
current is needed, the REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ pin may be connected to VEE through a resistor
to provide up to 8 ma additional current.
Charge Pump Reference Output The pin voltage is nominally 1.2 volts below
CPREF
VCC. If an external integrator is used, CPREF should be connected to the
integrator reference input through a bias current cancellation network.
Charge Pump Output The charge pump output voltage is V(CPREF) ±0.3V
during a phase correction pulse. When there is no correction pulse the output
CPOUT
goes high impedance. If an external integrator is used, CPOUT should be
connected to the input integrator resistor.
Charge Pump Polarity Logic LOW on this pin causes CPOUT to go low
when the VCO frequency is too low, and go high when the VCO frequency is
too high. Logic HIGH on this pin causes CPOUT to go low when the VCO
CPPOL
frequency is too high, and go high when the VCO frequency is too low. This
pin should be LOW when the internal VCO is used.
INTREF
INTSUM
INTOUT
VCOSEL
TANK
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
DS2
DS1
Q
Q̄
N/C
VBB
VCC
VCOVCC
VEE
If this pin is left open it is pulled to the HIGH condition.
Integrator Reference Input This pin should be connected to CPREF through a
bias current cancellation network
Integrator Summing Junction This pin is the summing junction for the
integrator amplifier
Integrator Output
Internal/External VCO Select Logic HIGH on this pin enables the internal
VCO. Logic LOW on this pin disables the internal VCO and allows use of the
EXTVCO inputs.
If this pin is left open it is pulled to the HIGH condition.
VCO Tank The tank components connect between this pin and VCC.
External VCO Input The external VCO input pins should be driven
differentially for best performance.
Divide Select VCO divide ratios are selected as shown:
DS1
Ratio
DS2
LOW
LOW
÷4
LOW
HIGH
÷8
HIGH
LOW
÷16
HIGH
HIGH
÷32
If the pins are left open they are pulled to the HIGH condition.
Clock Output These pins are the main (multiplied) clock output.
No Connect This pin is used during factory test. It must be left open.
Reference Voltage Output This pin is used to bias the REFIN signal. It must
be bypassed externally to the VEE pins with a 0.01 µF capacitor.
Positive Supply +3.0 to +5.5 V
VCO Positive Supply +3.0 to +5.5 V
Negative Supply Ground
January 2005 * REV - 3
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4
Logic Level
PECL
CMOS/TTL
compatible
CMOS/TTL
compatible
PECL
CMOS/TTL
Compatible
LVDS
AZ12000
AZ12001
AZ12000 (PECL OUTPUT) DC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol
VBB
RPD
ICS
VHCTL
VLCTL
-40°C
Min
Max
VCC
VCC
-1.38
-1.26
Characteristic
Reference Voltage
0°C
Min
Max
VCC
VCC
-1.38
-1.26
REFIN Pull-Down resistor
to VBB
REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ Current Source
High level integrator output
Min
VCC
-1.38
25°C
Typ
VCC
-1.31
Q
Q̄
Output LOW Voltage1
Q
Q̄
Input HIGH Voltage,
PECL/ECL
VIH
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input LOW Voltage,
PECL/ECL
VIL
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input HIGH Voltage,
TTL/CMOS
CPPOL
VIH
VCOSEL
DS2
DS1
Input HIGH Voltage,
TTL/CMOS
CPPOL
VIL
VCOSEL
DS2
DS1
ICC (IEE)
Power Supply Current
1. Load is 50Ω to VCC-2V
January 2005 * REV - 3
Max
VCC
-1.26
Unit
V
Ω
4.0
ma
VCC
-1.0
V
VEE
+0.5
V
1
VOH
VOL
Min
VCC
-1.38
470
Low level integrator output
Output HIGH Voltage
85°C
Max
VCC
-1.26
VCC
-1085
VCC
-880
VCC
-1025
VCC
-880
VCC
-1025
VCC
-955
VCC
-880
VCC
-1025
VCC
-880
mV
VCC
-1830
VCC
-1555
VCC
-1810
VCC
-1620
VCC
-1810
VCC
-1705
VCC
-1620
VCC
-1810
VCC
-1620
mV
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
mV
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
mV
VEE
+2.0
VEE
+2.0
VEE
+2.0
VEE
+0.8
VEE
+0.8
55
58
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5
VEE
+2.0
45
V
VEE
+0.8
VEE
+0.8
V
58
60
mA
AZ12000
AZ12001
AZ12001 (LVDS OUTPUT) DC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol
VBB
RPD
ICS
VHCTL
VLCTL
-40°C
Min
Max
VCC
VCC
-1.38
-1.26
Characteristic
Reference Voltage
0°C
Min
Max
VCC
VCC
-1.38
-1.26
REFIN Pull-Down resistor
to VBB
REFOUT
¯ ¯ ¯ ¯ ¯ ¯ ¯ Current Source
High level integrator output
Min
VCC
-1.38
85°C
Max
VCC
-1.26
Min
VCC
-1.38
Max
VCC
-1.26
Unit
V
470
Ω
4.0
ma
VCC
-1.0
Low level integrator output
Output HIGH Voltage
25°C
Typ
VCC
-1.31
V
VEE
+0.5
V
1
VOH
Q
Q̄
mV
Q
Q̄
mV
Output LOW Voltage1
VOL
Input HIGH Voltage,
PECL/ECL
VIH
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input LOW Voltage,
PECL/ECL
VIL
EXTVCO
EXTVCO
¯¯¯¯¯¯¯¯
Input HIGH Voltage,
TTL/CMOS
CPPOL
VIH
VCOSEL
DS2
DS1
Input HIGH Voltage,
TTL/CMOS
CPPOL
VIL
VCOSEL
DS2
DS1
ICC (IEE)
Power Supply Current
1. 100 Ω between outputs
January 2005 * REV - 3
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
VCC
-1165
VCC
-880
mV
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
VCC
-1810
VCC
-1475
mV
VEE
+2.0
VEE
+2.0
VEE
+0.8
VEE
+2.0
VEE
+2.0
V
VEE
+0.8
VEE
+0.8
VEE
+0.8
V
60
60
60
mA
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6
AZ12000
AZ12001
AZ 12000 (PECL OUTPUT) AC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol
AV1
Characteristic
Min
-40°C
Typ
Max
Min
Gain, REFIN to REFOUT
Output Impedance,
REFOUT
Phase Detector Gain
VCO frequency (Internal
or External)
Output Rise & Fall Times
(20% - 80%)
Q
¯Q¯
ZO
APD
fVCO
tr / tf
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
20
V/V
TBD
Ω
20.3
radians/V
800
MHz
120
120
ps
AZ12001 (LVDS OUTPUT) AC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol
AV1
ZO
APD
fVCO
tr / tf
Characteristic
Min
-40°C
Typ
Max
Min
Gain, REFIN to REFOUT
Output Impedance,
REFOUT
Phase Detector Gain
VCO frequency (Internal
or External)
Output Rise & Fall Times
(20% - 80%)
Q
Q̄
January 2005 * REV - 3
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
20
V/V
TBD
Ω
20.3
Radians/V
800
MHz
ps
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7
AZ12000
AZ12001
Internal Reference Oscillator
The PLL reference can be generated either with an internal oscillator or with an external source. In either case, the input
is the REFIN pin. This should be AC coupled since the input is internally biased to VBB. The REFOUT pin should be left
open when an external reference is used.
The exact topology of the crystal circuit will vary based on the resonant mode of the crystal. The circuit shown is for a
series resonant crystal. The AC gain between the REFIN and REFOUT pins is approximately 20. This value is sufficient
to overcome crystal matching network losses without phase noise degradation caused by an excessive drive level. An
internal current source on REFOUT eliminates the need for an external load resistor.
REFOUT
OUTPT
DRVR
4mA
VEE
(GROUND)
L3
REFIN
INPUT
RCVR
Y1
C4
GROUND
470 Ω
C3
VBB
VBB
Figure 1 Reference Oscillator
January 2005 * REV - 3
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8
AZ12000
AZ12001
Loop Filter Design
The combination of the phase detector, amplifier, VCO and divider form a second-order phase-locked loop. Proper
selection of the loop components is important to obtain stable, low jitter operation.
The loop bandwidth (or natural frequency, ωn) and damping factor (ζ) are the two major driving forces that define the
loop’s response to a disturbance. The value of ζ is typically 0.7 to ensure the fastest step response consistent with no
ringing. However in many oscillator application ζ may be 3 or higher to provide further phase noise reduction. ωn is
chosen as a compromise between settling time, VCO jitter and reference feedthrough. These values can be computed by
the following equations:
ωn =
ζ =
1
N
Kφ KVCO
τ1
τ 2ω n
2
τ 1 = R1C1
τ 2 = R2C1
K φ = Phase Detector Gain (20.3 radians/V)
KVCO = VCO Gain (radians/sec/volt)
N = Frequency Divisor value (4,8, 16 or 32)
The component definitions are shown in the figure below. R3 should be equal to R1 to minimize integrator offsets.
C1
R1
R2
R3
CPREF CPOUT
INTREF INTSUM
INTOUT
INTEGRATOR
CHARGE
PUMP
Figure 2 Charge Pump and Integrator
January 2005 * REV - 3
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9
VCO
CONTROL
VOLTAGE
AZ12000
AZ12001
Internal VCO
The internal VCO is designed for reliable, low jitter operation up to 800 MHz. It operates as a single terminal negative
impedance type circuit.
The tank circuit should have a minimum Q of 12 for reliable operation. The series combination of CV and C1 resonate
with L1 to set the operating frequency. The VCO control voltage is isolated through an inductor or resistor and changes
the varactor capacitance based on that control voltage. Note that the CPPOL pin should be tied high for internal VCO
operation since the tank frequency decreases with increasing control voltage.
VCOVCC
VARACTOR
VCO
CONTROL
VOLTAGE
TANK
CV
L2
R1
L1
C2
TANK
VCO
Figure 3 Internal VCO with Tank
External VCO
¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ pair is enabled. That input pair is
When VCOSEL is high, the internal VCO is disabled and the EXTVCO, EXTVCO
sine wave and PECL compatible.
The CPPOL pin sets the frequency slope polarity based on the operation of the external VCO. When CPPOL is low, the
charge pump generates pulses for an integrator and loop filter assuming the VCO frequency goes lower as the integrator
output voltage increases. When CPPOL is high, pulses are generated for a VCO in which the frequency goes higher as
the integrator output voltage increases.
January 2005 * REV - 3
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10
AZ12000
AZ12001
Application Circuit
A typical application circuit is shown in Figure 4. This drawing shows use of the internal reference oscillator and internal
VCO.
VCC
VARACTOR
C1
R1
TANK
CV
R2
L2
L1
C2
R3
CPPOL CPREF CPOUT
REFOUT
OUTPT
DRVR
4mA
INTREF INTSUM
INTOUT
INTEGRATOR
CHARGE
PUMP
TANK
AZ12000
AZ12001
VEE
L3
REFIN
INPUT
RCVR
Y1
C4
C3
470 Ω
VBB
VCOVCC,
VCC
VEE
F
MUX
MUX
DIVIDE BY
4,8,16,32
DS1
EXTVCO
EXTVCO
Q
Q
BUFFER
VBB
DS2
C4
0.01 µF
VCO
OUTPUT
VCO
PHASE/
FREQ
DETECT
VCOSEL
CONNECT TO VCC OR
GROUND FOR REQUIRED
DIVISION RATIO
GROUND
Figure 4. Typical Application with Crystal Reference and Internal VCO
January 2005 * REV - 3
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11
PECL OR
LVDS
OUTPUT
AZ12000
AZ12001
PACKAGE DIAGRAM
MLP 24
NOTES
1. DIMENSIONING AND TOLERANCING
CONFORM TO ASME T14-1994.
2. THE TERMINAL #1 AND PAD
NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012.
3. DIMENSION b APPLIES TO METALLIZED
PAD AND IS MEASURED BETWEEN 0.25
AND 0.30mm FROM PAD TIP.
4. COPLANARITY APPLIES TO THE
EXPOSED PAD AS WELL AS THE
TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.25 REF
0.18
0.30
3.90
4.10
2.65
2.95
3.90
4.10
2.65
2.95
0.50 BSC
0.35
0.45
0.25
0.10
0.10
January 2005 * REV - 3
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12
AZ12000
AZ12001
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
January 2005 * REV - 3
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13
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