MOTOROLA Order this document by MCM56824A/D SEMICONDUCTOR TECHNICAL DATA MCM56824A DSPRAM 8K x 24 Bit Fast Static RAM Single 5 V ± 10% Power Supply Fast Access and Cycle Times: 20/25/35 ns Max Fully Static Read and Write Operations Equal Address and Chip Enable Access Times Single Bit On–Chip Address Multiplexer Active High and Active Low Chip Enable Inputs Output Enable Controlled Three State Outputs High Board Density PLCC Package Low Power Standby Mode Fully TTL Compatible DQ6 DQ7 DQ8 VSS DQ9 DQ10 PIN NAMES A A0 – A11 . . . . . . . . . . . . . . . Address Inputs A12, X/Y . . . . . . . . . . Multiplexed Address V/S . . . . . . . . . Address Multiplexer Control W . . . . . . . . . . . . . . . . . . . . . . . Write Enable E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ23 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . +5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . No Connection B For proper operation of the device, all VSS pins must be connected to ground. REV 2 4/95 Motorola, Inc. 1995 MOTOROLA FAST SRAM PIN ASSIGNMENTS PLCC 7 6 5 4 3 2 1 52 51 50 49 48 47 46 8 45 9 44 10 43 11 42 12 41 13 40 14 39 15 38 16 37 17 36 18 35 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3334 10 C D E F G H J DSPRAM is a trademark of Motorola, Inc. 9 x 10 GRID 86 BUMP PBGA CASE 896A–01 DQ23 DQ22 DQ21 VSS DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 VSS DQ14 DQ13 DQ11 A9 A8 A7 A6 G VCC VSS E1 E2 W NC DQ12 • • • • • • • • • • FN PACKAGE 52–LEAD PLCC CASE 778–02 A10 A11 A12 X/Y V/S NC V CC A0 A1 A2 A3 A4 A5 The MCM56824A is a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic. The availability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically re–partitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control pin, such partitioning can occur with no additional components. This allows efficient utilization of the RAM resource irrespective of operand DQ0 type. See application diagrams at the end of this document for additionDQ1 al information. DQ2 Multiple power and ground pins have been utilized to minimize effects VSS induced by output noise. DQ3 The MCM56824A is available in a 52 pin plastic leaded chip–carrier DQ4 (PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA. DQ5 VIEW OF PBGA PACKAGE BOTTOM 9 8 7 6 5 4 3 2 D13 VSS D16 D17 D18 D20 D21 D23 W D12 D14 D15 E1 VSS 1 D19 VSS D22 A5 A4 E2 A3 A2 VSS A1 A0 VCC VCC G A6 V/S NC A7 A8 A12 X/Y A9 D11 D9 D8 D10 VSS D7 D6 D4 VSS D1 A10 A11 D5 D3 D2 D0 Not to Scale MCM56824A 1 BLOCK DIAGRAM V/S A12 X/Y 1 Q 0 2 TO 1 MUX A12 A0 VCC VSS • • • MEMORY ARRAY ROW DECODER A5 • • • 512 ROWS x 384 COLUMNS A10 A11 ••• DQ0 • • • • • • INPUT DATA CONTROL DQ23 E1 E2 • • • COLUMN I/O COLUMN DECODER ••• W G A6 A9 (LSB) (MSB) TRUTH TABLE E1 E2 G W V/S Mode Supply Current I/O Status H X X X X Not Selected ISB High–Z X L X X X Not Selected ISB High–Z L H H H X Output Disable ICC High–Z L H L H H Read Using X/Y ICC Data Out L H L H L Read Using A12 ICC Data Out L H X L H Write Using X/Y ICC Data In L H X L L Write Using A12 ICC Data In NOTE: X=don’t care. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.75 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 125 °C Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Storage Temperature NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM56824A 2 This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is assumed to be in a test socket or mounted on a printed circuit board with at least 300 LFPM of transverse air flow being maintained. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3 V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(i) — ± 1.0 µA Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout = 0 to VCC) Ilkg(O) — ± 1.0 µA — — — 260 220 180 Parameter * VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter AC Supply Current (G = VIH, E1 = VIL, E2 = VIH, Iout = 0 mA, All Other Inputs ≥ VIL = 0.0 V and VIH ≥ 3.0 V) MCM56824A–20 Cycle Time: ≥ 20 ns MCM56824A–25 Cycle Time: ≥ 25 ns MCM56824A–35 Cycle Time: ≥ 35 ns ICCA mA Standby Current (E1 = VIH, E2 = VIL, All Inputs = VIL or VIH) ISB1 — 15 mA CMOS Standby Current (E1 ≥ VCC – 0.2 V, E2 ≤ 0.2 V, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V) ISB2 — 10 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Typ Max Unit Cin 4 6 pF Cout 6 8 pF CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance All Pins Except DQ0 – DQ23 Input/Output Capacitance DQ0 – DQ23 +5V 480 Ω RL = 50 Ω OUTPUT OUTPUT 255 Ω Z0 = 50 Ω 5 pF VL = 1.5 V (a) (b) Figure 1. AC Test Loads MOTOROLA FAST SRAM MCM56824A 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted READ CYCLE TIMING (See Notes 1, 2, and 3) MCM56824A–20 Parameter MCM56824A–25 MCM56824A–35 Symbol Min Max Min Max Min Max Unit Read Cycle Time tAVAV 20 — 25 — 35 — ns Address Access Time tAVQV — 20 — 25 — 35 ns MUX Control Valid to Output Valid tVSVQV — 20 — 25 — 35 ns Chip Enable to Output Valid tE1LQV tE2HQV — 20 — 25 — 35 ns tGLQV — 8 — 10 — 15 ns tE1LQX tE2HQX 2 — 2 — 0 — ns 4, 5 Output Active from Output Enable tGLQX 0 — 0 — 0 — ns 5 Output Hold from Address Change tAXQX 4 — 5 — 5 — ns Output Hold from MUX Control Change tVSXQX 4 — 5 — 5 — ns Chip Enable to Output High–Z tE1HQZ tE2LQZ 0 10 0 15 0 15 ns Output Enable to Output Valid Output Active from Chip Enable Notes 4 4, 5 Output Enable High to Output High–Z tGHQZ 0 8 0 15 0 15 ns 5 NOTES: 1. A read cycle is defined by W high. 2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition. 3. Addresses valid prior to or coincident with E1 going low or E2 going high. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device. READ CYCLE tAVAV A (ADDRESS) tAVQV tAXQX V/S (MUX CONTROL) tVSVQV tVSXQX E1 (CHIP ENABLE) tE1HQZ tE1LQV tGLQV G (OUTPUT ENABLE) tGLQX Q (DATA OUT) tGHQZ HIGH–Z DATA VALID HIGH–Z tE1LQX MCM56824A 4 MOTOROLA FAST SRAM WRITE CYCLE TIMING (Write Enable Initiated, See Note 1) MCM56824A–20 Parameter Write Cycle Time Address Setup Time MCM56824A–25 MCM56824A–35 Symbol Min Max Min Max Min Max Unit tAVAV 20 — 25 — 35 — ns Notes tAVWL 0 — 0 — 0 — ns MUX Control Setup Time tVSVWL 0 — 0 — 0 — ns 2 Address Valid to End of Write tAVWH 15 — 20 — 30 — ns MUX Control Valid to End of Write tVSVWH 15 — 20 — 30 — ns Write Pulse Width tWLWH 15 — 15 — 20 — ns 3 Write Enable to Chip Enable Disable tWLE1H tWLE2L 15 — 15 — 20 — ns 3, 4 Chip Enable to End of Write tE1LWH tE2HWH 15 — 15 — 20 — ns 3, 4 Data Valid to End of Write tDVWH 8 — 10 — 15 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns 5 Write Recovery Time tWHAX 0 — 0 — 0 — ns 2 MUX Control Recovery Time tWHVSX 0 — 0 — 0 — ns Write High to Output Low–Z tWHQX 4 — 5 — 5 — ns 6 Write Low to Output High–Z tWLQZ 0 15 0 15 0 15 ns 6 NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. Write must be high for all address transitions. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device. WE INITIATED WRITE CYCLE tAVAV A (ADDRESS) tAVWH tWHAX V/S (MUX CONTROL) tVSVWH tE1LWH tWHVSX E1 (CHIP ENABLE) tVSVWL tWLWH W (WRITE ENABLE) tAVWL tDVWH tWHDX VALID DATA IN D (DATA IN) tWLQZ Q (DATA OUT) HIGH–Z tWHQX HIGH–Z tWLE1H MOTOROLA FAST SRAM MCM56824A 5 WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1) MCM56824A–20 Parameter MCM56824A–25 MCM56824A–35 Symbol Min Max Min Max Min Max Unit tAVAV 20 — 25 — 35 — ns tAVE1L tAVE2H 0 — 0 — 0 — ns 2 tVSVE1L tVSVE2H 0 — 0 — 0 — ns 2 tAVE1H tAVE2L 15 — 20 — 30 — ns 2 MUX Control Valid to End of Write tVSVE1H tVSVE2L 15 — 20 — 30 — ns 2 Chip Enable to End of Write tE1LE1H tE2HE2L 12 — 15 — 20 — ns 2, 3 Data Valid to End of Write tDVE1H tDVE2L 8 — 10 — 15 — ns 2 Data Hold Time tE1HDX tE2LDX 0 — 0 — 0 — ns 2, 4 Write Recovery Time tE1HAX tE2LAX 0 — 0 — 0 — ns 2 tE1HVSX tE2LVSX 0 — 0 — 0 — ns 2 Write Cycle Time Address Setup Time MUX Control Setup Time Address Valid to End of Write MUX Control Recovery Time Notes NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state. 4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time. E1 OR E2 INITIATED WRITE CYCLE tAVAV A (ADDRESS) tAVE1H tE1HAX V/S (MUX CONTROL) tVSVE1H E1 (CHIP ENABLE) W (WRITE ENABLE) tE1HVSX tE1LE1H tAVE1L tVSVE1L tDVE1H D (DATA IN) Q (DATA OUT) MCM56824A 6 tE1HDX DATA VALID HIGH–Z MOTOROLA FAST SRAM DSPRAM Multiplexed Vector/Scalar Address Maps DSP56001 DSP56001 MCM56824A A0 – A11 A12 X/Y 8K x 24 DSPRAM Used in Typical Application A0 – A11 MUX MCM56824A D0 – D23 D0 – D23 A0 – A11 A0 – A11 RAM A12 A15 X/Y A12 V/S X/Y WR W A12 V/S MEMORY MANAGEMENT PINS 4K x 24 “X” OPERANDS 8K x 24 “X” OPERANDS PROGRAM MEMORY HIGH 4K x 24 “Y” OPERANDS PROGRAM MEMORY LOW PROGRAM MEMORY V/S = “1” V/S = “0” ORDERING INFORMATION (Order by Full Part Number) MCM 56824A XX XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = rails) Part Number Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (FN = PLCC, ZP = PBGA) Full Part Numbers — MCM56824AFN20 MCM56824AFN25 MCM56824AFN35 MCM56824AZP20 MCM56824AZP25 MCM56824AZP35 MCM56824AZP20R2 MCM56824AZP25R2 MCM56824AZP35R2 MOTOROLA FAST SRAM MCM56824A 7 PACKAGE DIMENSIONS ZP PACKAGE 9 x 10 PBGA CASE 896A–01 0.20 (0.008) -T- B -B- 10 9 8 7 6 5 4 3 2 1 A G B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. C D N A DIM A B C D G L N R E F G H J R C MCM56824A 8 INCHES MIN MAX 0.637 0.644 0.697 0.703 0.053 0.068 0.028 0.031 0.060 BSC 0.073 0.096 0.544 0.559 0.602 0.617 G D 86 PL L -A- MILLIMETERS MIN MAX 16.36 16.16 17.88 17.68 1.73 1.33 0.81 0.69 1.524 BSC 2.44 1.84 14.20 13.80 15.69 15.29 0.50 (0.020) M T B S A S MOTOROLA FAST SRAM FN PACKAGE 52–LEAD PLCC CASE 778–02 D -L- T N M –P S L S –M S T N S –P S L S S –M S NOTE 1 Z1 W D 1 -P- G1 V A 0.25(0.010) S T L S –M S N S –P S R 0.25(0.010) S T L S –M S N S –P S VIEW D–D 0.25(0.010) S T N S –P S L S –M S 0.18(0.007) 0.18(0.007) M T L T N S –M –P S N L S –P –M S H F 0.18(0.007) 0.18(0.007) M T L T N S –M –P S N L S –P –M S Z X M S S S S K1 C E K 0.10 (0.004) 52 (NOTE 1) G -T- J SEATING PLANE DETAIL S 0.25(0.010) M 0.18(0.007) U -M- 52 LEADS ACTUAL (NOTE 1) 52 0.18(0.007) B Y BRK -N- S G 1 T L S –M S MOTOROLA FAST SRAM N S –P S M S S S S DETAIL S DIM A B C E F G H J K R U V W X Y Z G1 K1 Z1 MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 — 0.51 — 0.64 19.05 19.20 19.05 19.20 1.21 1.07 1.21 1.07 1.42 1.07 0.50 — 10° 2° 18.04 18.54 1.02 — 2° 10° INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.710 0.730 0.040 — 2° 10° NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. MCM56824A 9 Motorola reserves the right to make changes without further notice to any products herein. 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