MOTOROLA Order this document by MCM67H618B/D SEMICONDUCTOR TECHNICAL DATA Advance Information MCM67H618B 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self–Timed Write • • • • • • • • • • • Single 5 V ± 5% Power Supply Fast Access Times: 9/10/12 ns Max Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package ADSP Disabled with Chip Enable (E) — Supports Address Pipelining FN PACKAGE PLASTIC CASE 778–02 A6 A7 E UW LW ADSC ADSP ADV K G A8 A9 A10 PIN ASSIGNMENT 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 A5 A4 A3 A2 A1 A0 VSS VCC A15 A14 A13 A12 A11 The MCM67H618B is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals DQ9 except output enable (G) are clock (K) controlled through positive– DQ10 edge–triggered noninverting registers. VCC Bursts can be initiated with either address status processor (ADSP) VSS or address status cache controller (ADSC) input pins. Subsequent DQ11 burst addresses can be generated internally by the MCM67H618B DQ12 (burst sequence imitates that of the i486 and Pentium) and controlled DQ13 by the burst address advance (ADV) input pin. The following pages proDQ14 vide more detailed information on burst controls. VSS Write cycles are internally self–timed and are initiated by the rising VCC edge of the clock (K) input. This feature eliminates complex off–chip DQ15 write pulse generation and provides increased flexibility for incoming DQ16 DQ17 signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. PIN NAMES A0 – A15 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock ADV . . . . . . . . . . . . Burst Address Advance LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Upper Byte Write Enable ADSC . . . . . . . . . Controller Address Status ADSP . . . . . . . . . Processor Address Status E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ17 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground All power supply and ground pins must be connected for proper operation of the device. i486 and Pentium are trademarks of Intel Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 7/15/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM67H618B 1 BLOCK DIAGRAM (See Note) ADV BURST LOGIC INTERNAL A0′ ADDRESS Q0 BINARY COUNTER K A0 ADSP 64K x 18 MEMORY ARRAY A1′ Q1 CLR ADSC 16 A1 A1 – A0 2 ADDRESS REGISTER A0 – A15 A2 – A15 WRITE REGISTER UW LW 9 OUTPUT BUFFER 9 G DQ9 – DQ17 9 DATA–IN REGISTERS ENABLE REGISTER E DQ0 – DQ8 18 16 9 9 9 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting ADSP, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and ADSC are high, ADSP is ignored — the external address is not registered in this case. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW). BURST SEQUENCE TABLE (See Note) External Address A15 – A2 A1 A0 1st Burst Address A15 – A2 A1 A0 2nd Burst Address A15 – A2 A1 A0 3rd Burst Address A15 – A2 A1 A0 NOTE: The burst wraps around to its initial state upon completion. MCM67H618B 2 MOTOROLA FAST SRAM SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) E ADSP ADSC ADV UW or LW K Address Used Operation H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst H X H L L L–H Next Address Write Cycle, Continue Burst H X H L H L–H Next Address Read Cycle, Continue Burst H X H H L L–H Current Address Write Cycle, Suspend Burst H X H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation G I/O Status Read L Data Out Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 1.6 W Tbias – 10 to + 85 °C Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Temperature Under Bias Ambient Temperature TA 0 to +70 °C Storage Temperature Tstg – 55 to + 125 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA FAST SRAM MCM67H618B 3 DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.75 5.25 V Input High Voltage VIH 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Ilkg(I) — ± 1.0 µA Ilkg(O) — ± 1.0 µA ICCA — TBD mA CMOS Standby Supply Current (Device Deselected, Freq = 0, VCC = Max, All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) ISB2 — TBD mA Clock Running (Device Deselected, Freq = Max, VCC = Max, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) ISB4 — TBD mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 3.3 V Parameter * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) MCM67H618B–9 MCM67H618B–10 MCM67H618B–12 NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium bus cycles. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Symbol Typ Max Unit Input Capacitance Cin 4 5 pF Input/Output Capacitance CI/O 6 8 pF Parameter MCM67H618B 4 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4) MCM67H618B–9 MCM67H618B–10 MCM67H618B–12 S b l Symbol Min Max Min Max Min Max U i Unit Cycle Time tKHKH 15 — 16.6 — 20 — ns Clock Access Time tKHQV — 9 — 10 — 12 ns Output Enable to Output Valid tGLQV — 5 — 5 — 6 ns Clock High to Output Active tKHQX1 6 — 6 — 6 — ns Clock High to Output Change P Parameter tKHQX2 3 — 3 — 3 — ns Output Enable to Output Active tGLQX 0 — 0 — 0 — ns Output Disable to Q High–Z tGHQZ — 6 — 7 — 7 ns Clock High to Q High–Z tKHQZ 3 6 3 7 3 7 ns Clock High Pulse Width tKHKL 5 — 5 — 6 — ns Clock Low Pulse Width tKLKH 5 — 5 — 6 — ns N Notes 5 6 Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — 2.5 — 2.5 — ns 7 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — 0.5 — 0.5 — ns 7 NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles. 6. Transition is measured ± 500 mV from steady–state voltage. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled. Chip enable must be asserted at each rising edge of clock for the device (when ADSC is low) to remain enabled. OUTPUT Z0 = 50 Ω RL = 50 Ω VL = 1.5 V Figure 1. Test Load MOTOROLA FAST SRAM MCM67H618B 5 MCM67H618B 6 MOTOROLA FAST SRAM t EVKH t AVKH t ADSVKH t GLQX A1 SINGLE READ Q(A1) t KHQV t GLQV t KHEX t KHAX t KHKL t KLKH Q(A2) t KHQX2 t ADVVKH t WVKH A2 t ADSVKH t GHQZ t KHKH Q(A2 + 1) t KHQV t KHADVX t KHWX t KHADSX BURST READ Q(A2 + 2) Q(A2 + 3) Q(A2) (BURST WRAPS AROUND TO ITS INITIAL STATE) (ADV SUSPENDS BURST) NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address. DATA OUT G ADV E LW, UW ADDRESS ADSC ADSP K t KHADSX READ CYCLES Q(A2 + 1) Q(A2 + 2) t KHQZ MOTOROLA FAST SRAM MCM67H618B 7 DATA OUT DATA IN G ADV E LW, UW ADDRESS ADSC ADSP K BURST READ Q(An – 1) t EVKH t AVKH t ADSVKH Q(An) A1 A2 t KLKH t KHADSX SINGLE WRITE t GHQZ D(A1) t KHEX D(A2) D(A2 + 1) D(A2 + 3) ADSC STARTS NEW BURST D(A2 + 2) BURST WRITE (WITH A SUSPENDED CYCLE) D(A2 + 1) ADV SUSPENDS BURST W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST t KHAX t ADSVKH t KHKL t KHADSX t KHKH WRITE CYCLES D(A3) t DVKH t ADVVKH t WVKH A3 D(A3 + 2) NEW BURST WRITE D(A3 + 1) t KHDX t KHADVX t KHWX COMBINATION READ/WRITE CYCLE (E Low, ADSC High) tKHKH K tADSVKH tKHADSX tKHKL tKLKH ADSP tAVKH ADDRESS tKHAX A1 A2 A3 tWVKH tKHWX LW, UW tADVVKH tKHADVX ADV G tDVKH tKHQV DATA IN tGHQZ tKHQX2 tGLQX Q(A3) Q(A1) READ MCM67H618B 8 tGLQV D(A2) tKHQX1 DATA OUT tKHDX WRITE Q(A3 + 1) Q(A3 + 2) BURST READ MOTOROLA FAST SRAM APPLICATION EXAMPLE DATA BUS DATA ADDRESS BUS ADDRESS 16 72 CLOCK Pentium ADDR CLK K CACHE CONTROL LOGIC NA ADDR DATA K ADSC W MCM67H618BFN9 G E ADV ADSP ADS CONTROL 512K Byte Burstable, Secondary Cache Using Four MCM67H618BFN9s with a 66 MHz Pentium Figure 2. MOTOROLA FAST SRAM MCM67H618B 9 ORDERING INFORMATION (Order by Full Part Number) MCM 67H618B XX XX Motorola Memory Prefix Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns) Part Number Package (FN = PLCC) Full Part Numbers — MCM67H618BFN9 MCM67H618B 10 MCM67H618BFN10 MCM67H618BFN12 MOTOROLA FAST SRAM PACKAGE DIMENSIONS FN PACKAGE 52–LEAD PLCC CASE 778–02 0.007 (0.18) B Y BRK –N– M T L–M 0.007 (0.18) U M S N S T L–M S N S D Z –M– –L– W D 52 1 V A 0.007 (0.18) M T L–M S N S R 0.007 (0.18) M T L–M S N S E C 0.004 (0.100) –T– SEATING J VIEW S G PLANE G1 0.010 (0.25) T L–M S H N S 0.007 (0.18) M T L–M S N S K1 K F VIEW S MOTOROLA FAST SRAM S T L–M S N S VIEW D–D Z S G1 0.010 (0.25) X 0.007 (0.18) M T L–M S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.710 0.730 0.040 ––– MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 18.04 18.54 1.02 ––– MCM67H618B 11 Motorola reserves the right to make changes without further notice to any products herein. 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