Holt HI-8444 Arinc 429 line receiver Datasheet

HI-8444, HI-8445, HI-8448
Quad / Octal
ARINC 429 Line Receivers
December 2016
PIN CONFIGURATIONS
DESCRIPTION
The HI-8444 and HI-8445 are quad ARINC 429 line
receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.
The technology is analog / digital CMOS. The device is
designed to operate from either a 5V or 3.3V supply. Each
receiver channel translates incoming ARINC 429 data bus
signals to a pair of TTL / CMOS outputs.
The optional HI-8444-10, HI-8445-10 and HI-8448-10 are
designed to be used with an external 15 Kohm series
resistor. The “-10” devices meet the lightning protection
requirements of DO-160G, level 3, waveforms 3, 4, 5A, and
5B.
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. They force the receiver outputs to the
specified ZERO, ONE or NULL state. The ARINC inputs
are ignored when the device is in the test mode.
(See page 6 for additional pin configurations)
IN1 A
IN1 B
IN2 A
IN2 B
TESTA (8444 only)
TESTB (8444 only)
IN3 A
IN3 B
IN4 A
IN4 B
1
20
2
HI-8444PS
HI-8444PS-10
&
HI-8445PS
HI-8445PS-10
19
Quad
Receiver
14
3
4
5
6
7
8
18
17
16
15
13
9
12
10
11
OUT1 A
OUT1 B
OUT2 A
OUT2 B
VDD
VSS
OUT3 A
OUT3 B
OUT4 A
OUT4 B
20 Pin Plastic TSSOP package
The HI-8445 is identical to the HI-8444 except the TESTA
and TESTB pins are not available.
FEATURES
!
Direct ARINC 429 quad or octal line receivers in small
footprint packages
!
3.3V or 5.0V single supply operation
!
Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state
!
!
ARINC inputs are internally lightning protected per DO160G level 3 (-10 configuration only)
Hi-Rel processing options available
FUNCTION TABLE
ARINC INPUTS TESTA TESTB OUTA OUTB
INA - INB
-2.5 to +2.5 V
0
0
0
0
< -6.5 V
0
0
0
1
> +6.5 V
0
0
1
0
X
0
1
0
1
X
1
0
1
0
X
1
1
0
0
(DS8444 Rev. K)
IN1 AX
IN1 BX
IN1 AY
IN1 BY
IN2 AX
IN2 BX
IN2 AY
IN2 BY
TESTA (X)
TESTB (X)
TESTA (Y)
TESTB (Y)
IN3 AX
IN3 BX
IN3 AY
IN3 BY
IN4 AX
IN4 BX
IN4 AY
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1
38
2
37
3
36
4
35
5
34
6
33
32
7
8
9
HI-8448PS
HI-8448PS-10
12
30
29
10
11
31
Octal
Receiver
28
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
OUT1 AX
OUT1 BX
OUT1 AY
OUT1 BY
OUT2AX
OUT2 BX
OUT2 AY
OUT2 BY
VDD
VSS
OUT3 AX
OUT3 BX
OUT3 AY
OUT3 BY
OUT4 AX
OUT4 BX
OUT4 AY
OUT4 BY
IN4 BY
38 Pin Plastic TSSOP package
12/16
HI-8444, HI-8445, HI-8448
BLOCK DIAGRAMS
IN1 A
IN1 B
OUT1 A
OUT1 B
IN2 A
IN2 B
OUT2 A
OUT2 B
IN3 A
IN3 B
OUT3 A
OUT3 B
IN4 A
IN4 B
OUT4 A
OUT4 B
IN1 AX
IN1 BX
OUT1 AX
OUT1 BX
IN2 AX
IN2 BX
OUT2 AX
OUT2 BX
IN3 AX
IN3 BX
OUT3 AX
OUT3 BX
IN4 AX
IN4 BX
OUT4 AX
A
OUT4 BX
B
TESTA(X)
TESTB(X)
TESTA
TESTB
IN1 A
IN1 B
OUT1 A
OUT1 B
IN2 A
IN2 B
OUT2 A
OUT2 B
IN3 A
IN3 B
OUT3 A
OUT3 B
IN4 A
IN4 B
OUT4 A
OUT4 B
HI-8444
TESTA(Y)
TESTB(Y)
IN1 AY
IN1 BY
OUT1 AY
OUT1 BY
IN2 AY
IN2 BY
OUT2 AY
OUT2 BY
IN3 AY
IN3 BY
OUT3 AY
OUT3 BY
IN4 AY
IN4 BY
OUT4 AY
OUT4 BY
HI-8445
HI-8448
PIN DESCRIPTIONS (HI-8444, HI-8445)
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
IN1 A
ARINC input
Receiver 1 positive input
2
IN1 B
ARINC input
Receiver 1 negative input
3
IN2 A
ARINC input
Receiver 2 positive input
4
IN2 B
ARINC input
Receiver 2 negative input
5
TESTA
Logic input
6
TESTB
Logic input
7
IN3 A
ARINC input
Receiver 3 positive input
8
IN3 B
ARINC input
Receiver 3 negative input
9
IN4 A
ARINC input
Receiver 4 positive input
10
IN4 B
ARINC input
Receiver 4 negative input
11
OUT4 B
Logic output
Receiver 4 "ZERO" output
12
OUT4 A
Logic output
Receiver 4 "ONE" output
13
OUT3 B
Logic output
Receiver 3 "ZERO" output
14
OUT3 A
Logic output
Receiver 3 "ONE" output
15
VSS
Power
Ground
16
VDD
Power
Positive supply voltage 3.3V or 5.0 V
17
OUT2 B
Logic output
Receiver 2 "ZERO" output
18
OUT2 A
Logic output
Receiver 2 "ONE" output
19
OUT1 B
Logic output
Receiver 1 "ZERO" output
20
OUT1 A
Logic output
Receiver 1 "ONE" output
Test input. (Not available on HI-8445)
Test input. (Not available on HI-8445)
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HI-8444, HI-8445, HI-8448
PIN DESCRIPTIONS (HI-8448)
PIN
FUNCTION
RECEIVER SET
DESCRIPTION
IN1 AX
ARINC input
X
Receiver 1 positive input
IN1 BX
ARINC input
X
Receiver 1 negative input
IN1 AY
ARINC input
Y
Receiver 1 positive input
IN1 BY
ARINC input
Y
Receiver 1 negative input
IN2 AX
ARINC input
X
Receiver 2 positive input
IN2 BX
ARINC input
X
Receiver 2 negative input
IN2 AY
ARINC input
Y
Receiver 2 positive input
Receiver 2 negative input
IN2 BY
ARINC input
Y
TESTA(X)
Logic input
X
Test input
TESTB(X)
Logic input
X
Test input
TESTA(Y)
Logic input
Y
Test input
TESTB(Y)
Logic input
Y
Test input
IN3 AX
ARINC input
X
Receiver 3 positive input
IN3 BX
ARINC input
X
Receiver 3 negative input
IN3 AY
ARINC input
Y
Receiver 3 positive input
IN3 BY
ARINC input
Y
Receiver 3 negative input
IN4 AX
ARINC input
X
Receiver 4 positive input
IN4 BX
ARINC input
X
Receiver 4 negative input
IN4 AY
ARINC input
Y
Receiver 4 positive input
IN4 BY
ARINC input
Y
Receiver 4 negative input
OUT4 BY
Logic output
Y
Receiver 4 "ZERO" output
OUT4 AY
Logic output
Y
Receiver 4 "ONE" output
OUT4 BX
Logic output
X
Receiver 4 "ZERO" output
OUT4 AX
Logic output
X
Receiver 4 "ONE" output
OUT3 BY
Logic output
Y
Receiver 3 "ZERO" output
OUT3 AY
Logic output
Y
Receiver 3 "ONE" output
OUT3 BX
Logic output
X
Receiver 3 "ZERO" output
OUT3 AX
Logic output
X
VSS
Power
VDD
Power
OUT2 BY
Logic output
Receiver 3 "ONE" output
Ground supply
Positive supply voltage 3.3V or 5.0 V
Y
Receiver 2 "ZERO" output
OUT2 AY
Logic output
Y
Receiver 2 "ONE" output
OUT2 BX
Logic output
X
Receiver 2 "ZERO" output
OUT2 AX
Logic output
X
Receiver 2 "ONE" output
OUT1 BY
Logic output
Y
Receiver 1 "ZERO" output
OUT1 AY
Logic output
Y
Receiver 1 "ONE" output
OUT1 BX
Logic output
X
Receiver 1 "ZERO" output
OUT1 AX
Logic output
X
Receiver 1 "ONE" output
HOLT INTEGRATED CIRCUITS
3
HI-8444, HI-8445, HI-8448
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Logic input voltage range
ARINC input voltage
Solder Temperature (reflow)
Storage Temperature
-0.3 V to +7 V
-0.3 V to +5.5 V
-120 V to + 120 V
260°C
-65°C to +150°C
Supply Voltage
VDD .................................. 3.0 V to 5.5 V
Operating Temperature Range
Industrial Screening .........
-40°C to +85°C
Hi-Temp Screening ........
-55°C to +125°C
NOTE: Stresses above absolute maximum ratings or
outside recommended operating conditions may cause
permanent damage to the device. These are stress
ratings only. Operation at the limits is not recommended.
ELECTRICAL CHARACTERISTICS
VDD = 5.0V ± 5% or 3.3V ± 5%, VSS = 0V, TA = Operating Temperature Range (unless or otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
ONE or ZERO
VDIN
Differential input voltage
6.5
10
NULL
VNIN
Differential input voltage
13
V
2.5
Common mode
VCOM
With respect to GND
±5.0
V
V
INA to INB
RDIFF
Supplies floating
30
75
KW
Input to VSS or VDD
RSUP
Supplies floating
19
40
KW
0.5
1.0
ARINC INPUTS
Input voltage
Input resistance
Input hysteresis
VHYS
Input capacitance
5
V
ARINC differential
CAD
10
pF
ARINC single ended to VSS
CAS
10
pF
High
VIH
Low
VIL
Sink
IIH
VIH=2.0V
Source
IIL
VIL=0.8V
-1.0
µA
VOH
IOH=-5mA, VDD=5.0V
2.4
V
IOH=-4mA, VDD=3.3V
2.4
TEST INPUTS
Logic input voltage
Logic input current
2.0
V
0.8
V
200
µA
OUTPUTS
Logic output voltage
High
Low
Logic output voltage (CMOS)
VOL
V
IOL=5mA, VDD=5.0V
0.4
V
IOL=4mA, VDD=3.3V
0.4
V
High
VOHC
IOH=-100µA
Low
VOLC
IOL=100µA
IDD
HI-8444, HI-8445
HI-8448
tLH
CL=50 pF
600
tHL
CL=50 pF
600
Output rise time
tR
10% to 90%
50
80
ns
Output fall time
tF
90% to 10%
50
80
ns
VDD-0.2
V
VSS+0.2
V
5.5
10
mA
11
20.0
mA
SUPPLY CURRENT
VDD current
SWITCHING CHARACTERISTICS (TA = 25 °C)
Propagation delay
Propagation delay
IN to OUT
TEST to OUT
ns
ns
tTOH
50
ns
tTOL
50
ns
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HI-8444, HI-8445, HI-8448
TIMING DIAGRAMS
IN A
TEST A
/
TEST B
IN B
tTOH
tLH
OUT A
OUT B
1.5V
tHL
tLH
tHL
1.5V
OUT A
/
OUT B
tTOL
1.5V
1.5V
ARINC 429 Receiver Timing
Test Mode Timing
INTERNAL LIGHTNING PROTECTION (-10 Only)
The HI-8444-10, HI-8445-10 and HI-8488-10 are similar to the
“non -10” configurations with the exception that an external
15 Kohm resistor must be added in series with each ARINC input
in order to properly detect the ARINC 429 specified input
thresholds. This option is especially useful in applications where
external lightning protection circuitry is required.
The HI-8444-10, HI-8445-10 and HI-8448-10 will meet the
requirements of DO-160G, Level 3, waveforms 3, 4, 5A and 5B
with the 15 Kohm series resistors in place.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightening protection of Holt
Line Drivers and Receivers.
HOLT INTEGRATED CIRCUITS
5
HI-8444, HI-8445, HI-8448
ORDERING INFORMATION
HI - 844xxx x x - xx
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
35 Kohm
-10
25 Kohm
PART
NUMBER
Blank
F
PART
NUMBER
0
15 Kohm
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
PART
NUMBER
TEST
PINS
PACKAGE
DESCRIPTION
8444PS
20 PIN PLASTIC TSSOP (20HS)
Yes
8445PS
20 PIN PLASTIC TSSOP (20HS)
No
8448PQ
44 PIN PLASTIC QUAD FLAT PACK PQFP (44PTQS)
Yes
8448PS
38 PIN PLASTIC TSSOP (38HS)
Yes
8448PC
44 PIN PLASTIC CHIP-SCALE, LPCC (44PCS)
Yes
44
43
42
41
40
39
38
37
36
35
34
-
44
43
42
41
40
39
38
37
36
35
34
IN2 AX
IN1 BY
IN1 AY
IN1 BX
IN1 AX
N/C
OUT1 AX
OUT1 BX
OUT1 AY
OUT1 BY
OUT2 AX
- IN2 AX
- IN1 BY
- IN1 AY
- IN1 BX
- IN1 AX
- N/C
- OUT1 AX
- OUT1 BX
- OUT1 AY
- OUT1 BY
- OUT2 AX
ADDITIONAL PIN CONFIGURATIONS
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
HI-8448PC
HI-8448PC-10
Octal
Receiver
33
32
31
30
29
28
27
26
25
24
23
-
OUT2 BX
OUT2 AY
OUT2 BY
N/C
VDD
N/C
VSS
N/C
OUT3 AX
OUT3 BX
OUT3 AY
IN2 BX - 1
IN2 AY - 2
IN2 BY - 3
N/C - 4
TESTA(X) - 5
TESTB(X) - 6
TESTA(Y) - 7
TESTB(Y) - 8
IN3 AX - 9
IN3 BX - 10
IN3 AY - 11
HI-8448PQ
HI-8448PQ-10
Octal
Receiver
33 - OUT2 BX
32 - OUT2 AY
31 - OUT2 BY
30 - N/C
29 - VDD
28 - N/C
27 - VSS
26 - N/C
25 - OUT3 AX
24 - OUT3 BX
23 - OUT3 AY
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
IN3 BY - 12
IN4 AX - 13
IN4 BX - 14
IN4 AY - 15
IN4 BY - 16
N/C - 17
OUT4 BY - 18
OUT4 AY - 19
OUT4 BX - 20
OUT4 AX - 21
OUT3 BY - 22
IN3 BY
IN4 AX
IN4 BX
IN4 AY
IN4 BY
N/C
OUT4 BY
OUT4 AY
OUT4 BX
OUT4 AX
OUT3 BY
-
12
13
14
15
16
17
18
19
20
21
22
IN2 BX
IN2 AY
IN2 BY
N/C
TESTA(X)
TESTB(X)
TESTA(Y)
TESTB(Y)
IN3 AX
IN3 BX
IN3 AY
44-Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
6
HI-8444, HI-8445, HI-8448
REVISION HISTORY
Revision
Date
DS8444, Rev. G
05/30/08
Page Description of Change
1
1
5
5
6
7
8
Rev. H
Rev. I
Rev. J
05/25/10
10/17/13
11/04/13
Rev. K
12/05/16
Changed “10 Kohm”, “DO-160C/D”, and “and 5A” in second paragraph of the
Description to “15 Kohm”, DO-160E”, and “5A, and 5B” respectively.
Changed “DO-160C/D” in fourth Feature bullet to “DO160E”.
Changed “10 Kohm” in second and third paragraphs and in the Required
Series Resistance of the Ordering information to “15 Kohm”.
Changed “DO-160D” and “4 and 5A” in third paragraph to “DO-160E” and
“4, 5A, and 5B” respectively.
Added Revision History page as new page 6.
Renumbered page 6 as page 7
Replaced the 44-Pin Plastic Quad Flat Pack (PQFP) drawing with new
drawing.
Added new package configurations for HI-8448PSx and HI-8448PCx.
Update PQFP and QFN package drawings.
Update QFN-44, QFP-44, TSSOP-38 and TSSOP-20 package drawings.
Update DO-160E to DO-160G rev. number in text.
Update Absolute Maximum Ratings Table. .
HOLT INTEGRATED CIRCUITS
7
HI-8444, HI-8445, HI-8448 PACKAGE DIMENSIONS
20-PIN PLASTIC TSSOP
millimeters(inches)
Package Type: 20HS
6.500 ± 0.100
(0.256 ± .004)
6.400 ± 0.150
(0.252 ± 0.006)
0.145 ± 0.055
(0.006 ± 0.002)
4.400 ± 0.100
(0.173 ± 0.004)
Pin 1
See Detail A
0.220 ± 0.050
(0.0087 ± 0.002)
0.925 ± 0.125
(0.036 ± 0.005)
0.650
BSC
(0.026)
0° to 8°
0.100 ± 0.050
(0.004 ± 0.002)
0.600 ± 0.150
(0.024 ± 0.006)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
millimeters (inches)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PMQS
0.230 MAX.
(0.009)
0.80
BSC
(0.031)
10.000 BSC
(0.394
SQ.
13.200 BSC
(0.520)
SQ.
0.370 ± 0.080
(0.015 ± 0.003)
0.880 ± 0.150
(0.035 ± 0.006)
1.60
typ
(0.063)
0.20
min
(0.008)
See Detail A
2.70
MAX.
(0.106)
2.00 ± 0.20
(0.079 ± 0.008)
0.30
R MAX.
(0.012)
0.13
R MIN. Detail A
(0.005)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
8
0° £ Q £ 7°
HI-8444, HI-8445, HI-8448 PACKAGE DIMENSIONS
38-PIN PLASTIC TSSOP
millimeters (inches)
Package Type: 38HS
9.700 ± 0.100
(0.382 ± 0.004)
6.400 ± 0.150
(0.252 ± 0.006)
0.145 ± 0.055
(0.006 ± 0.002)
4.400 ± 0.100
(0.173 ± 0.004)
Pin 1
See Detail A
0.220 ± 0.050
(0.0087 ± 0.002)
0.925 ± 0.125
(0.036 ± 0.005)
0.500
BSC
(0.0197)
0° to 8°
0.100 ± 0.050
(0.004 ± 0.002)
0.600 ± 0.150
(0.024 ± 0.006)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Detail A
millimeters (inches)
Package Type: 44PCS
7.00
BSC
(0.276)
5.50 ± 0.050
(0.217 ± 0.002)
0.50 BSC
(0.0197)
7.00
BSC
(0.276)
5.50 ± 0.050
(0.217 ± 0.002)
Top View
Bottom
View
0.25 ± 0.050
(0.010 ± 0.002)
1.00
max
(0.039)
0.200 typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Electrically isolated heat
sink pad on bottom of
package
Connect to any ground or
power plane for optimum
thermal dissipation
HOLT INTEGRATED CIRCUITS
9
0.400 ± 0.050
(0.016 ± 0.002)
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