Central CMLDM7003JE Surface mount dual n-channel enhancement-mode silicon mosfet Datasheet

CMLDM7003E
CMLDM7003JE
ENHANCED SPECIFICATION
SURFACE MOUNT
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE
FEATURES
• ESD protected up to 2kV
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Maximum Pulsed Drain Current
Power Dissipation (Note 1)
Power Dissipation (Note 2)
Power Dissipation (Note 3)
Operating and Storage Junction Temperature
Thermal Resistance
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DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM7003E
and CMLDM7003JE are Enhancement-mode
N-Channel Field Effect Transistors, manufactured
by the N-Channel DMOS Process, designed for high
speed pulsed amplifier and driver applications. The
CMLDM7003E utilizes the USA pinout configuration,
while the CMLDM7003JE utilizes the Japanese pinout
configuration. These special Dual Transistor devices
offer low drain-source on state resistance (rDS(ON))
and ESD protection up to 2kV.
MARKING CODES: CMLDM7003E: C73
CMLDM7003JE: C7J
SYMBOL
VDS
VDG
VGS
ID
IDM
PD
PD
PD
TJ, Tstg
ΘJA
UNITS
V
V
V
mA
A
mW
mW
mW
°C
°C/W
50
50
12
280
1.5
350
300
150
-65 to +150
357
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
VGS=5.0V
50
♦ IGSSF, IGSSR
VGS=10V
0.5
♦ IGSSF, IGSSR
VGS=12V
1.0
♦ IGSSF, IGSSR
IDSS
VDS=50V, VGS=0
50
BVDSS
VGS=0, ID=10μA
50
VGS(th)
VDS=VGS, ID=250μA
0.49
1.2
VSD
VGS=0, IS=115mA
1.4
VGS=1.8V, ID=50mA
1.6
2.3
♦ rDS(ON)
♦ rDS(ON)
VGS=2.5V, ID=50mA
1.3
1.9
♦ rDS(ON)
VGS=5.0V, ID=50mA
1.1
1.5
gFS
VDS=10V, ID=200mA
200
Crss
VDS=25V, VGS=0, f=1.0MHz
5.0
Ciss
VDS=25V, VGS=0, f=1.0MHz
50
Coss
VDS=25V, VGS=0, f=1.0MHz
25
UNITS
nA
μA
μA
nA
V
V
V
Ω
Ω
Ω
mS
pF
pF
pF
♦ Enhanced specification
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2
R2 (18-January 2010)
CMLDM7003E
CMLDM7003JE
ENHANCED SPECIFICATION
SURFACE MOUNT
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7003E (USA Pinout)
CMLDM7003JE (Japanese Pinout)
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: C73
MARKING CODE: C7J
R2 (18-January 2010)
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