LSI LS7534 Dimmer light switch with up and down control Datasheet

UL
LSI/CSI
®
LS7534, LS7535
LS7535FT
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
DIMMER LIGHT SWITCH
WITH UP AND DOWN CONTROLS
Nov. 2009
PIN ASSIGNMENT - TOP VIEW
FEATURES:
DESCRIPTION:
LS7534 and LS7535 are MOS integrated circuits
that are designed for brightness control of incandescent lamps. The outputs of these ICs control
the brightness of a lamp by controlling the firing angle of a triac connected in series with the lamp. All
internal timings are synchronized with the line frequency by means of a built-in phase-lock loop circuit. The output occurs once every half-cycle of the
line frequency. Within the half-cycle, the output can
be positioned anywhere between 159° conduction
angle for maximum brightness and 41° conduction
angle for minimum brightness in relation to the AC
line frequency. The positioning of the output is controlled by applying the proper logic levels at the UP
and DOWN inputs.
These functions may be implemented with very few
interface components which is described in the application examples (See Fig. 5A and 5B). For touch
plates, LS7534 is used (Fig. 5A). For pushbutton
switches, LS7535 is used (Fig. 5B).
In the following Operating Description of the application examples, an Activation is Touch for LS7534
and Switch Closure for LS7535.
7535-111109-1
1
DOZE
2
CAP
3
SYNC
4
LS7534
APPLICATION:
LS7535 is ideal for use in electronic dimmers for
“smart-house” type applications because it is designed
to be easily controlled by remote switches.
V SS (+V)
LSI
• Phase-lock loop synchronization allows use
as a Wall Switch
• Brightness control of incandescent lamps with touch
plates (LS7534) or pushbutton switches (LS7535)
• Dual Controls eliminate confusion
• Soft turn-on /turn-off
• Controls the "Duty Cycle" from 23% to 88%
(conduction angles for AC half-cycles between 41°
and 159°, respectively)
• Operates at 50Hz/60Hz line frequency
• Input for slow dimming
• +12V to +18V DC supply voltage (VSS - VDD)
• LS7534, LS7535, LS7535FT (DIP); - See Figure 1
LS7534-S, LS7535-S, LS7535FT-S (SOIC)
8
TRIG
7
V DD (-V )
6
DOWN
5
UP
FIGURE 1
Short Activation (34ms to 325ms)
UP - When the lamp is off, if a short activation is applied to
the UP input, the lamp brightness is ramped up to full-on or
to a previous brightness stored in the memory. The rampup time from off to full-on is 2.8 sec. The ramp-up time from
off to any other brightness is proportionally shorter. When
the lamp is on at any brightness, a short activation applied
to the UP input has no effect.
DOWN - If a short activation is applied to the DOWN input,
the lamp brightness is ramped down to off. The ramp-down
time from full-on to off is 5.6 seconds. The ramp-down time
from any other brightness is proportionally shorter. When
the lamp is off, a short activation applied to the DOWN input
has no effect.
Long Activation (Greater than 334ms)
UP - If a long activation is applied to the UP input, the lamp
brightness ramps up from the pre-activation brightness as
long as the activation is maintained or until the full brightness is reached. At full brightness any continued long activation has no further effect.
DOWN - If a long activation is applied to the DOWN input,
the lamp brightness is ramped down as long as the long activation is maintained or until the minimum brightness is
reached. At minimum brightness, any continued long activation has no further effect. When the lamp is off, a long
activation applied to the DOWN input has no effect.
LS7535FT NOTE
LS7535FT ramp-up and ramp-down times are instantaneous.
Otherwise, it functions the same as LS7535.
TABLE 1
INPUT
UP
DOWN
UP/DOWN SIGNAL DURATION
SHORT
34ms to 325 ms
LONG
More than 334ms
PRE-ACTIVATION
BRIGHTNESS
POST-ACTIVATION
BRIGHTNESS
PRE-ACTIVATION
BRIGHTNESS
POST-ACTIVATION
BRIGHTNESS
Off
Off
Increases from Min.
Max.
Memory **
(See Note 1)
No Change
Max.
No change
Intermediate
No Change
Intermediate
Increases from pretouch brightness
Off
No Change
Off
No change
Max.
Off *
Max.
Decreases from Max.
Intermediate
Off *
Intermediate
Decreases from pretouch brightness
* 5.6 second ramp-down from max. to off. Ramp-down time from any other brightness is proportionally shorter.
** 2.8 second ramp-up from off to max.
NOTE 1: "Memory" refers to the brightness stored in the memory. The brightness is stored in memory when the
lamp is turned off by a short activation. First time after power-up, a short activation produces max. brightness.
INPUT/OUTPUT DESCRIPTION:
VSS (Pin 1)
Supply voltage positive terminal.
UP (Pin 5)
This input controls the turn-on and the conduction angle, ø ,
of the TRIG output. A description of this is provided in the
DOZE (Pin 2)
DESCRIPTION and TABLE 1. For LS7534, a logic low level
A clock applied to this input causes the brightness to de- is the active level whereas for LS7535 a logic high level is
crease in equal increments with each negative transition the active level. LS7535 has an internal pull-down resistor
of the clock. Eventually, when the lamp becomes off, this of about 500k Ohms on this input.
input has no further effect. The lamp can be turned on
again by activating the UP input. For the transition from DOWN (Pin 6)
maximum brightness to off, a total of 83 clock pulses are This input controls the turn-off and the conduction angle, ø,
needed at the DOZE input.
of the TRIG output. A description of this is provided in the
When either the UP or the DOWN input is active, the DESCRIPTION and TABLE 1. For LS7534, a logic low level
DOZE input is disabled.
is the active level, whereas for LS7535 a logic high level is
the active level. LS7535 has an internal pull-down resistor
CAP (Pin 3)
of about 500k Ohms on this input.
The CAP input is for external component connection for
the PLL filter capacitor. A capacitor of 0.047µF ± 20% VDD (Pin 7)
should be used at this input.
Supply voltage negative terminal.
SYNC (Pin 4)
The AC line frequency (50Hz/60Hz), when applied to this
input, synchronizes all internal timings through a phase
lock loop. The signal for this input may be obtained from
the line voltage by employing the circuit arrangement
shown in the application examples.
7535-012703-2
TRIG (Pin 8)
The TRIG output provides a low level pulse occurring every
half-cycle of the SYNC signal. The conduction angle, ø, of
the TRIG output can be varied within the range of 41o to
159o by means of either the UP or the DOWN input.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
DC supply voltage
Any input voltage
Operating temperature
Storage temperature
SYMBOL
VSS - VDD
VIN
TA
TSTG
VALUE
+20
VSS - 20 to VSS + 0.5
0 to +80
-65 to +150
UNIT
V
V
°C
°C
DC ELECTRICAL CHARACTERISTICS:
(TA = 25°C, all voltages referenced to VDD)
PARAMETER
Supply voltage
Supply current
SYMBOL
VSS
ISS
MIN
+12
-
TYP
1.2
MAX
+18
1.7
UNIT
V
mA
VIZL
VIZH
VIRL
VIRH
VIOL
VIOH
0
VSS - 2
0
VSS - 5.5
0
VSS - 2
-
VSS - 6
VSS
VSS - 9.5
VSS
VSS - 8
VSS
V
V
V
V
V
V
-
Input Current:
SYNC, UP, DOWN HI
IIH
-
-
110
uA
SYNC, UP, DOWN LO
DOZE HI
DOZE LO
IIL
IIH
IIL
-
-
100
100
100
nA
nA
nA
With Series 1.5MΩ
Resistor to
115 VAC Line
-
VOH
VOL
IOS
50
VSS
VSS - 8
-
-
V
V
mA
Input Voltages:
DOZE LO
DOZE HI
SYNC LO
SYNC HI
UP, DOWN LO
UP, DOWN HI
TRIG HI
TRIG LO
TRIG Sink Current
CONDITIONS
VSS = +15V,
Output off
VSS = +15V
VSS = +15V,
VOL = VSS - 4V
TRANSIENT CHARACTERISTICS (See Fig. 2 and 3)
(All timings are based on fs = 60Hz, unless otherwise specified.)
PARAMETER
SYNC frequency
UP, DOWN duration (SHORT)
UP, DOWN duration (LONG)
ø ramp time, off to max
(UP,SHORT)
ø ramp time, min to max
(UP,LONG)
ø ramp time, max to min
(DOWN,SHORT)
ø ramp time, max to min
(DOWN,LONG)
TRIG pulse width
TRIG conduction angle (See Note)
DOZE frequency
SYMBOL
fs
Ts1
Ts2
TUS
MIN
40
34
334
-
TYP
2.8
MAX
70
325
infinite
-
UNIT
Hz
ms
ms
sec
TUL
-
3.6
-
sec
TDS
-
5.6
-
sec
TDL
-
3.6
-
sec
TW
ø
fD
41
0
33
-
159
500
µs
degrees
Hz
NOTE: The phase delay caused by the typical RC network used between SYNC input and the AC line (See Fig. 5A and
Fig. 5B) reduces the effective ø values by 8°.
7535-012703-3
SYNC
ø
OUT
TW
TW
FIGURE 2. OUTPUT CONDUCTION ANGLE, ø
TS2
TS1
TS2
TS1
UP
TS2
TS1
DOWN
TS1
334ms
TUS
200
ø 150
(Degrees) 100
50
0
TUL
TDS
334ms
TDL
334ms
0
B
A
C
4
8
GH
F J
K
E
D
12
16
0
4
8
M
L
12
0
4
M
8
12
16
20
SECONDS
FIGURE 3. OUTPUT CONDUCTION ANGLE, ø, vs UP/DOWN INPUTS
Note 1. UP/DOWN input polarity shown is for LS7534. For LS7535, the polarity is reversed.
Note 2. Points A, D, E and K correspond to minimum brightness, where ø = 41°.
Points B, C, G and H correspond to maximum brightness, where ø = 159°.
Points denoted by M correspond to an arbitrary intermediate brightness.
Note 3. Points F, J and L correspond to ø = 64°. The ramp-up or ramp-down rate of ø changes at these points
(upon long activation only) indicated by the discontinuity of the slopes. The interval E to F or J to K,
in terms of time and angle, are 934ms and 23°, respectively.
7535-012703-4
24
SYNC
4
CAP
3
DOZE
2
BUF
PHASE
LOCK
LOOP
BRIGHTNESS
MEMORY
BUF
DOWN
6
BUF
UP
5
BUF
V SS
1
(+V)
V DD
7
(-V)
DIGITAL
COMPARATOR
CONTROL
LOGIC
OUTPUT
DRIVER
Ø
POINTER
FIGURE 4
LS7534/LS7535 BLOCK DIAGRAM
APPLICATION EXAMPLES:
Typical dimmer light switch circuit schematics are shown in Fig. 5A (LS7534) and
Fig. 5B (LS7535). The brightness of the lamp is set by touching the UP and DOWN
touch plates in Fig. 5A and closure of the UP and DOWN switches in Fig. 5B. The
functions of different components are as follows:
•
•
•
•
•
•
Z, D1, R1, C2 and C5 produce the 15V DC supply for the chip.
R2 and C4 filter and current limit the AC signal for the SYNC input.
C3 is the filter capacitor for the internal PLL.
C1 and L are RFI filters.
In Fig. 5A, R3 and R4 set the touch sensitivity of the UP and DOWN inputs.
In Fig. 5B, R3 limits the current between Vss and the UP and DOWN inputs upon
closure of a switch.
• The resistor and diode connected between the chip output and the triac gate
provides current limiting and isolation for the chip. The resistor is R5 in Fig. 5A
and R4 in Fig. 5B.
• In Fig. 5B, PCB layout may cause triac switching transients to be coupled to the Up
or Down input which can have the effect of having a Long switch closure “lock-up”
at a certain phase angle output. In this case, capacitors C6 and C7 must be added
as shown.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7535-012703-5
8
TRIG
FIGURE 5A. TYPICAL LS7534 DIMMER LIGHT SWITCH
P
R5
G
MT1
R3
+
T
-
Z
MT2
R4
C5
D2
DOWN
D1
L
115VAC
OR
220VAC
R4
C1
8
C2
7
TRIG
R2
V DD DOWN UP
SEE NOTE 1
B
LOAD
C3
DOWN
TOUCH
PLATE
UP
TOUCH
PLATE
V DD
V SS DOZE CAP SYNC
2
3
1
4
A
R4
5
6
LS7534
R1
R4
C4
UP
R3
SEE NOTE 2
DZ
V SS
N
NOTES: 1) When DOZE circuit is used, break Pin 1 to Pin 2 connection.
2) Use Connection A when Neutral is not available. Use Connection B when Neutral is available.
115VAC
C1 = 0.15µF, 200V
R4 = 2.7MΩ, 1/4W
C2 = See C2 Value Table
R5 = See R5 Value Table
C3 = 0.047µF, 25V
D1, D2 = IN4148
C4 = 470pF, 25V
Z = 15V, 1W (Zener)
C5 = 47µF, 25V
T = Q4004L4 Triac (Typical)
(1) R1 = 270Ω, 1W
L = 100µH (RFI Filter)
R2 = 1.5MΩ, 1/4W
R3 = 1MΩ to 5MΩ, 1/4W (Select for sensitivity)
(1) For Connection A. Use 1/4 W for Connection B.
C2 VALUE TABLE
C2 = 0.33µF, 200V, Connection A
R5 VALUE TABLE
R5 = 100Ω, 1/4W, 25mA Triac Gate
220VAC
C1 = 0.15µF, 400V
R4 = 4.7MΩ, 1/4W
C2 = See C2 Value Table
R5 = See R5 Value Table
C3 = 0.047µF, 25V
D1, D2 = IN4148
C4 = 470pF, 25V
Z = 15V, 1W (Zener)
C5 = 47µF, 25V
T = Q5004L4 Triac (Typical)
L = 200µH (RFI Filter)
(2) R1 = 1kΩ, 2W
R2 = 3.3ΜΩ, 1/4W
R3 = 1MΩ to 5MΩ, 1/4W (Select for sensitivity)
(2) For Connection A. Use 1/4W for Connection B.
C2 VALUE TABLE
C2 = 0.22µF, 400V, Connection A
C2 = 0.10µF, 400V, Connection B
7535-111109-6
R5 VALUE TABLE
R5 = 100Ω, 1/4W, 25mA Triac Gate
R5 = 50Ω, 1/4W, 50mA Triac Gate
DOZE
CIRCUIT
FIG. 6A
FIGURE 5B. TYPICAL LS7535 DIMMER LIGHT SWITCH
P
SEE NOTE 3
R4
G
R3
C6
DOWN
MT1
C7.
+
T
-
Z
MT2
C5
D2
DOWN
UP
D1
115VAC
OR
220VAC
C1
L
8
C2
7
TRIG
6
5
V DD DOWN
UP
LS7535
R1
R2
1
V DD
V SS DOZE CAP SYNC
2
3
4
UP
DOZE
CIRCUIT
FIG. 6B
A
SEE NOTE 1
B
LOAD
C3
C4
DZ
SEE NOTE 2
V SS
N
NOTES: 1) When DOZE circuit is used, break Pin 1 to Pin 2 connection.
2) Use Connection A when Neutral is not available. Use Connection B when Neutral is available .
3) C6 and C7 may be required in some PCB layouts to eliminate coupling from triac circuitry.
115VAC
C1 = 0.15µF, 200V
C2 = See C2 Value Table
C3 = 0.047µF, 25V
C4 = 470pF, 25V
C5 = 47µF, 25V
C6, C7 = 0.001µF, 25V
(1) R1 = 270Ω, 1W
R2 = 1.5MΩ, 1/4W
R3 = 27kΩ, 1/4W
R4 = See R4 Value Table
D1, D2 = IN4148
Z = 15V, 1W (Zener)
T = Q4004L4 Triac (Typical)
L = 100µH (RFI Filter)
(1) For Connection A. Use 1/4W for Connection B.
C2 VALUE TABLE
C2 = 0.33µF, 200V, Connection A
C2 = 0.22µF, 200V, Connection B
R4 VALUE TABLE
R4 = 100Ω, 1/4W, 25mA Triac Gate
R4 = 50Ω, 1/4W, 50mA Triac Gate
220VAC
C1 = 0.15µF, 400V
C2 = See C2 Value Table
C3 = 0.047µF, 25V
C4 = 470pF, 25V
C5 = 47µF, 25V
C6, C7 = 0.001µF, 25V
(2) R1 = 1kΩ, 2W
R2 = 3.3MΩ, 1/4W
R3 = 27kΩ, 1/4W
R4 = See R4 Value Table
D1, D2 = IN4148
Z = 15V, 1W (Zener)
T = Q5004L4 Triac (Typical)
L = 200µH (RFI Filter)
(2) For Connection A. Use 1/4 W for Connection B.
C2 VALUE TABLE
C2 = 0.22µF, 400V, Connection A
C2 = 0.10µF, 400V, Connection B
7535-111109-7
R4 VALUE TABLE
R4 = 100Ω, 1/4W, 25mA Triac Gate
R4 = 50Ω, 1/4W, 50mA Triac Gate
3.3M
V SS
3.3M
V SS
330K
Sense
3.3M
3.3M
UP
4093
330K
UP
4093
DN
MP58098
4093
IN914
4093
IN914
+
4093
-
DZ
4093
DN
10µF
4093
DOZE
SWITCH
3.3M
DZ
Sense
4093
+
- 10µF
DOZE
SWITCH
V DD
V DD
NOTE: All Resistors 1/4W, all Capacitors 25V
FIGURE 6A.
NOTE: All Resistors 1/4 W, all Capacitors 25V.
FIGURE 6B.
DOZE CIRCUIT FOR LS7534
DOZE CIRCUIT: (Figures 6A and 6B)
The Doze circuits shown generate a slow clock (0.04Hz) at
the DZ terminal. If the UP/DOWN inputs (Figures 5A and
5B) are not activated, the Sense node of the Doze circuit
sits at a logic high level. A momentary pressing of the
Doze switch sets the SR flip-flop, enabling the oscillator.
Every negative transition of the clock (DZ terminal) causes
the lamp brightness to be reduced by equal increments, until eventurally the lamp is shut- off.
DOZE CIRCUIT FOR LS7535
When the lamp is off, the oscillator has no further effect on
the dimmer circuit. When the lamp is turned on again by
activating the UP input, the SR flip-flop is reset and the DZ
clock is turned off.
When the Doze circuit is used, the connection between
DOZE input (Pin 2) and Vss (Pin 1), as shown in Figures
5A and 5B, should be removed.
FIGURE 7. OPERATING DESCRIPTION OF A FULL-FEATURE LS7535 WALL SWITCH
ON
See Application Note
AN 705 for the Schematic
DIM UP
OFF
DIM DOWN
DUAL CONTROL CONTINUOUS
DIMMER WITH UNIQUE
DELAYED OFF FEATURE
AUTO DIM
INITIAL CONDITION
Off
Off
On
On
On
On
Auto-Dimming
Auto-Dimming
Auto-Dimming
Auto-Dimming
Auto-Dimming
Auto-Dimming
ACTION
SHORT PRESS On
LONG PRESS On
LONG PRESS On
LONG PRESS Off
SHORT PRESS Off
PRESS Auto-Dim
SHORT PRESS On
LONG PRESS On
SHORT PRESS Off
LONG PRESS Off
PRESS Auto-Dim
None
RESULT
“Softly” turns On to memory intensity (1)
Varies from min. intensity towards max. intensity (2)
Varies towards max. intensity (2)
Varies towards min. intensity (3)
“Softly” turns Off
Begins auto-dimming to off (4)
“Softly” returns to memory intensity (5)
Varies towards max. intensity (2)
“Softly “ turns off
Varies towards min. intensity (3)
No change
Auto-dims to Off
(1) Last intensity achieved before turn off is stored as memory intensity.
(2) On (Dim Up) varies intensity towards maximum and stops there.
(3) Off (Dim Down) varies intensity towards minimum and stops there.
(4) Auto-dimming period controlled by RC components and intensity level when Auto-Dim is activated.
(5) Last intensity achieved before Auto-Dim started is stored as memory intensity.
7535-012703-8
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