ON MC10176FN Hex d master/slave flip-flop Datasheet

MC10176
Hex D Master/Slave
Flip-Flop
The MC10176 contains six high-speed, master slave type “D”
flip-flops. Clocking is common to all six flip-flops. Data is entered
into the master when the clock is low. Master to slave data transfer
takes place on the positive-going Clock transition. Thus, outputs may
change only on a positive-going Clock transition. A change in the
information present at the data (D) input will not affect the output
information any other time due to the master-slave construction of this
device.
• PD = 460 mW typ/pkg (No Load)
• ftoggle = 150 MHz (typ)
• tr, tf = 2.0 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
LOGIC DIAGRAM
D0
5
D1
2
6
D2
7
D3
10
MC10176L
AWLYYWW
3
4
MC10176P
AWLYYWW
Q0
1
PLCC–20
FN SUFFIX
CASE 775
Q1
A
WL
YY
WW
Q2
1
10176
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
D4
13 Q3
11
VCC1
1
16
VCC2
Q0
2
15
Q5
Q1
3
14
Q4
Q2
4
13
Q3
D0
5
12
D5
D1
6
11
D4
D2
7
10
D3
VEE
8
9
CLOCK
14 Q4
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
CLOCK
D5
9
12
15 Q5
CLOCKED TRUTH TABLE
C
D
Qn+1
L
X
Qn
H*
L
L
H*
H
H
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
*A clock H is a clock transition
from a low to a high state.
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Package
Shipping
MC10176L
CDIP–16
25 Units / Rail
MC10176P
PDIP–16
25 Units / Rail
MC10176FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10176/D
MC10176
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
IE
8
121
IinH
5
9
350
495
IinL
5
9
0.5
0.5
Input Current
–30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
88
110
Min
121
mAdc
220
310
220
310
µAdc
0.5
0.5
µAdc
0.3
0.3
Output Voltage
Logic 1
VOH
2
15
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
15
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
15
–1.080
–1.080
Threshold Voltage
Logic 0
VOLA
2
15
–0.980
–0.980
–0.910
–0.910
–1.655
–1.655
–1.630
–1.630
Vdc
–1.595
–1.595
Switching Times (50Ω Load)
Clock Input
Propagation Delay
Vdc
ns
t9+2+
t9+2–
2
2
1.6
1.6
4.6
4.6
1.6
1.6
4.5
4.5
1.6
1.6
5.0
5.0
Rise Time
(20 to 80%)
t2+
2
1.0
4.1
1.1
4.0
1.1
4.4
Fall Time
(20 to 80%)
t2–
2
1.0
4.1
1.1
4.0
1.1
4.4
Setup Time
tsetup
2
2.5
2.5
2.5
ns
Hold Time
thold
2
1.5
1.5
1.5
ns
Toggle Frequency (Max)
ftog
2
125
125
125
MHz
Output level to be measured after a clock pulse has been applied to the C Input (Pin 9)
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2
150
VIHmax
VILmin
MC10176
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
Characteristic
Power Supply Drain Current
Input Current
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Symbol
Pin
Under
Test
IE
8
IinH
5
9
IinL
5
9
VILmin
VEE
(VCC)
Gnd
8
1, 16
8
8
1, 16
1, 16
8
8
1, 16
1, 16
8
8
1, 16
1, 16
8
8
1, 16
1, 16
8
8
1, 16
1, 16
5
12
8
8
1, 16
1, 16
Pulse In
Pulse Out
–3.2 V
+2.0 V
VIHAmin
VILAmax
5
9
Logic 1
VOH
2
15
Output Voltage
Logic 0
VOL
2
15
Threshold Voltage
Logic 1
VOHA
2
15
Threshold Voltage
Logic 0
VOLA
2
15
(50Ω Load)
VIHmax
5
9
Output Voltage
Switching Times
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
5
12
5
12
5
12
+1.11Vdc
+0.31V
Clock Input
Propagation Delay
t9+2+
t9+2–
2
2
5, 9
5, 9
2
2
8
8
1, 16
1, 16
Rise Time
(20 to 80%)
t2+
2
5, 9
2
8
1, 16
Fall Time
(20 to 80%)
t2–
2
5, 9
2
8
1, 16
Setup Time
tsetup
2
5, 9
2
8
1, 16
Hold Time
thold
2
5, 9
2
8
1, 16
Toggle Frequency (Max)
ftog
2
8
1, 16
Output level to be measured after a clock pulse has been applied to the C Input (Pin 9)
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10176
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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4
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10176
PACKAGE DIMENSIONS
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
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5
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
MC10176
Notes
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6
MC10176
Notes
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7
MC10176
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8
MC10176/D
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