MOTOROLA MPC17550EV

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MPC17550
Rev 1.0, 03/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
17550
Quad H-Bridge Micromotor Driver
with DC/DC Boost Converter
Freescale Semiconductor, Inc...
The 17550 is a monolithic quad H-Bridge power IC ideal for portable
electronic applications containing tiny bipolar stepper motors and/or brush
DC-motors powered by two-to-four cell NiCd/NiMH batteries.
QUAD H-BRIDGE MICROMOTOR
DRIVER WITH DC/DC BOOST
CONVERTER
The 17550 operates from 2.5 V to 5.5 V, with independent control of each
H-Bridge via parallel 3.0 V or 5.0 V logic-compatible I/O. The device features
an on-board DC/DC boost converter that allows motor operation all the way
down to 1.6 V (the boost converter supplies the gate-drive voltage for each of
the four independent H-bridge output stages). Each output bridge has its own
gate-drive and logic circuitry with built-in shoot-through current protection.
The 17550 has four operating modes: Forward, Reverse, Brake, and
Tri-Stated (High Impedance). The 17550 has a low total RDS(ON) of 1.2 Ω max
@ 25°C. In addition, it can be set into a very low current-drain standby mode.
The H-Bridge outputs can be independently PWM’ed at up to 200 kHz for
speed/torque and current control. The 17550 can efficiently drive many types
of micromotors owing to its low output resistance and high output slew rates.
EV (Pb-FREE) SUFFIX
CASE 1522-01
36-LEAD VMFP
Features
• Low Total RDS(ON) 0.7 Ω (Typ), 1.2 Ω (Max) @ 25°C
•
•
•
•
•
•
•
ORDERING INFORMATION
Output Current 700 mA (Continuous per Output)
Shoot-Through Current Protection Circuit
PWM Control Input Frequency up to 200 kHz
Built-In DC/DC Boost Converter
Low Power Consumption Standby Mode
Undervoltage Detection and Shutdown Circuit
Pb-Free Packaging Designated by Suffix Code EV
Device
Temperature
Range (TA)
Package
MPC17550EV/EL
-10°C to 60°C
36 VMFP
Simplified Application Diagram
17550 Simplified Application Diagram
VM
VDD
17550
VDD
VM
LX
OE
PSB
MCU
VG
INAF
INAR
HBAF
HBAR
INBF
INBR
HBBF
HBBR
INCF
INCR
HBCF
HBCR
INDF
INDR
HBDF
HBDR
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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GND
LX
VG
VDD
VDD
VDD
DC/DC
Converter
PSB
VDD
VG
HBA
VMA
HBAF
INAF
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AGND
HBAR
INAR
PGND
HBB
INBF
VMB
INBR
HBBF
HBBR
VDD
OE
Control
Logic
Gate
Driver
and
Level
Shifter
PGND
HBC
VMC
HBCF
HBCR
INCF
PGND
INCR
HBD
VMD
INDF
HBDF
INDR
HBDR
PGND
Figure 1. 17550 Simplified Internal Block Diagram
17550
2
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AGND
NC
PSB
OE
VMA
HBAF
PGND
HBAR
VMA
VMB
HBBR
PGND
HBBF
VMB
INAR
INAF
INBF
INBR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VG
VDD
LX
GND
VMC
HBCF
PGND
HBCR
VMC
VMD
HBDR
PGND
HBDF
VMD
INCR
INCF
INDF
INDR
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
1
AGND
Analog Ground
2
NC
No Connect
3
PSB
Power Standby
Power standby mode control terminal.
4
OE
Output Enable
Logic output Enable control of H-Bridges (Low = True).
5, 9
VMA
Motor Drive Power Supply A
6
HBAF
HBA Forward Output
Forward output of H-Bridge A.
8
HBAR
HBA Reverse Output
Reverse output of H-Bridge A.
10, 14
VMB
Motor Drive Power Supply B
11
HBBR
HBB Reverse Output
7, 12, 25, 30
PGND
Power Ground
13
HBBF
HBB Forward Output
15
INAR
Input Control HBA Reverse
16
INAF
Input Control HBA Forward
Control signal input for H-Bridge A forward.
17
INBF
Input Control HBB Forward
Control signal input for H-Bridge B forward.
18
INBR
Input Control HBB Reverse
Control signal input for H-Bridge B reverse.
19
INDR
Input Control HBD Reverse
Control signal input for H-Bridge D reverse.
20
INDF
Input Control HBD Forward
Control signal input for H-Bridge D forward.
21
INCF
Input Control HBC Forward
Control signal input for H-Bridge C forward.
22
INCR
Input Control HBC Reverse
Control signal input for H-Bridge C reverse.
23, 27
VMD
Motor Drive Power Supply D
Power supply voltage connection for Motor “D” (top of HBD).
24
HBDF
HBD Forward Output
Forward output of H-Bridge D.
26
HBDR
HBD Reverse Output
Reverse output of H-Bridge D.
28, 32
VMC
Motor Drive Power Supply C
29
HBCR
HBC Reverse Output
Reverse Output of H-Bridge C.
31
HBCF
HCB Forward Output
Forward Output of H-Bridge C.
Definition
Analog and logic signal ground reference terminal.
No connection to this terminal.
Power supply voltage connection for Motor “A” (top of HBA).
Power supply voltage connection for Motor “B” (top of HBB).
Reverse output of H-Bridge B.
Power ground connection.
Forward output of H-Bridge B.
Control signal input for H-Bridge A reverse.
Power supply voltage connection for Motor “C” (top of HBC).
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal
Name
Formal Name
33
GND
Ground
34
LX
DC/DC Converter Switching
Transistor Output
35
VDD
Logic Supply
36
VG
Gate-Driver Circuit Power
Supply
Definition
Control circuit ground terminal for DC/DC circuit ground.
Open-drain output of the internal DC/DC converter circuit.
Control circuit power supply terminal.
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Input terminal for the gate-drive voltage.
17550
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
Motor Supply Voltage
VM
-0.5 to 9.0
V
Gate-Driver Circuit Power Supply Voltage
VG
VDD -0.5 to 14
V
Logic Supply Voltage
VDD
-0.5 to 6.0
V
Signal Input Voltage (Note 1)
VIN
-0.5 to VDD +0.5
V
IO
0.7
IOPK
2.0
Human Body Model (Note 4)
VESD1
±2000
Machine Model (Note 5)
VESD2
±100
TSTG
-65 to 150
°C
Operating Ambient Temperature
TA
-10 to 60
°C
Operating Junction Temperature
TJ
-10 to 150
°C
RθJA
TBD
°C/W
PD
1500
mW
TSOLDER
260
°C
A
Driver Output Current
Continuous (Note 2)
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Peak (Note 3)
V
ESD Voltage
Storage Temperature Range
Thermal Resistance (Note 6)
Power Dissipation (Note 7)
Soldering Temperature (Note 8)
Notes
1. VIN is the voltage level applied to any input terminal.
2. IO is measured as the load current flowing through the H-bridge.
3.
TA = 25°C, pulse width < 10 ms at intervals > 0.2 seconds.
4.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5.
6.
7.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
Mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
Maximum at TA = 25°C.
8.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 2.5 V, GND = 0 V, fIN = 176 kHz unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Motor Supply Voltage
VM
1.6
2.5
5.5
V
Logic Supply Voltage
VDD
2.5
3.0
5.5
V
–
–
1.0
–
–
1.0
–
0.3
1.0
mA
µA
POWER
Standby Power Supply Current (Note 9)
I
Motor Supply Standby Current
I
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Logic Supply Standby Current
VMSTBY
VDDSTBY
IV
Logic Supply Current
DD
µA
Gate Driver Circuit Power Supply Current (Note 10)
Standby (PSB = “L”)
IDDC0
–
–
1.0
No Signal Operating
IDDCN
–
1.0
3.0
µA
Input Signal Operating (Note 11)
IDDC
–
19
25
mA
Driver Output ON Resistance (Note 12)
RDS(ON)
–
0.7
1.2
Ω
VG
10
11.5
13
V
VIN
0
–
VDD
V
High-Level Input Voltage
VIH
VDD x 0.7
–
–
V
Low-Level Input Voltage
VIL
–
–
VDD x 0.3
V
High-Level Input Current
IIH
–
–
1.0
µA
-1.0
–
–
µA
GATE DRIVE
Gate Driver Circuit Power Supply Voltage (Note 13)
CONTROL LOGIC
Logic Input Voltage (Note 14)
Logic Input (F, R, PSB, OE)
IIL
Low-Level Input Current
Notes
9. Applies individually to each H-Bridge.
10. Average inductor current for DC/DC converter (connected between VDD and LX [L = 1.0 mH, C = 2.2 µF]).
11.
12.
Full drive (input signal to all input terminals).
The total H-bridge ON resistance when VG is 11.5 V.
13.
14.
When voltage is supplied externally without built-in DC/DC.
VIN is the voltage level applied to any input.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 2.5 V, GND = 0 V, fIN = 176 kHz unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f IN
–
–
200
kHz
f OSC
–
100
200
kHz
t VGON
–
10
20
ms
Turn-ON Time
t PLH
–
0.2
1.0
Turn-OFF Time
t PHL
–
0.2
1.0
INPUT
Pulse Input Frequency (Note 15)
Internal Oscillator Frequency
OUTPUT
Gate Driver Circuit Power Supply Wake-Up Time
µs
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Propagation Delay Time
Notes
15. fIN is the signal frequency applied to an input terminal (F, R).
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Timing Diagrams
2.1 V
VIH
F, R,
PSB
VIL
10 V
50%
FO, RO
VG
tPLH
tVGON
Figure 2. DC/DC Converter Output Waveform
Freescale Semiconductor, Inc...
50%
tPHL
Figure 3. H-Bridge Output Waveform
Table 1. Truth Table
PSB, OE
INA/INB/INC/IND
HBA/HBB/HBC/HBC
PSB
OE
IN*F
IN*R
HB*F
HB*R
H
L
L
L
L
L
H
L
L
H
L
H
H
L
H
L
H
L
H
L
H
H
Z
Z
H
H
X
X
Z
Z
L
X
X
X
Z
Z
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
* = A, B, C, or D.
17550
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 17550 is a monolithic quad H-Bridge ideal for portable
electronic applications containing multiple bipolar step motors
and/or brush DC motors. The device features an on-board DC/
DC converter to provide gate-drive voltages, as well as levelshifting circuitry. The control logic translates the input signals
to the gate-driver circuitry while providing cross-conduction
suppression.
The 17550 has four operating modes: Forward, Reverse,
Brake, and Tri-Stated (High Impedance). The MOSFETs
comprising the output bridge have a total source+sink RDS(ON)
≤ 1.2 Ω.
The 17550 can simultaneously drive four brush DC motors
or two bipolar step motors. The drivers are designed to be
PWM’ed at frequencies up to 200 kHz.
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FUNCTIONAL TERMINAL DESCRIPTION
VDD
VM
The VDD terminal carries the logic supply voltage and
current into the logic sections of the IC. VDD has an
undervoltage threshold. If the supply voltage drops below the
undervoltage threshold, the output power stage switches to a
tri-state condition. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input terminals.
The VM terminals carry the main supply voltage and current
into the power sections of the 17550. This supply then
becomes controlled and/or modulated by the 17550 as it
delivers the power to the loads attached between the H-Bridge
output terminals. All VM terminals must be connected together
on the printed circuit board.
INAF, INAR, INBF, INBR, INCF, INCR, INDF, INDR
These logic input terminals control each H-Bridge output;
e.g., IN*F logic HIGH = HB*F HIGH; likewise, IN*R logic HIGH
= HB*R HIGH. However, if both “F” and “R” inputs are taken
HIGH, the associated bridge’s outputs are both tri-stated (refer
to Table 1, Truth Table, page 8).
OE
OE terminal is a LOW = TRUE enable input. When
OE = HIGH, all H-Bridge outputs are tri-stated (high
impedance) regardless of logic inputs states.
LX
The LX terminal is the open-drain output of the internal DC/
DC converter circuit. It is the junction for the external inductor
and the anode of the external Schottky diode.
VG
The VG terminal is the input terminal for the gate-drive
voltage. It can be supplied from the built-in DC/DC converter
or from an external source.
Ground Terminals
All ground terminals must be tied together on the PCB.
HBAF, HBAR, HBBF, HBBR, HBCF, HBCR, HBDF,
HBDR
These terminals provide connection to the outputs of each
of the internal H-Bridges (see Figure 1, 17550 Simplified
Internal Block Diagram, page 2).
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APPLICATIONS
Introduction
To attain high-efficiency operation, the rectifier should be a
Schottky diode, and the filter capacitor should be of the low
ESR type. Attention should be paid to proper switch mode
power supply PCB layout practice. Some experimentation may
be required to determine optimal external component values.
The recommended starting values are L = 1.0 mH, C = 2.2 µF.
The 17550's built-in DC/DC converter must be connected to
an external inductor, rectifier, and filter capacitor. This step-up
converter generates the gate-drive voltage, VG, required by the
internal gate driver circuits. Although there is some latitude in
selecting the values for the external component, care must be
taken that VG does not exceed 14 V. Additionally, too low an
inductance will cause large instantaneous switching currents,
which may damage the device.
The DC/DC converter includes its own internal oscillator and
does not require an external clock input.
Typical Application
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Important Do not use an inductance lower than 330 µH.
VM = 2.5 V
47 µF
A typical application schematic is shown in Figure 4.
VDD = 3.0 V
17550
VM
VDD
10 µF
L = 1.0 mH
LX
OE
PSB
VG
2.2 µF
INAF
INAR
HBAF
HBAR
N
S
MCU
INBF
HBBF
INBR
HBBR
INCF
HBCF
INCR
HBCR
N
S
HBDF
INDF
INDR
HBDR
GND
Figure 4. Typical 17550 Application
17550
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CEMF Snubbing Techniques
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a capacitor or zener at the motor
supply voltage terminal (VM) (see Figure 5).
5.0 V
5.0 V
175XX
VDD
VM
C1L
C1L
C1H
C1H
C2L
C2H
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5.0 V
5.0 V
175XX
VDD
VM
CRES
OUT
OUT
GND
C2L
C2H
CRES
OUT
OUT
GND
Figure 5. CEMF Snubbing Techniques
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PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
36-LEAD VMFP
PLASTIC PACKAGE
CASE 1522-01
ISSUE O
1.90
1.70
1.20±0.10
5
36
19
B
1.35±0.10
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NPJ
IA
5.40
5.20
(JPN)/CAVITY #(A1)
BOTTOM SIDE
3
4
1.20±0.10
4X R0.40±0.10
18
1
1.30±0.10
VIEW Y
12.70
12.50
3
VIEW K
4
A
12˚±1˚
2X
R0.15±0.10
12˚±1˚
36X
0.10 C
0.25
1.90
1.70
GUAGE PLANE
SEATING PLANE
14˚±1˚
2X
R0.15±0.10
0.20
0.00
C
0.27
36X
0.37
0.13 M
14˚±1˚
0˚- 8˚
0.60±0.20
C A B
0.69±0.20
4
0.37
0.27
0.13 M
R
VIEW K
VIEW ROTATED 90˚ CW
C A B
R
BASE METAL
0.325
0.27 (0.20)
0.15
34X
0.65
VIEW Y
PLATING
(0.30)
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DIMENSIONS DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.5 MM PER END. DIMENSION DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.5 MM PER SIDE.
4. DIMENSIONS ARE DETERMINED AT THE OUTMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE PLASTIC
BODY.
5. TERMINAL NUMBERS ARE SHOWN FOR REFERNCE
ONLY.
SECTION R-R
17550
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NOTES
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13
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NOTES
17550
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NOTES
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MPC17550