MOTOROLA Order this document by MPC2002/D SEMICONDUCTOR TECHNICAL DATA 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC – Based Systems The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0 – PD2 are reserved for density and speed identification. MPC2002 MPC2003 (Formerly MCM72MS32/64) 136–LEAD DIMM CASE 1104–01 TOP VIEW 1 • PowerPC–style Burst Counter on Board • Dual Readout SIMM for Circuit Density 34 35 • Single 5 V ± 5% Power Supply • All Inputs and Outputs are TTL Compatible • Three State Outputs • Byte Parity • Byte Write Capability • Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz • Decoupling Capacitors for each Fast Static RAM 68 • High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes • I/Os are 3.3 V Compatible BurstRAM is a trademark of Motorola. PowerPC and PowerPC 601 are trademarks of International Business Machines Corp. 5/95 Motorola, Inc. 1995 MOTOROLA FAST SRAM MPC2002•MPC2003 1 PIN ASSIGNMENT 136–LEAD DIMM CASE 1104–01 TOP VIEW PD2 PD1 PD0 Cache Size Module VSS NC NC 512KB MPC2003SG66/60 VSS NC VSS 512KB MPC2003SG50 VSS VSS NC 256KB MPC2002SG66/60 VSS VSS VSS 256KB MPC2002SG50 PIN NAMES A0 – A15 . . . . . . . . . . . . . . . . . . . . . . Address Inputs K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W0 – W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable DQ0 – DQ63 . . . . . . . . . . Cache Data Input/Output DQP0 – DQP7 . . . . . . . . . Data Parity Input/Output TSC . . . . . . . . . . . . . . . . . . Transfer Start Controller TSP . . . . . . . . . . . . . . . . . Transfer Start Processor BAA . . . . . . . . . . . . . . . . . . Burst Address Advance PD0 – PD2 . . . . . . . . . . . . . . . . . . Presence Detect VCC . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground PD0 PD1 DQ0 DQ1 VCC DQ4 DQ6 DQP0 DQ8 DQ10 VSS K0 VSS DQ14 VCC DQ16 DQ17 DQ19 DQ21 VCC DQP2 DQ24 DQ26 DQ28 VSS DQ31 DQP3 VSS W0 W2 TSP BAA VCC W4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 VSS PD2 VCC DQ2 DQ3 DQ5 DQ7 VSS DQ9 DQ11 DQ12 VSS DQ13 DQ15 DQP1 VSS DQ18 DQ20 DQ22 DQ23 VSS DQ25 DQ27 DQ29 DQ30 VSS E0 W1 W3 G0 TSC VSS G1 W5 W6 DQ32 DQ33 VSS DQ36 DQ38 DQ39 DQ40 VCC DQ43 DQ45 DQ46 DQP5 VSS K1 VSS DQ52 DQ53 DQ55 DQP6 VCC DQ58 DQ60 DQ62 DQP7 A0 A2 A4 A6 A8 A10 A12 A14 VSS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 W7 E1 DQ34 DQ35 DQ37 VCC DQP4 DQ41 DQ42 DQ44 VSS DQ47 DQ48 DQ49 VSS DQ50 DQ51 DQ54 DQ56 VSS DQ57 DQ59 DQ61 DQ63 VCC A1 A3 A5 A7 NC A9 A11 A13 A15* * This pin on the MPC2002 is a No Connect (NC) MPC2002•MPC2003 2 MOTOROLA FAST SRAM MPC2003 (64K x 72) MODULE BLOCK DIAGRAM 16 A0 – A15 MCM67M618 A0 – A15 LW W0 8 TSP TSP DQ0 – DQ7 TSC TSC DQ8 BAA BAA UW DQ0 – DQ7 DQP0 W1 8 K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ8 – DQ15 DQP1 MCM67M618 A0 – A15 LW W2 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ16 – DQ23 DQP2 W3 8 K DQ9 – DQ16 G DQ17 DQ24 – DQ31 DQP3 E MCM67M618 A0 – A15 LW W4 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ32 – DQ39 DQP4 W5 8 K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ40 – DQ47 DQP5 MCM67M618 A0 – A15 LW W6 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ48 – DQ55 DQP6 W7 8 K DQ9 – DQ16 G DQ17 DQ56 – DQ63 DQP7 E MOTOROLA FAST SRAM MPC2002•MPC2003 3 MPC2002 (32K x 72) MODULE BLOCK DIAGRAM A15 A0 – A14 NC 15 MCM67M518 A0 – A14 LW W0 8 TSP TSP DQ0 – DQ7 TSC TSC DQ8 BAA BAA UW DQ0 – DQ7 DQP0 W1 8 K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ8 – DQ15 DQP1 MCM67M518 A0 – A14 LW W2 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ16 – DQ23 DQP2 W3 8 K DQ9 – DQ16 G DQ17 DQ24 – DQ31 DQP3 E MCM67M518 A0 – A14 LW W4 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ32 – DQ39 DQP4 W5 8 K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ40 – DQ47 DQP5 MCM67M518 A0 – A14 LW W6 8 TSP DQ0 – DQ7 TSC DQ8 BAA UW DQ48 – DQ55 DQP6 W7 8 K DQ9 – DQ16 G DQ17 DQ56 – DQ63 DQP7 E MPC2002•MPC2003 4 MOTOROLA FAST SRAM BLOCK DIAGRAM (See Note) BURST LOGIC BAA Q1 K A1′ BINARY COUNTER TSP D1 A1 EXTERNAL ADDRESS A15 – A0 16 Q0 LOAD TSC INTERNAL ADDRESS A0′ 64K x 18 MEMORY ARRAY D0 A0 A15 – A2 ADDRESS REGISTERS 16 18 WRITE REGISTER UW LW 9 DATA–IN REGISTERS ENABLE REGISTER E 9 OUTPUT BUFFER 9 9 G DQ0 – DQ8 DQ9 – DQ17 9 9 NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE GRAPH. Write refers to either or both byte write enables (LW, UW). BURST SEQUENCE GRAPH (See Note) 0,0 A1′, A0′ = 1,1 0,1 1,0 NOTE: The external two values for A1 and A0 provide the starting point for the burst sequence graph. The burst logic advances A1 and A0 as shown above. MOTOROLA FAST SRAM MPC2002•MPC2003 5 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) E TSP TSC BAA LW or UW K Address Operation H L X X X L–H N/A Deselected H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation G I/O Status Read L Data Out (DQ0 – DQ8) Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 6.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MPC2002•MPC2003 6 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC Input High Voltage VIH 4.75 5.25 V 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS AND SUPPLY CURRENTS Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Parameter Ilkg(I) — ± 1.0 µA Output Leakage Current (G = VIH) Ilkg(O) — ± 1.0 µA AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ICCA66 ICCA60 ICCA50 — 1160 1100 1000 mA AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ISB1 — 300 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible PowerPC bus cycles. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance Input Capacitance MOTOROLA FAST SRAM Symbol Typ Max Unit (A0 – A15, TSP, TSC, BAA) Cin 25 32 pF (DQ0 – DQ63, DQP0 – DQP7) CI/O 8 10 pF (Kx, Gx, Ex, Wx) Cin 12 15 pF MPC2002•MPC2003 7 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) (W refers to either or both byte write enables) MPC2002SG66/ MPC2003SG66 Parameter MPC2002SG60/ MPC2003SG60 MPC2002SG50/ MPC2003SG50 Symbol Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 15 — 16.6 — 20 — ns Clock Access Time tKHQV — 9 — 11 — 14 ns Output Enable to Output Valid tGLQV — 5 — 5 — 6 ns Clock High to Output Active tKHQX1 6 — 6 — 6 — ns Clock High to Output Change tKHQX2 3 — 3 — 3 — ns Output Enable to Output Active tGLQX 0 — 0 — 0 — ns Output Disable to Q High–Z tGHQZ 2 6 2 6 2 6 ns 5 Clock High to Q High–Z tKHQZ — 6 — 6 — 6 ns 5 Clock High Pulse Width tKHKL 5 — 5 — 6 — ns Clock Low Pulse Width tKLKH 5 — 5 — 6 — ns 4 Setup Times: Address Address Status Data In Write Address Advance Chip Select tAVKH tTSVKH tDVKH tWVKH tBAVKH tEVKH 2.5 — 2.5 — 2.5 — ns 6 Hold Times: Address Address Status Data In Write Address Advance Chip Select tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX 0.5 — 0.5 — 0.5 — ns 6 NOTES: 1. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don’t care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC 60x external bus cycles. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device. 6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever TSP or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is selected.Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. AC TEST LOADS +5V 480 Ω OUTPUT OUTPUT Z0 = 50 Ω RL = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MPC2002•MPC2003 8 Figure 1B MOTOROLA FAST SRAM MOTOROLA FAST SRAM MPC2002•MPC2003 9 t EVKH t AVKH t TSVKH t GLQX A1 SINGLE READ Q(A1) t KHQV t GLQV t KHEX t KHAX t KHKL t KLKH t BAVKH t WVKH A2 Q(A2) t KHQX2 t TSVKH t GHQZ t KHKH Q(A2 + 1) t KHQV t KHBAX t KHWX t KHTSX BURST READ Q(A2 + 2) Q(A2 + 3) Q(A2) (BURST WRAPS AROUND TO ITS INITIAL STATE) (BAA SUSPENDS BURST) NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address. DATA OUT G BAA E LW, UW ADDRESS TSC TSP K t KHTSX READ CYCLES Q(A2 + 1) Q(A2 + 2) t KHQZ MPC2002•MPC2003 10 MOTOROLA FAST SRAM Q D G BAA E LW, UW A TSC TSP K BURST READ Q(An – 1) t EVKH t AVKH t TSVKH Q(An) A1 t TSVKH A2 t KLKH t KHSX SINGLE WRITE t GHQZ D(A1) t KHEX D(A2) BURST WRITE D(A2 + 1) D(A2 + 3) TSC STARTS NEW BURST D(A2 + 2) (WITH A SUSPENDED CYCLE) D(A2 + 1) BAA SUSPENDS BURST W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST t KHAX t KHKL t KHTSX t KHKH WRITE CYCLES D(A3) t DVKH D(A3 + 1) NEW BURST WRITE t BAVKH t WVKH A3 D(A3 + 2) t KHDX t KHBAX t KHWX COMBINATION READ/WRITE CYCLE (E low, TSC high) tKHKH K tTSVKH tKHTSX tKHKL tKLKH TSP tAVKH ADDRESS tKHAX A1 A2 A3 tWVKH tKHWX LW, UW tBAVKH tKHBAX BAA G tDVKH tKHQV DATA IN tKHDX tGLQV D(A2) tKHQX1 DATA OUT tKHQX2 Q(A3) Q(A1) READ MOTOROLA FAST SRAM tGLQX tGHQZ WRITE Q(A3 + 1) Q(A3 + 2) BURST READ MPC2002•MPC2003 11 APPLICATION EXAMPLE DATA BUS DATA ADDRESS BUS ADDRESS CLOCK MPC601 ADDR (PowerPC) BCLK ADDR DATA K0 K1 TSC Wx MCM67M618FN9 G0 G1 TSP BAA K CACHE CONTROL LOGIC MPC2003SG66 TS CONTROL 512K Byte Burstable, Secondary Cache Using MPC2003SG66 with a 66 MHz MPC601 PowerPC Figure 2 ORDERING INFORMATION (Order by Full Part Number) MPC2002 MCM MPC2003 XX XX Motorola Memory Prefix Speed (66 = 66 MHz, 60 = 60 MHz, 50 = 50 MHz) Package (SG = Gold Pad SIMM) Part Number Full Part Numbers — MPC2002SG66 MPC2003SG66 MPC2002•MPC2003 12 MPC2002SG60 MPC2003SG60 MPC2002SG50 MPC2003SG50 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 136–LEAD DIMM CASE 1104–01 A 0.006 (0.15) M T Y X S ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ C U NOTE 4 COMPONENT AREA B -Y- Y S P NOTE 4 68 35 1 N 2X 34 R -X- 2X VIEW AA L V NOTE 5 F 2X ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇ J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND S DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION V DEFINES OPTIONAL SINGLE–SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. BACK VIEW W 2X 2X W R R ÉÉ ÉÉ ÉÉ Q 0.006 (0.15) VIEW AA 132X T Y X ÇÇÇÇ ÇÇ ÇÇÇÇ ÇÇ ÇÇÇÇ ÇÇ ÇÇÇÇ ÇÇ L D 0.004 (0.10) 136X M T M G 136X L M SIDE VIEW COMPONENT AREA 2X NOTE 6 0.012 (0.30) -T- 136 103 69 102 FRONT VIEW T Y X K 136X H S DIM A B C D F G H J K L M N P Q R S T U V W Y INCHES MIN MAX 4.045 4.055 0.995 1.005 ––– 0.413 0.040 0.042 0.125 BSC 0.050 BSC ––– 0.010 0.046 0.054 0.100 ––– 1.650 BSC 0.075 0.085 0.400 BSC 0.125 ––– 0.123 0.127 0.245 0.255 0.157 ––– 0.064 0.060 3.784 BSC ––– 0.236 0.062 ––– 0.060 0.064 MILLIMETERS MIN MAX 102.74 103.00 25.27 25.53 ––– 10.50 1.02 1.07 3.18 BSC 1.27 BSC ––– 0.25 1.17 1.37 2.54 ––– 41.91 BSC 1.91 2.16 10.16 BSC 3.18 ––– 3.12 3.22 6.22 6.48 4.00 ––– 1.52 1.63 96.11 BSC ––– 6.00 1.57 ––– 1.52 1.63 Motorola reserves the right to make changes without further notice to any products herein. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MPC2002•MPC2003 14 ◊ *MPC2002/D* MPC2002/D MOTOROLA FAST SRAM