MOTOROLA MPC750

Freescale Semiconductor, Inc.
MPC750/D
(Motorola Order Number)
8/97
Advance Information
MPC750 RISC Microprocessor
Technical Summary
This document gives an overview of the MPC750 and MPC740 microprocessor features,
including a block diagram showing the major functional components. It summarizes how
the MPC750 and MPC740 processors implement the PowerPC® architecture specification
and describes processor-specific features not defined by the PowerPC architecture.
This document has two parts:
•
Part 1, “MPC750 Microprocessor Overview,” provides an overview of MPC750
features, including a block diagram showing the major functional components.
•
Part 2, “MPC750 Microprocessor: Implementation,” describes the PowerPC
architecture in general and provides specific details about the MPC750 as a lowpower, 32-bit implementation of the PowerPC architecture.
Unless otherwise noted, references in this document to the MPC750 apply to the MPC740.
The MPC750 differs from the MPC740 primarily in its extensive L2 cache support.
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/powerpc/.
The PowerPC name is a registered trademark and the PowerPC logotype is a trademark of International Business Machines Corporation
used by Motorola under license from International Business Machines Corporation.
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or
discontinue this product without notice.
© Motorola Inc. 1997. All rights reserved.
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MPC750 Technical Summary
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Part 1 MPC750 Microprocessor Overview
This section describes the features and general operation of the MPC750 and provides a block diagram
showing major functional units. The MPC750 is an implementation of the PowerPC microprocessor family
of reduced instruction set computer (RISC) microprocessors. The MPC750 implements the 32-bit portion
of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32
bits, and floating-point data types of 32 and 64 bits. The MPC750 is a superscalar processor that can
complete two instructions simultaneously. It incorporates the following six execution units:
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•
•
•
•
•
Floating-point unit (FPU)
Branch processing unit (BPU)
System register unit (SRU)
Load/store unit (LSU)
Two integer units (IUs): IU1 executes all integer instructions. IU2 executes all integer instructions
except multiply and divide instructions.
The ability to execute several instructions in parallel and the use of simple instructions with rapid execution
times yield high efficiency and throughput for MPC750-based systems. Most integer instructions execute in
one clock cycle. The FPU is pipelined, the tasks it performs are broken into subtasks, implemented as three
successive stages. Typically, a floating-point instruction can occupy only one of the three stages at a time,
freeing the previous stage to work on the next floating-point instruction. Thus, three single-precision
floating-point instructions can be in the FPU execute stage at a time. Double-precision add instructions have
a three-cycle latency; double-precision multiply and multiply-add instructions have a four-cycle latency.
Figure 1 shows the parallel organization of the execution units (shaded in the diagram). The instruction unit
fetches, dispatches, and predicts branch instructions. Note that this is a conceptual model that shows basic
features rather than attempting to show how features are implemented physically.
The MPC750 has independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed caches
for instructions and data and independent instruction and data memory management units (MMUs). Each
MMU has a 128-entry, two-way set-associative translation lookaside buffer (DTLB and ITLB) that saves
recently used page address translations. Block address translation is done through the four-entry instruction
and data block address translation (IBAT and DBAT) arrays, defined by the PowerPC architecture. During
block translation, effective addresses are compared simultaneously with all four BAT entries.
The L2 cache is implemented with an on-chip, two-way, set-associative tag memory, and with external,
synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated L2 cache port
that supports a single bank of up to 1 Mbyte of synchronous SRAMs. The L2 cache interface is not
implemented in the MPC740.
The MPC750 has a 32-bit address bus and a 64-bit data bus. Multiple devices compete for system resources
through a central external arbiter. The MPC750’s three-state cache-coherency protocol (MEI) supports the
exclusive, modified, and invalid states, a compatible subset of the MESI (modified/exclusive/shared/invalid)
four-state protocol, and it operates coherently in systems with four-state caches. The MPC750 supports
single-beat and burst data transfers for memory accesses and memory-mapped I/O operations.
The MPC750 has four software-controllable power-saving modes. Three static modes, doze, nap, and sleep,
progressively reduce power dissipation. When functional units are idle, a dynamic power management mode
causes those units to enter a low-power mode automatically without affecting operational performance,
software execution, or external hardware. The MPC750 also provides a thermal assist unit (TAU) and a way
to reduce the instruction fetch rate for limiting power dissipation.
The MPC750 uses an advanced CMOS process technology and is fully compatible with TTL devices.
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+
+ x ÷
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Reorder Buffer
(6 Entry)
Completion Unit
Integer Unit 2
Integer Unit 1
I
32-Bit
Reservation Station
Reservation Station
2 Instructions
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
DTLB
SRs
(Original)
DBAT
Array
Data MMU
32-Bit
CR
System Register
Unit
Reservation Station
PA
Tags
32-Kbyte
D Cache
64-Bit
32-Bit
CTR
LR
64-Bit
Instruction Fetch Queue
17-Bit L2 Address Bus
64-Bit L2 Data Bus
Data Load Queue
L1 Castout Queue
FPR File
ITLB
SRs
(Shadow)
Tags
L2 Castout Queue
L2 Tags
L2CR
L2 Controller
Not in the MPC740
FPSCR
FPSCR
+ x ÷
Floating-Point
Unit
32-Kbyte
I Cache
128-Bit
(4 Instructions)
Reservation Station
L2 Bus Interface
Unit
64-Bit
IBAT
Array
Instruction MMU
Rename Buffers
(6)
60x Bus Interface Unit
Store Queue
(EA Calculation)
+
Load/Store Unit
Reservation Station
(2 Entry)
64-Bit
(2 Instructions)
BHT
64 Entry
BTIC
32-Bit Address Bus
32-/64-Bit Data Bus
EA
Rename Buffers
(6)
GPR File
Dispatch Unit
Instruction Queue
(6 Word)
Fetcher
Branch Processing
Unit
Instruction Unit
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Figure 1. MPC750 Microprocessor Block Diagram
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1.1 MPC750 Microprocessor Features
This section lists features of the MPC750. The interrelationship of these features is shown in Figure 1.
1.1.1 Overview of the MPC750 Microprocessor Features
Major features of the MPC750 are as follows:
•
High-performance, superscalar microprocessor
— As many as four instructions can be fetched from the instruction cache per clock cycle
— As many as two instructions can be dispatched per clock
— As many as six instructions can execute per clock (including two integer instructions)
— Single-clock-cycle execution for most instructions
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•
Six independent execution units and two register files
— BPU featuring both static and dynamic branch prediction
– 64-entry (16-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, if a fetch access hits the BTIC, it
provides the first two instructions in the target stream.
– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—
not-taken, strongly not-taken, taken, strongly taken
– Branch instructions that do not update the count register (CTR) or link register (LR) are
removed from the instruction stream.
— Two integer units (IUs) that share thirty-two GPRs for integer operands
– IU1 can execute any integer instruction.
– IU2 can execute all integer instructions except multiply and divide instructions (multiply,
divide, shift, rotate, arithmetic, and logical instructions). Most instructions that execute in
the IU2 take one cycle to execute. The IU2 has a single-entry reservation station.
— Three-stage FPU
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Single-entry reservation station
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Two-stage LSU
– Two-entry reservation station
– Single-cycle, pipelined cache access
– Dedicated adder performs EA calculations
– Performs alignment and precision conversion for floating-point data
– Performs alignment and sign extension for integer data
– Three-entry store queue
– Supports both big- and little-endian modes
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— SRU handles miscellaneous instructions
– Executes CR logical and Move to/Move from SPR instructions (mtspr and mfspr)
– Single-entry reservation station
•
Rename buffers
— Six GPR rename buffers
— Six FPR rename buffers
— Condition register buffering supports two CR writes per clock
•
Completion unit
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— The completion unit retires an instruction from the six-entry reorder buffer (completion queue)
when all instructions ahead of it have been completed, the instruction has finished execution,
and no exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions from the mispredicted branch
— Retires as many as two instructions per clock
•
Separate on-chip instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) cache block
— Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical
address space as real address space.)
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock; data cache can provide two words per
clock
— Caches can be disabled in software
— Caches can be locked in software
— Data cache coherency (MEI) maintained in hardware
— The critical double word is made available to the requesting unit when it is burst into the linefill buffer. The cache is nonblocking, so it can be accessed during this operation.
•
Level 2 (L2) cache interface (The L2 cache interface is not supported in the MPC740.)
— On-chip two-way set-associative L2 cache controller and tags
— External data SRAMs
— Support for 256-Kbyte, 512-Kbyte, and 1-Mbyte L2 caches
— 64-byte (256-Kbyte/512-Kbyte) and 128-byte (1 Mbyte) sectored line size
— Supports flow-through (register-buffer), pipelined (register-register), and pipelined late-write
(register-register) synchronous burst SRAMs
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•
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, cacheable/noncacheable, and coherency
enforced/coherency not enforced on a page or block basis
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm
– TLBs are hardware reloadable (that is, the page table search is performed in hardware)
•
Separate bus interface units for system memory and for the L2 cache
— Bus interface features include the following:
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– Selectable bus-to-core clock frequency ratios of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x ... 8x. (2x to 8x,
all half-clock multipliers in-between)
– A 64-bit, split-transaction external data bus with burst transfers
– Support for address pipelining and limited out-of-order bus transactions
– Single-entry load queue
– Single-entry instruction fetch queue
– Two-entry L1 cache castout queue
– No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant. This allows
the forwarding of data during load operations to the internal core one bus cycle sooner than
if the use of DRTRY is enabled.
— L2 cache interface features (which are not implemented on the MPC740) include the following:
– Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3
– Four-entry L2 cache castout queue in L2 cache BIU
– 17-bit address bus
– 64-bit data bus
•
Multiprocessing support features include the following:
— Hardware-enforced, three-state cache coherency protocol (MEI) for data cache.
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
•
Power and thermal management
— Three static modes, doze, nap, and sleep, progressively reduce power dissipation:
– Doze—All the functional units are disabled except for the time base/decrementer registers
and the bus snooping logic.
– Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving
only the time base register and the PLL in a powered state.
– Sleep—All internal functional units are disabled, after which external system logic may
disable the PLL and SYSCLK.
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— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an MPC750specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power consumption.
•
Performance monitor can be used to help debug system designs and improve software efficiency.
•
In-system testability and debugging features through JTAG boundary-scan capability
1.1.2 Instruction Flow
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As shown in Figure 1, the MPC750 instruction unit provides centralized control of instruction flow to the
execution units. The instruction unit contains a sequential fetcher, six-entry instruction queue (IQ), dispatch
unit, and BPU. It determines the address of the next instruction to be fetched based on information from the
sequential fetcher and from the BPU.
The sequential fetcher loads instructions from the instruction cache into the instruction queue. The BPU
extracts branch instructions from the sequential fetcher. Branch instructions that cannot be resolved
immediately are predicted using either the MPC750-specific dynamic branch prediction or the architecturedefined static branch prediction.
Branch instructions that do not affect the LR or CTR are removed from the instruction stream. The BPU
folds branch instructions when a branch is taken (or predicted as taken); branch instructions that are not
taken, or predicted as not taken, are removed from the instruction stream through the dispatch mechanism.
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,
preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction
unit flushes all predicted path instructions, and instructions are fetched from the correct path.
1.1.2.1 Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 1, holds as many as six instructions and loads up to four
instructions from the instruction cache during a single processor clock cycle. The instruction fetcher
continuously attempts to load as many instructions as there were vacancies in the IQ in the previous clock
cycle. All instructions except branch instructions are dispatched to their respective execution units from the
bottom two positions in the instruction queue (IQ0 and IQ1) at a maximum rate of two instructions per cycle.
Reservation stations are provided for the IU1, IU2, FPU, LSU, and SRU. The dispatch unit checks for source
and destination register dependencies, determines whether a position is available in the completion queue,
and inhibits subsequent instruction dispatching as required.
Branch instructions can be detected, decoded, and predicted from anywhere in the instruction queue. For a
more detailed discussion of instruction dispatch, see Section 2.6, “Instruction Timing.”
1.1.2.2 Branch Processing Unit (BPU)
The BPU receives branch instructions from the sequential fetcher and performs CR lookahead operations
on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
Unconditional branch instructions and conditional branch instructions in which the condition is known can
be resolved immediately. For unresolved conditional branch instructions, the branch path is predicted using
either the architecture-defined static branch prediction or the MPC750-specific dynamic branch prediction.
Dynamic branch prediction is enabled if HID0[BHT] = 1.
When a prediction is made, instruction fetching, dispatching, and execution continue from the predicted
path, but instructions cannot complete and write back results to architected registers until the prediction is
determined to be correct (resolved). When a prediction is incorrect, the instructions from the incorrect path
are flushed from the processor and processing begins from the correct path. The MPC750 allows a second
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branch instruction to be predicted; instructions from the second predicted instruction stream can be fetched
but cannot be dispatched.
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Dynamic prediction is implemented using a 512-entry branch history table (BHT), a cache that provides two
bits per entry that together indicate four levels of prediction for a branch instruction—not-taken, strongly
not-taken, taken, strongly taken. When dynamic branch prediction is disabled, the BPU uses a bit in the
instruction encoding to predict the direction of the conditional branch. Therefore, when an unresolved
conditional branch instruction is encountered, the MPC750 executes instructions from the predicted target
stream although the results are not committed to architected registers until the conditional branch is
resolved. This execution can continue until a second unresolved branch instruction is encountered.
When a branch is taken (or predicted as taken), the instructions from the untaken path must be flushed and
the target instruction stream must be fetched into the IQ. The BTIC is a 64-entry cache that contains the
most recently used branch target instructions, typically in pairs. When an instruction fetch hits in the BTIC,
the instructions arrive in the instruction queue in the next clock cycle, a clock cycle sooner than they would
arrive from the instruction cache. Additional instructions arrive from the instruction cache in the next clock
cycle. The BTIC reduces the number of missed opportunities to dispatch instructions and gives the processor
a one-cycle head start on processing the target stream.
The BPU contains an adder to compute branch target addresses and three user-control registers—the link
register (LR), the count register (CTR), and the CR. The BPU calculates the return pointer for subroutine
calls and saves it into the LR for certain types of branch instructions. The LR also contains the branch target
address for the Branch Conditional to Link Register (bclrx) instruction. The CTR contains the branch target
address for the Branch Conditional to Count Register (bcctrx) instruction. Because the LR and CTR are
SPRs, their contents can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than GPRs or FPRs, execution of branch instructions is largely independent from execution of integer and
floating-point instructions.
1.1.2.3 Completion Unit
The completion unit operates closely with the instruction unit. Instructions are fetched and dispatched in
program order. At the point of dispatch, the program order is maintained by assigning each dispatched
instruction a successive entry in the six-entry completion queue. The completion unit tracks instructions
from dispatch through execution and retires them in program order from the two bottom entries in the
completion queue (CQ0 and CQ1).
Instructions cannot be dispatched to an execution unit unless there is a vacancy in the completion queue.
Branch instructions that do not update the CTR or LR are removed from the instruction stream and do not
take an entry in the completion queue. Instructions that update the CTR and LR follow the same dispatch
and completion procedures as nonbranch instructions, except that they are not issued to an execution unit.
Completing an instruction commits execution results to architected registers (GPRs, FPRs, LR, and CTR).
In-order completion ensures the correct architectural state when the MPC750 must recover from a
mispredicted branch or any exception. Retiring an instruction removes it from the completion queue.
1.1.2.4 Independent Execution Units
In addition to the BPU, the MPC750 provides the five execution units described in the following sections.
1.1.2.4.1 Integer Units (IUs)
The integer units, IU1 and IU2, are shown in Figure 1. The IU1 can execute any integer instruction; the IU2
can execute any integer instruction except multiplication and division instructions. Each IU has a singleentry reservation station that can receive instructions from the dispatch unit and operands from the GPRs or
the rename buffers.
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Each IU consists of three single-cycle subunits—a fast adder/comparator, a subunit for logical operations,
and a subunit for performing rotates, shifts, and count-leading-zero operations. These subunits handle all
one-cycle arithmetic instructions; only one subunit can execute an instruction at a time.
The IU1 has a 32-bit integer multiplier/divider as well as the adder, shift, and logical units of the IU2. The
multiplier supports early exit for operations that do not require full 32- x 32-bit multiplication.
Each IU has a dedicated result bus (not shown in Figure 1) that connects to rename buffers.
1.1.2.4.2 Floating-Point Unit (FPU)
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The FPU, shown in Figure 1, is designed such that single-precision operations require only a single pass,
with a latency of three cycles. As instructions are dispatched to the FPU’s reservation station, source operand
data can be accessed from the FPRs or from the FPR rename buffers. Results in turn are written to the
rename buffers and are made available to subsequent instructions. Instructions pass through the reservation
station in dispatch order.
The FPU contains a single-precision multiply-add array and the floating-point status and control register
(FPSCR). The multiply-add array allows the MPC750 to efficiently implement multiply and multiply-add
operations. The FPU is pipelined so that one single- or double-precision instruction can be issued per clock
cycle. Thirty-two 64-bit floating-point registers are provided to support floating-point operations. Stalls due
to contention for FPRs are minimized by automatic allocation of the six floating-point rename registers. The
MPC750 writes the contents of the rename registers to the appropriate FPR when floating-point instructions
are retired by the completion unit.
The MPC750 supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and
infinity) in hardware, eliminating the latency incurred by software exception routines. (Note that exception
is also referred to as interrupt in the architecture specification.)
1.1.2.4.3 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the GPRs,
FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment,
and provides sequencing for load/store string and multiple instructions.
Load and store instructions are issued and translated in program order; however, some memory accesses can
occur out of order. Synchronizing instructions can be used to enforce strict ordering. When there are no data
dependencies and the guarded bit for the page or block is cleared, a maximum of one out-of-order cacheable
load operation can execute per cycle, with a two-cycle total latency on a cache hit. Data returned from the
cache is held in a rename register until the completion logic commits the value to a GPR or FPR. Stores
cannot be executed out of order and are held in the store queue until the completion logic signals that the
store operation is to be completed to memory. The MPC750 executes store instructions with a maximum
throughput of one per cycle and a three-cycle total latency to the data cache. The time required to perform
the actual load or store operation depends on the processor/bus clock ratio and whether the operation
involves the on-chip cache, the L2 cache, system memory, or an I/O device.
1.1.2.4.4 System Register Unit (SRU)
The SRU executes various system-level instructions, as well as condition register logical operations and
move to/from special-purpose register instructions. To maintain system state, most instructions executed by
the SRU are execution-serialized; that is, the instruction is held for execution in the SRU until all previously
issued instructions have executed. Results from execution-serialized instructions executed by the SRU are
not available or forwarded for subsequent instructions until the instruction completes.
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1.1.3 Memory Management Units (MMUs)
The MPC750’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical
memory for instructions and data. The MMUs also control access privileges for these spaces on block and
page granularities. Referenced and changed status is maintained by the processor for each page to support
demand-paged virtual memory systems.
The LSU calculates effective addresses for data loads and stores; the instruction unit calculates effective
addresses for instruction fetching. The MMU translates the effective address to determine the correct
physical address for the memory access.
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The MPC750 supports the following types of memory translation:
•
Real addressing mode—In this mode, translation is disabled by clearing bits in the machine state
register (MSR): MSR[IR] for instruction fetching or MSR[DR] for data accesses. When address
translation is disabled, the physical address is identical to the effective address.
•
Page address translation—translates the page frame address for a 4-Kbyte page size
•
Block address translation—translates the base address for blocks (128 Kbytes to 256 Mbytes)
If translation is enabled, the appropriate MMU translates the higher-order bits of the effective address into
physical address bits. The lower-order address bits (that are untranslated and therefore, considered both
logical and physical) are directed to the on-chip caches where they form the index into the eight-way setassociative tag array. After translating the address, the MMU passes the higher-order physical address bits
to the cache and the cache lookup completes. For caching-inhibited accesses or accesses that miss in the
cache, the untranslated lower-order address bits are concatenated with the translated higher-order address
bits; the resulting 32-bit physical address is used by the memory unit and the system interface, which
accesses external memory.
The TLBs store page address translations for recent memory accesses. For each access, an effective address
is presented for page and block translation simultaneously. If a translation is found in both the TLB and the
BAT array, the block address translation in the BAT array is used. Usually the translation is in a TLB and
the physical address is readily available to the on-chip cache. When a page address translation is not in a
TLB, hardware searches for one in the page table following the model defined by the PowerPC architecture.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring
no additional time penalty in the event of a TLB hit. The MPC750’s TLBs are 128-entry, two-way setassociative caches that contain instruction and data address translations. The MPC750 automatically
generates a TLB search on a TLB miss.
1.1.4 On-Chip Instruction and Data Caches
The MPC750 implements separate instruction and data caches. Each cache is 32-Kbyte and eight-way set
associative. As defined by the PowerPC architecture, they are physically indexed. Each cache block contains
eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits EA[27–31] are
zeros); thus, a cache block never crosses a page boundary. An entire cache block can be updated by a fourbeat burst load. Misaligned accesses across a page boundary can incur a performance penalty. Caches are
nonblocking, write-back caches with hardware support for reloading on cache misses. The critical double
word is transferred on the first beat and is simultaneously written to the cache and forwarded to the
requesting unit, minimizing stalls due to load delays. The cache being loaded is not blocked to internal
accesses while the load completes.
The MPC750 cache organization is shown in Figure 2.
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128 Sets
Block 0
Address Tag 0
State
Words [0–7]
Block 1
Address Tag 1
State
Words [0–7]
Block 2
Address Tag 2
State
Words [0–7]
Block 3
Address Tag 3
State
Words [0–7]
Block 4
Address Tag 4
State
Words [0–7]
Block 5
Address Tag 5
State
Words [0–7]
Block 6
Address Tag 6
State
Words [0–7]
Block 7
Address Tag 7
State
Words [0–7]
8 Words/Block
Figure 2. Cache Organization
Within one cycle, the data cache provides double-word access to the LSU. Like the instruction cache, the
data cache can be invalidated all at once or on a per-cache-block basis. The data cache can be disabled and
invalidated by clearing HID0[DCE] and setting HID0[DCFI]. The data cache can be locked by setting
HID0[DLOCK]. To ensure cache coherency, the data cache supports the three-state MEI protocol. The data
cache tags are single-ported, so a simultaneous load or store and a snoop access represent a resource
collision. If a snoop hit occurs, the LSU is blocked internally for one cycle to allow the eight-word block of
data to be copied to the write-back buffer.
Within one cycle, the instruction cache provides up to four instructions to the instruction queue. The
instruction cache can be invalidated entirely or on a cache-block basis. The instruction cache can be disabled
and invalidated by clearing HID0[ICE] and setting HID0[ICFI]. The instruction cache can be locked by
setting HID0[ILOCK]. The instruction cache supports only the valid/invalid states.
The MPC750 also implements a 64-entry (16-set, four-way set-associative) branch target instruction cache
(BTIC). The BTIC is a cache of branch instructions that have been encountered in branch/loop code
sequences. If the target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than
it can be made available from the instruction cache. Typically the BTIC contains the first two instructions
in the target stream. The BTIC can be disabled and invalidated through software. For more information, see
Section 1.1.2.2, “Branch Processing Unit (BPU).”
1.1.5 L2 Cache Implementation (Not Supported in the MPC740)
The L2 cache is a unified cache that receives memory requests from both the L1 instruction and data caches
independently. The L2 cache is implemented with an on-chip, two-way, set-associative tag memory, and
with external, synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated
L2 cache port that supports a single bank of up to 1 Mbyte of synchronous SRAMs. The L2 cache normally
operates in write-back mode and supports system cache coherency through snooping.
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Depending on its size, the L2 cache is organized into 64- or 128-byte lines, which in turn are subdivided
into 32-byte sectors (blocks), the unit at which cache coherency is maintained.
The L2 cache controller contains the L2 cache control register (L2CR), which includes bits for enabling
parity checking, setting the L2-to-processor clock ratio, and identifying the type of RAM used for the L2
cache implementation. The L2 cache controller also manages the L2 cache tag array, two-way setassociative with 4K tags per way. Each sector (32-byte cache block) has its own valid and modified status
bits.
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Requests from the L1 cache generally result from instruction misses, data load or store misses, writethrough operations, or cache management instructions. Requests from the L1 cache are looked up in the L2
tags and serviced by the L2 cache if they hit; they are forwarded to the bus interface if they miss.
The L2 cache can accept multiple, simultaneous accesses. The L1 instruction cache can request an
instruction at the same time that the L1 data cache is requesting one load and two store operations. The L2
cache also services snoop requests from the bus. If there are multiple pending requests to the L2 cache,
snoop requests have highest priority. The next priority consists of load and store requests from the L1 data
cache. The next priority consists of instruction fetch requests from the L1 instruction cache.
1.1.6 System Interface/Bus Interface Unit (BIU)
The address and data buses operate independently; address and data tenures of a memory access are
decoupled to provide a more flexible control of memory traffic. The primary activity of the system interface
is transferring data and instructions between the processor and system memory. There are two types of
memory accesses:
•
Single-beat transfers—These memory accesses allow transfer sizes of 8, 16, 24, 32, or 64 bits in
one bus clock cycle. Single-beat transactions are caused by uncacheable read and write operations
that access memory directly (that is, when caching is disabled), cache-inhibited accesses, and stores
in write-through mode.
•
Four-beat burst (32 bytes) data transfers—Burst transactions, which always transfer an entire cache
block (32 bytes), are initiated when an entire cache block is transferred. Because the first-level
caches on the MPC750 are write-back caches, burst-read memory, burst operations are the most
common memory accesses, followed by burst-write memory operations, and single-beat
(noncacheable or write-through) memory read and write operations.
The MPC750 also supports address-only operations, variants of the burst and single-beat operations, (for
example, atomic memory operations and global memory operations that are snooped), and address retry
activity (for example, when a snooped read access hits a modified block in the cache). The broadcast of some
address-only operations is controlled through HID0[ABE]. I/O accesses use the same protocol as memory
accesses.
Access to the system interface is granted through an external arbitration mechanism that allows devices to
compete for bus mastership. This arbitration mechanism is flexible, allowing the MPC750 to be integrated
into systems that implement various fairness and bus parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the
bus without sacrificing data coherency. The MPC750 allows read operations to go ahead of store operations
(except when a dependency exists, or in cases where a noncacheable access is performed), and provides
support for a write operation to go ahead of a previously-queued read data tenure (for example, letting a
snoop push be enveloped between address and data tenures of a read operation). Because the MPC750 can
dynamically optimize run-time ordering of load/store traffic, overall performance is improved.
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The system interface is specific for each PowerPC microprocessor implementation.
The MPC750 signals are grouped as shown in Figure 3. Signals are provided for clocking and control of the
L2 caches, as well as separate L2 address and data buses. Test and control signals provide diagnostics for
selected internal circuits.
Address Arbitration
Data Arbitration
Data Transfer
Address Start
Data Termination
Address Transfer
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L2 Cache Clock/Control 1
MPC750
Transfer Attribute
Address Termination
L2 Cache Address/Data 1
Clocks
Processor Status/Control
Test and Control
System Status
V DD
V DD (I/O)
1 Not supported in the MPC740
Figure 3. System Interface
The system interface supports address pipelining, which allows the address tenure of one transaction to
overlap the data tenure of another. The extent of the pipelining depends on external arbitration and control
circuitry. Similarly, the MPC750 supports split-bus transactions for systems with multiple potential bus
masters—one device can have mastership of the address bus while another has mastership of the data bus.
Allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other
activity.
The MPC750’s clocking structure supports a wide range processor-to-bus clock ratios.
1.1.7 Signals
The MPC750’s signals are grouped as follows:
•
Address arbitration signals—The MPC750 uses these signals to arbitrate for address bus
mastership.
•
Address start signals—These signals indicate that a bus master has begun a transaction on the
address bus.
•
Address transfer signals—These signals include the address bus and address parity signals. They
are used to transfer the address and to ensure the integrity of the transfer.
•
Transfer attribute signals—These signals provide information about the type of transfer, such as the
transfer size and whether the transaction is bursted, write-through, or caching-inhibited.
•
Address termination signals—These signals are used to acknowledge the end of the address phase
of the transaction. They also indicate whether a condition exists that requires the address phase to
be repeated.
•
Data arbitration signals—The MPC750 uses these signals to arbitrate for data bus mastership.
•
Data transfer signals—These signals, which consist of the data bus and data parity signals, are used
to transfer the data and to ensure the integrity of the transfer.
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•
Data termination signals—Data termination signals are required after each data beat in a data
transfer. In a single-beat transaction, a data termination signal also indicates the end of the tenure;
in burst accesses, data termination signals apply to individual beats and indicate the end of the
tenure only after the final data beat. They also indicate whether a condition exists that requires the
data phase to be repeated.
•
L2 cache clock/control signals—These signals provide clocking and control for the L2 cache. (The
L2 cache feature is not supported in the MPC740.)
•
L2 cache address/data—The MPC750 has separate address and data buses for accessing the L2
cache. (The L2 cache feature is not supported in the MPC740.)
•
Interrupt signals—These signals include the interrupt signal, checkstop signals, and both soft reset
and hard reset signals. These signals are used to generate interrupt exceptions and, under various
conditions, to reset the processor.
•
Processor status/control signals—These signals are used to set the reservation coherency bit, enable
the time base, and other functions.
•
Miscellaneous signals—These signals are used in conjunction with such resources as secondary
caches and the time base facility.
•
JTAG/COP interface signals—The common on-chip processor (COP) unit provides a serial
interface to the system for performing board-level boundary-scan interconnect tests.
•
Clock signals—These signals determine the system clock frequency. These signals can also be used
to synchronize multiprocessor systems.
NOTE
A bar over a signal name indicates that the signal is active low—for
example, ARTRY (address retry) and TS (transfer start). Active-low
signals are referred to as asserted (active) when they are low and negated
when they are high. Signals that are not active low, such as AP[0–3]
(address bus parity signals) and TT[0–4] (transfer type signals) are referred
to as asserted when they are high and negated when they are low.
1.1.8 Signal Configuration
Figure 4 shows the MPC750's logical pin configuration. The signals are grouped by function.
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L2V DD
L2AV DD Not supported in the MPC740
BR
Address
Arbitration
Address
Start
BG
ABB
TS
1
17
1
64
1
8
1
1
1
2
A[0–31]
Address
Bus
AP[0–3]
32
1
4
1
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1
TT[0–4]
TBST
Transfer
Attributes
TSIZ[0–2]
GBL
WT
CI
5
1
1
3
1
1
1
MPC750
AACK
ARTRY
DBG
Data
Arbitration
DBW O
DBB
D[0–63]
Data
Transfer
DP[0–7]
DBDIS
TA
Data
Termination
DRTRY
TEA
L2DATA[0–63]
L2DP[0–7]
L2WE
L2CLK_OUT[A–B]
L2SYNC_OUT
L2SYNC_IN
L2 Cache
Clock/
Control
L2ZZ
INT
SMI
1
MCP
1
SRESET
1
HRESET
1
L2 Cache
Address/
Data
L2CE
1
1
Address
Termination
L2ADDR[16–0]
Interrupts/
Resets
CKSTP_IN
CKSTP_OUT
1
1
1
1
1
1
1
1
1
1
64
1
8
4
1
1
1
5
1
3
RSRV
TBEN
TLBISYNC
QREQ
Processor
Status/
Control
QACK
SYSCLK
PLL_CFG[0–3]
CLK_OUT
JTAG/COP
Factory Test
Clock
Control
Test
Interface
1
V DD V DD (I/O) AV DD
Figure 4. MPC750 Microprocessor Signal Groups
1.1.9 Clocking
The MPC750 requires a single system clock input, SYSCLK, that represents the bus interface frequency.
Internally, the processor uses a phase-locked loop (PLL) circuit to generate a master core clock that is
frequency-multiplied and phase-locked to the SYSCLK input. This core frequency is used to operate the
internal circuitry.
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The PLL is configured by the PLL_CFG[0–3] signals, which select the multiplier that the PLL uses to
multiply the SYSCLK frequency up to the internal core frequency. The feedback in the PLL guarantees that
the processor clock is phase locked to the bus clock, regardless of process variations, temperature changes,
or parasitic capacitances. The PLL also ensures a 50% duty cycle for the processor clock.
The MPC750 supports various processor-to-bus clock frequency ratios, although not all ratios are available
for all frequencies. Configuration of the processor/bus clock ratios is displayed through a MPC750-specific
register, HID1. For information about supported clock frequencies, see the MPC750 hardware
specifications.
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Part 2 MPC750 Microprocessor: Implementation
The PowerPC architecture is derived from the POWER architecture (Performance Optimized with
Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture
optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction
execution and is scalable to take advantage of future technological gains.
This section describes the PowerPC architecture in general, and specific details about the implementation
of the MPC750 as a low-power, 32-bit member of the PowerPC processor family.
16
•
Registers and programming model—Section 2.1, “PowerPC Registers and Programming Model,”
describes the registers for the operating environment architecture common among PowerPC
processors and describes the programming model. It also describes the registers that are unique to
the MPC750.
•
Instruction set and addressing modes—Section 2.2, “Instruction Set,” describes the PowerPC
instruction set and addressing modes for the PowerPC operating environment architecture, and
defines and describes the PowerPC instructions implemented in the MPC750.
•
Cache implementation—Section 2.3, “On-Chip Cache Implementation,” describes the cache model
that is defined generally for PowerPC processors by the virtual environment architecture. It also
provides specific details about the MPC750 cache implementation.
•
Exception model—Section 2.4, “Exception Model,” describes the exception model of the PowerPC
operating environment architecture and the differences in the MPC750 exception model.
•
Memory management—Section 2.5, “Memory Management,” describes generally the conventions
for memory management among the PowerPC processors. This section also describes the
MPC750’s implementation of the 32-bit PowerPC memory management specification.
•
Instruction timing—Section 2.6, “Instruction Timing,” provides a general description of the
instruction timing provided by the superscalar, parallel execution supported by the PowerPC
architecture and the MPC750.
•
Power management—Section 2.7, “Power Management,” describes how the power management
can be used to reduce power consumption when the processor, or portions of it, are idle.
•
Thermal management—Section 2.8, “Thermal Management,” describes how the thermal
management unit and its associated registers (THRM1–THRM3) and exception can be used to
manage system activity in a way that prevents exceeding system and junction temperature
thresholds. This is particularly useful in high-performance portable systems, which cannot use the
same cooling mechanisms (such as fans) that control overheating in desktop systems.
•
Performance monitor—Section 2.9, “Performance Monitor,” describes the performance monitor
facility, which system designers can use to help bring up, debug, and optimize software
performance.
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The following sections summarize the features of the MPC750, distinguishing those that are defined by the
architecture from those that are unique to the MPC750 implementation.
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The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can
be described in terms of which of the following levels of the architecture is implemented:
•
PowerPC user instruction set architecture (UISA)—Defines the base user-level instruction set, userlevel registers, data types, floating-point exception model, memory models for a uniprocessor
environment, and programming model for a uniprocessor environment.
•
PowerPC virtual environment architecture (VEA)—Describes the memory model for a
multiprocessor environment, defines cache control instructions, and describes other aspects of
virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may
not necessarily adhere to the OEA.
•
PowerPC operating environment architecture (OEA)—Defines the memory management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and system interface
implementations. The MPC750 implementations support the three levels of the architecture described
above. For more information about the PowerPC architecture, see PowerPC Microprocessor Family: The
Programming Environments.
Specific features of the MPC750 are listed in Section 1.1, “MPC750 Microprocessor Features.”
2.1 PowerPC Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two source operands. Load and store instructions transfer data between registers
and memory.
PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the
operating system) and user mode of operation (used by the application software). The programming models
incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers. Each
PowerPC microprocessor also has its own unique set of hardware implementation (HID) registers.
Having access to privileged instructions, registers, and other resources allows the operating system to
control the application environment (providing virtual memory and protecting operating-system and critical
machine resources). Instructions that control the state of the processor, the address translation mechanism,
and supervisor registers can be executed only when the processor is operating in supervisor mode.
Figure 5 shows all the MPC750 registers available at the user and supervisor level. The numbers to the right
of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.
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SUPERVISOR MODEL—OEA
Configuration Registers
USER MODEL—VEA
Time Base Facility (For Reading)
TBL
TBR 268
TBU
Processor
Version
Register
Hardware
Implementation
Registers 1
TBR 269
HID0
SPR 1008
HID1
SPR 1009
USER MODEL—UISA
Count
Register
SPR 9
XER
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XER
Instruction BAT
Registers
LR
Performance Counters 1
UPMC1
SPR 937
UPMC2
SPR 938
UPMC3
SPR 941
UPMC4
SPR 942
Sampled Instruction
Address 1
USIA
SPR 939
Monitor Control 1
UMMCR0
SPR 936
UMMCR1
SPR 940
Segment
Registers
IBAT0U
SPR 528
DBAT0U
SPR 536
SR0
GPR1
IBAT0L
SPR 529
DBAT0L
SPR 537
SR1
IBAT1U
SPR 530
DBAT1U
SPR 538
IBAT1L
SPR 531
DBAT1L
SPR 539
GPR31
IBAT2U
SPR 532
DBAT2U
SPR 540
Floating-Point
Registers
IBAT2L
SPR 533
DBAT2L
SPR 541
IBAT3U
SPR 534
DBAT3U
SPR 542
FPR0
IBAT3L
SPR 535
DBAT3L
SPR 543
SPR 8
Performance
Monitor Registers
(For Reading)
Data BAT
Registers
GPR0
SPR 1
Link Register
MSR
SPR 287
Memory Management Registers
General-Purpose
Registers
CTR
PVR
Machine State
Register
FPR1
SR15
SDR1
SDR1
SPR 25
Exception Handling Registers
SPRGs
FPR31
Condition
Register
SPRG0
SPR 272
SPRG1
SPR 273
SPRG2
SPR 274
SPRG3
SPR 275
Data Address
Register
DAR
Save and Restore
Registers
SPR 19
DSISR
DSISR
SRR0
SPR 26
SRR1
SPR 27
SPR 18
CR
Miscellaneous Registers
Floating-Point
Status and
Control Register
External Access
Register
EAR
FPSCR
Time Base
(For Writing)
SPR 282
Data Address
Breakpoint Register
DABR
Decrementer
DEC
TBL
SPR 284
TBU
SPR 285
L2 Control
Register 1, 2
SPR 1013
L2CR
SPR 22
Instruction Address
Breakpoint Register 1
SPR 1017
IABR
SPR 1010
Performance Monitor Registers
Performance
Counters 1
PMC1
SPR 953
PMC2
SPR 954
PMC3
SPR 957
PMC4
SPR 958
Power/Thermal Management Registers
Sampled
Instruction
Address 1
SIA
Thermal Assist
Unit Registers 1
SPR 955
Monitor Control 1
MMCR0
SPR 952
MMCR1
SPR 956
THRM1
SPR 1020
THRM2
SPR 1021
THRM3
SPR 1022
Instruction Cache
Throttling Control
Register 1
ICTC
SPR 1019
1 These registers are MPC750-specific registers. They may not be supported by other PowerPC processors.
2 Not supported by the MPC740.
Figure 5. MPC750 Microprocessor Programming Model—Registers
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The following tables summarize the PowerPC registers implemented in the MPC750; Table 1 describes
registers (excluding SPRs) defined by the architecture.
Table 1. Architecture-Defined Registers on the MPC750 (Excluding SPRs)
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Register
Level
Function
CR
User
The condition register (CR) consists of eight 4-bit fields that reflect the results of certain
operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
FPRs
User
The 32 floating-point registers (FPRs) serve as the data source or destination for floatingpoint instructions. These 64-bit registers can hold either single- or double-precision floatingpoint values.
FPSCR
User
The floating-point status and control register (FPSCR) contains the floating-point exception
signal bits, exception summary bits, exception enable bits, and rounding control bits needed
for compliance with the IEEE-754 standard.
GPRs
User
The 32 GPRs serve as the data source or destination for integer instructions.
MSR
Supervisor The machine state register (MSR) defines the processor state. Its contents are saved when
an exception is taken and restored when exception handling completes. The MPC750
implements MSR[POW], (defined by the architecture as optional), which is used to enable the
power management feature. The MPC750-specific MSR[PM] bit is used to mark a process for
the performance monitor.
SR0–
SR15
Supervisor The sixteen 32-bit segment registers (SRs) define the 4-Gbyte space as sixteen 256-Mbyte
segments. The MPC750 implements segment registers as two arrays—a main array for data
accesses and a shadow array for instruction accesses; see Figure 1. Loading a segment
entry with the Move to Segment Register (mtsr) instruction loads both arrays. The mfsr
instruction reads the master register, shown as part of the data MMU in Figure 1.
The OEA defines numerous special-purpose registers that serve a variety of functions, such as providing
controls, indicating status, configuring the processor, and performing special operations. During normal
execution, a program can access the registers, shown in Figure 5, depending on the program’s access
privilege (supervisor or user, determined by the privilege-level (PR) bit in the MSR). GPRs and FPRs are
accessed through operands that are part of the instructions. Access to registers can be explicit (that is,
through the use of specific instructions for that purpose such as Move to Special-Purpose Register (mtspr)
and Move from Special-Purpose Register (mfspr) instructions) or implicit, as the part of the execution of
an instruction. Some registers can be accessed both explicitly and implicitly.
In the MPC750, all SPRs are 32 bits wide. Table 2 describes the architecture-defined SPRs implemented by
the MPC750. For more information about these registers, see PowerPC Microprocessor Family: The
Programming Environments.
Table 2. Architecture-Defined SPRs Implemented by the MPC750
Register
Level
Function
LR
User
The link register (LR) can be used to provide the branch target address and to hold the
return address after branch and link instructions.
BATs
Supervisor
The architecture defines 16 block address translation registers (BATs), which operate in
pairs. There are four pairs of data BATs (DBATs) and four pairs of instruction BATs
(IBATs). BATs are used to define and configure blocks of memory.
CTR
User
The count register (CTR) is decremented and tested by branch-and-count instructions.
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Table 2. Architecture-Defined SPRs Implemented by the MPC750 (Continued)
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Register
Level
Function
DABR
Supervisor
The optional data address breakpoint register (DABR) supports the data address
breakpoint facility.
DAR
User
The data address register (DAR) holds the address of an access after an alignment or DSI
exception.
DEC
Supervisor
The decrementer register (DEC) is a 32-bit decrementing counter that provides a way to
schedule decrementer exceptions.
DSISR
User
The DSISR defines the cause of data access and alignment exceptions.
EAR
Supervisor
The external access register (EAR) controls access to the external access facility through
the External Control In Word Indexed (eciwx) and External Control Out Word Indexed
(ecowx) instructions.
PVR
Supervisor
The processor version register (PVR) is a read-only register that identifies the processor.
SDR1
Supervisor
SDR1 specifies the page table format used in virtual-to-physical page address translation.
SRR0
Supervisor
The machine status save/restore register 0 (SRR0) saves the address used for restarting
an interrupted program when a Return from Interrupt (rfi) instruction executes.
SRR1
Supervisor
The machine status save/restore register 1 (SRR1) is used to save machine status on
exceptions and to restore machine status when an rfi instruction is executed.
SPRG0–
SPRG3
Supervisor
SPRG0–SPRG3 are provided for operating system use.
TB
User: read The time base register (TB) is a 64-bit register that maintains the time of day and operates
Supervisor: interval timers. The TB consists of two 32-bit fields—time base upper (TBU) and time base
read/write lower (TBL).
XER
User
The XER contains the summary overflow bit, integer carry bit, overflow bit, and a field
specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or
Store String Word Indexed (stswx) instruction.
Table 3 describes the SPRs in the MPC750 that are not defined by the PowerPC architecture.
Table 3. MPC750-Specific Registers
Register
Level
Function
HID0
Supervisor The hardware implementation register 0 (HID0) provides checkstop enables and other
functions.
HID1
Supervisor The hardware implementation register 1 (HID1) allows software to read the configuration
of the PLL configuration signals.
IABR
Supervisor The instruction address breakpoint register (IABR) supports instruction address
breakpoint exceptions. It can hold an address to compare with instruction addresses in
the IQ. An address match causes an instruction address breakpoint exception.
ICTC
Supervisor The instruction cache-throttling control register (ICTC) has bits for controlling the interval
at which instructions are fetched into the instruction buffer in the instruction unit. This
helps control the MPC750’s overall junction temperature.
L2CR
Supervisor The L2 cache control register (L2CR) is used to configure and operate the L2 cache. It
has bits for enabling parity checking, setting the L2-to-processor clock ratio, and
identifying the type of RAM used for the L2 cache implementation. (The L2 cache feature
is not supported in the MPC740.)
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Table 3. MPC750-Specific Registers (Continued)
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Register
Level
Function
MMCR0–
MMCR1
Supervisor The monitor mode control registers (MMCR0–MMCR1) are used to enable various
performance monitoring interrupt functions. UMMCR0–UMMCR1 provide user-level read
access to MMCR0–MMCR1.
PMC1–
PMC4
Supervisor The performance monitor counter registers (PMC1–PMC4) are used to count specified
events. UPMC1–UPMC4 provide user-level read access to these registers.
SIA
Supervisor The sampled instruction address register (SIA) holds the EA of an instruction executing
at or around the time the processor signals the performance monitor interrupt condition.
The USIA register provides user-level read access to the SIA.
THRM1–
THRM2
Supervisor THRM1 and THRM2 provide a way to compare the junction temperature against two
user-provided thresholds. The thermal assist unit (TAU) can be operated so that the
thermal sensor output is compared to only one threshold, selected in THRM1 or THRM2.
THRM3
Supervisor THRM3 is used to enable the TAU and to control the output sample time.
UMMCR0–
UMMCR1
User
The user monitor mode control registers (UMMCR0–UMMCR1) provide user-level read
access to MMCR0–MMCR1.
UPMC1–
UPMC4
User
The user performance monitor counter registers (UPMC1–UPMC4) provide user-level
read access to PMC1–PMC4.
USIA
User
The user sampled instruction address register (USIA) provides user-level read access to
the SIA register.
2.2 Instruction Set
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent
among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This
fixed instruction length and consistent format greatly simplifies instruction pipelining.
2.2.1 PowerPC Instruction Set
The PowerPC instructions are divided into the following categories:
•
•
Integer instructions—These include computational and logical instructions.
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
Floating-point instructions—These include floating-point computational instructions, as well as
instructions that affect the FPSCR.
—
—
—
—
—
Floating-point arithmetic instructions
Floating-point multiply/add instructions
Floating-point rounding and conversion instructions
Floating-point compare instructions
Floating-point status and control instructions
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•
•
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•
•
Load/store instructions—These include integer and floating-point load and store instructions.
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
— Primitives used to construct atomic memory operations (lwarx and stwcx. instructions)
Flow control instructions—These include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow.
— Branch and trap instructions
— Condition register logical instructions
Processor control instructions—These instructions are used for synchronizing memory accesses
and management of caches, TLBs, and the segment registers.
— Move to/from SPR instructions
— Move to/from MSR
— Synchronize
— Instruction synchronize
— Order loads and stores
Memory control instructions—These instructions provide control of caches, TLBs, and SRs.
—
—
—
—
Supervisor-level cache management instructions
User-level cache instructions
Segment register manipulation instructions
Translation lookaside buffer management instructions
This grouping does not indicate the execution unit that executes a particular instruction or group of
instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and
word operand loads and stores between memory and a set of 32 GPRs. It also provides for word and doubleword operand loads and stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register, modified,
and then written back to the target location with distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the
flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous
event. Either kind of exception may cause one of several components of the system software to be invoked.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic.
A carry from bit 0 is ignored in 32-bit implementations.
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2.2.2 MPC750 Instruction Set
The MPC750 instruction set is defined as follows:
•
The MPC750 provides hardware support for all 32-bit PowerPC instructions.
•
The MPC750 implements the following instructions optional to the PowerPC architecture:
— External Control In Word Indexed (eciwx)
— External Control Out Word Indexed (ecowx)
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
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— Store Floating-Point as Integer Word (stfiwx)
2.3 On-Chip Cache Implementation
The following subsections describe the PowerPC architecture’s treatment of cache in general, and the
MPC750-specific implementation, respectively.
2.3.1 PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For example,
PowerPC processors can have unified caches, separate instruction and data caches (Harvard architecture),
or no cache at all. PowerPC microprocessors control the following memory access modes on a page or block
basis:
•
•
•
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
The caches are physically addressed, and the data cache can operate in either write-back or write-through
mode as specified by the PowerPC architecture.
The PowerPC architecture defines the term ‘cache block’ as the cacheable unit. The VEA and OEA define
cache management instructions a programmer can use to affect cache contents.
2.3.2 MPC750 Cache Implementation
The MPC750 cache implementation is described in Section 1.1.4, “On-Chip Instruction and Data Caches,”
and Section 1.1.5, “L2 Cache Implementation (Not Supported in the MPC740).” The BPU also contains a
64-entry BTIC that provides immediate access to cached target instructions. For more information, see
Section 1.1.2.2, “Branch Processing Unit (BPU).”
2.4 Exception Model
The following sections describe the PowerPC exception model and the MPC750 implementation.
2.4.1 PowerPC Exception Model
The PowerPC exception mechanism allows the processor to interrupt the instruction flow to handle certain
situations caused by external signals, errors, or unusual conditions arising from the instruction execution.
When exceptions occur, information about the state of the processor is saved to certain registers and the
processor begins execution at an address (exception vector) predetermined for each exception. Exception
processing occurs in supervisor mode.
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Although multiple exception conditions can map to a single exception vector, a more specific condition may
be determined by examining a register associated with the exception—for example, the DSISR and the
FPSCR. Additionally, some exception conditions can be enabled or disabled explicitly by software.
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The PowerPC architecture requires that exceptions be handled in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are handled in order. When
an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the
instruction stream, including any that are undispatched, are required to complete before the exception is
taken, and any exceptions those instructions cause must also be handled first. Likewise, asynchronous,
precise exceptions are recognized when they occur, but are not handled until the instructions currently in the
completion queue successfully retire or generate an exception, and the completion queue is emptied.
Unless a catastrophic condition causes a system reset or machine check exception, only one exception is
handled at a time. For example, if one instruction encounters multiple exception conditions, those conditions
are handled sequentially. After the exception handler handles an exception, the instruction processing
continues until the next exception condition is encountered. Recognizing and handling exception conditions
sequentially guarantees that exceptions are recoverable.
When an exception is taken, information about the processor state before the exception was taken is saved
in SRR0 and SRR1. Exception handlers should save the information stored in SRR0 and SRR1 early to
prevent the program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
•
•
•
•
24
Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are
handled precisely; that is, the machine state at the time the exception occurs is known and can be
completely restored. This means that (excluding the trap and system call exceptions) the address of
the faulting instruction is provided to the exception handler and that neither the faulting instruction
nor subsequent instructions in the code stream will complete execution before the exception is
taken. Once the exception is processed, execution resumes at the address of the faulting instruction
(or at an alternate address provided by the exception handler). When an exception is taken due to a
trap or system call instruction, execution resumes at an address provided by the handler.
Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point
exception modes, recoverable and nonrecoverable. Even though the MPC750 provides a means to
enable the imprecise modes, it implements these modes identically to the precise mode (that is,
enabled floating-point exceptions are always precise).
Asynchronous, maskable—The PowerPC architecture defines external and decrementer interrupts
as maskable, asynchronous exceptions. When these exceptions occur, their handling is postponed
until the next instruction, and any exceptions associated with that instruction, completes execution.
If no instructions are in the execution units, the exception is taken immediately upon determination
of the correct restart address (for loading SRR0). As shown in Table 4, the MPC750 implements
additional asynchronous, maskable exceptions.
Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset
and the machine check exception. These exceptions may not be recoverable, or may provide a
limited degree of recoverability. Exceptions report recoverability through the MSR[RI] bit.
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2.4.2 MPC750 Exception Implementation
The MPC750 exception classes described above are shown in Table 4.
Table 4. MPC750 Microprocessor Exception Classifications
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Synchronous/Asynchronous Precise/Imprecise
Exception Type
Asynchronous, nonmaskable
Imprecise
Machine check, system reset
Asynchronous, maskable
Precise
External, decrementer, system management, performance
monitor, and thermal management interrupts
Synchronous
Precise
Instruction-caused exceptions
Although exceptions have other characteristics, such as priority and recoverability, Table 4 describes
categories of exceptions the MPC750 handles uniquely. Table 4 includes no synchronous imprecise
exceptions; although the PowerPC architecture supports imprecise handling of floating-point exceptions,
the MPC750 implements these exception modes precisely. Table 5 lists MPC750 exceptions and conditions
that cause them. Exceptions specific to the MPC750 are indicated.
Table 5. Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System reset
00100
Assertion of either HRESET or SRESET or at power-on reset
Machine check
00200
Assertion of TEA during a data bus transaction, assertion of MCP, or an
address, data, or L2 bus parity error. MSR[ME] must be set.
DSI
00300
As specified in the PowerPC architecture. For TLB misses on load, store, or
cache operations, a DSI exception occurs if a page fault occurs.
ISI
00400
As defined by the PowerPC architecture.
External interrupt
00500
MSR[EE] = 1 and INT is asserted.
Alignment
00600
•
•
•
A floating-point load/store, stmw, stwcx., lmw, lwarx, eciwx or ecowx
instruction operand is not word-aligned.
A multiple/string load/store operation is attempted in little-endian mode.
The operand of dcbz is in memory that is write-through-required or
caching-inhibited or the cache is disabled
Program
00700
As defined by the PowerPC architecture.
Floating-point
unavailable
00800
As defined by the PowerPC architecture.
Decrementer
00900
As defined by the PowerPC architecture, when the most-significant bit of the
DEC register changes from 0 to 1 and MSR[EE] = 1.
Reserved
00A00–00BFF —
System call
00C00
Execution of the System Call (sc) instruction.
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Table 5. Exceptions and Conditions (Continued)
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Exception Type
Vector Offset
(hex)
Causing Conditions
Trace
00D00
MSR[SE] = 1 or a branch instruction completes and MSR[BE] = 1. Unlike the
architecture definition, isync does not cause a trace exception.
Reserved
00E00
The MPC750 does not generate an exception to this vector. Other PowerPC
processors may use this vector for floating-point assist exceptions.
Reserved
00E10–00EFF —
Performance monitor 1 00F00
The limit specified in a PMC register is reached and MMCR0[ENINT] = 1.
Instruction address
breakpoint 1
01300
IABR[0–29] matches EA[0–29] of the next instruction to complete, IABR[TE]
matches MSR[IR], and IABR[BE] = 1.
System management
interrupt 1
01400
MSR[EE] = 1 and SMI is asserted.
Reserved
01500–016FF —
Thermal management
interrupt 1
01700
Reserved
01800–02FFF —
Thermal management is enabled, the junction temperature exceeds the
threshold specified in THRM1 or THRM2, and MSR[EE] = 1.
1MPC750-specific
2.5 Memory Management
The following subsections describe the memory management features of the PowerPC architecture, and the
MPC750 implementation, respectively.
2.5.1 PowerPC Memory Management Model
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for
memory accesses and to provide access protection on blocks and pages of memory. There are two types of
accesses generated by the MPC750 that require address translation—instruction accesses, and data accesses
to memory generated by load, store, and cache control instructions.
The PowerPC architecture defines different resources for 32- and 64-bit processors; the MPC750
implements the 32-bit memory management model. The memory-management model provides 4 Gbytes of
logical address space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte
segment size. BAT block sizes range from 128 Kbyte to 256 Mbyte and are software selectable. In addition,
it defines an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses.
The architecture also provides independent four-entry BAT arrays for instructions and data that maintain
address translations for blocks of memory. These entries define blocks that can vary from 128 Kbytes to 256
Mbytes. The BAT arrays are maintained by system software.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory
management permits execution of programs larger than the size of physical memory; demand-paged implies
that individual pages are loaded into physical memory from system memory only when they are first
accessed by an executing program.
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The hashed page table is a variable-sized data structure that defines the mapping between virtual page
numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple
of its size. The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight
page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are
entry points for table search operations.
Setting MSR[IR] enables instruction address translations and MSR[DR] enables data address translations.
If the bit is cleared, the respective effective address is the same as the physical address.
2.5.2 MPC750 Memory Management Implementation
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The MPC750 implements separate MMUs for instructions and data. It implements a copy of the segment
registers in the instruction MMU, however, read and write accesses (mfsr and mtsr) are handled through
the segment registers implemented as part of the data MMU. The MPC750 MMU is described in
Section 1.1.3, “Memory Management Units (MMUs).”
The R (referenced) bit is updated in the PTE in memory (if necessary) during a table search due to a TLB
miss. Updates to the C (changed) bit are treated like TLB misses. A complete table search is performed and
the entire TLB entry is rewritten to update the C bit.
2.6 Instruction Timing
The MPC750 is a pipelined, superscalar processor. A pipelined processor is one in which instruction
processing is divided into discrete stages, allowing work to be done on different instructions in each stage.
For example, after an instruction completes one stage, it can pass on to the next stage leaving the previous
stage available to the subsequent instruction. This improves overall instruction throughput.
A superscalar processor is one that issues multiple independent instructions into separate execution units,
allowing instructions to execute in parallel. The MPC750 has six independent execution units, two for
integer instructions, and one each for floating-point instructions, branch instructions, load/store instructions,
and system register instructions. Having separate GPRs and FPRs allows integer, floating-point calculations,
and load and store operations to occur simultaneously without interference. Additionally, rename buffers are
provided to allow operations to post execution results for use by subsequent instructions without committing
them to the architected FPRs and GPRs.
As shown in Figure 6, the common pipeline of the MPC750 has four stages through which all instructions
must pass—fetch, decode/dispatch, execute, and complete/write back. Some instructions occupy multiple
stages simultaneously and some individual execution units have additional stages. For example, the floatingpoint pipeline consists of three stages through which all floating-point instructions must pass.
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Maximum four-instruction fetch per
clock cycle
Fetch
BPU
Maximum three-instruction dispatch per
clock cycle (includes one branch
instruction)
Dispatch
Execute Stage
FPU1
FPU2
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SRU
FPU3
LSU1
IU2
IU1
Complete (Write Back)
LSU2
Maximum two-instruction completion
per clock cycle
Figure 6. Pipeline Diagram
Note that Figure 6 does not show features, such as reservation stations and rename buffers that reduce stalls
and improve instruction throughput.
The instruction pipeline in the MPC750 has four major pipeline stages, described as follows:
•
The fetch pipeline stage primarily involves retrieving instructions from the memory system and
determining the location of the next instruction fetch. The BPU decodes branches during the fetch
stage and removes those that do not update CTR or LR from the instruction stream.
•
The dispatch stage is responsible for decoding the instructions supplied by the instruction fetch
stage and determining which instructions can be dispatched in the current cycle. If source operands
for the instruction are available, they are read from the appropriate register file or rename register
to the execute pipeline stage. If a source operand is not available, dispatch provides a tag that
indicates which rename register will supply the operand when it becomes available. At the end of
the dispatch stage, the dispatched instructions and their operands are latched by the appropriate
execution unit.
Instructions executed by the IUs, FPU, SRU, and LSU are dispatched from the bottom two positions
in the instruction queue. In a single clock cycle, a maximum of two instructions can be dispatched
to these execution units in any combination. When an instruction is dispatched, it is assigned a
position in the six-entry completion queue. A branch instruction can be issued on the same clock
cycle for a maximum three-instruction dispatch.
•
28
During the execute pipeline stage, each execution unit that has an executable instruction executes
the selected instruction (perhaps over multiple cycles), writes the instruction's result into the
appropriate rename register, and notifies the completion stage that the instruction has finished
execution. In the case of an internal exception, the execution unit reports the exception to the
completion pipeline stage and (except for the FPU) discontinues instruction execution until the
exception is handled. The exception is not signaled until that instruction is the next to be completed.
Execution of most floating-point instructions is pipelined within the FPU allowing up to three
instructions to be executing in the FPU concurrently. The FPU stages are multiply, add, and round-
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convert. Execution of most load/store instructions is also pipelined. The load/store unit has two
pipeline stages. The first stage is for effective address calculation and MMU translation and the
second stage is for accessing the data in the cache.
•
The complete pipeline stage maintains the correct architectural machine state and transfers
execution results from the rename registers to the GPRs and FPRs (and CTR and LR, for some
instructions) as instructions are retired. As with dispatching instructions from the instruction queue,
instructions are retired from the two bottom positions in the completion queue. If completion logic
detects an instruction causing an exception, all following instructions are cancelled, their execution
results in rename registers are discarded, and instructions are fetched from the appropriate
exception vector.
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Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction
timing varies among PowerPC processors.
2.7 Power Management
The MPC750 provides four power modes, selectable by setting the appropriate control bits in the MSR and
HID0 registers. The four power modes are as follows:
•
Full-power—This is the default power state of the MPC750. The MPC750 is fully powered and the
internal functional units are operating at the full processor clock speed. If the dynamic power
management mode is enabled, functional units that are idle will automatically enter a low-power
state without affecting performance, software execution, or external hardware.
•
Doze—All the functional units of the MPC750 are disabled except for the time base/decrementer
registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous
interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine
check brings the MPC750 into the full-power state. The MPC750 in doze mode maintains the PLL
in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to
the full-power state takes only a few processor clock cycles.
•
Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving only
the time base register and the PLL in a powered state. The MPC750 returns to the full-power state
upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer
exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from
a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK
is negated, the processor is put in doze mode to support snooping.
•
Sleep—Sleep mode minimizes power consumption by disabling all internal functional units, after
which external system logic may disable the PLL and SYSCLK. Returning the MPC750 to the fullpower state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external
asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check
input (MCP) signal after the time required to relock the PLL.
2.8 Thermal Management
The MPC750’s thermal assist unit (TAU) provides a way to control heat dissipation. This ability is
particularly useful in portable computers, which, due to power consumption and size limitations, cannot use
desktop cooling solutions such as fans. Therefore, better heat sink designs coupled with intelligent thermal
management is of critical importance for high performance portable systems.
Primarily, the thermal management system monitors and regulates the system’s operating temperature. For
example, if the temperature is about to exceed a set limit, the system can be made to slow down or even
suspend operations temporarily in order to lower the temperature.
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The thermal management facility also ensures that the processor’s junction temperature does not exceed the
operating specification. To avoid the inaccuracies that arise from measuring junction temperature with an
external thermal sensor, the MPC750’s on-chip thermal sensor and logic tightly couples the thermal
management implementation.
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The TAU consists of a thermal sensor, digital-to-analog convertor, comparator, control logic, and the
dedicated SPRs described in Section 2.1, “PowerPC Registers and Programming Model.” The TAU does the
following:
•
Compares the junction temperature against user-programmable thresholds
•
Generates a thermal management interrupt if the temperature crosses the threshold
•
Enables the user to estimate the junction temperature by way of a software successive
approximation routine
The TAU is controlled through the privileged mtspr/mfspr instructions to the three SPRs provided for
configuring and controlling the sensor control logic, which function as follows:
•
THRM1 and THRM2 provide the ability to compare the junction temperature against two userprovided thresholds. Having dual thresholds gives the thermal management software finer control
of the junction temperature. In single threshold mode, the thermal sensor output is compared to only
one threshold in either THRM1 or THRM2.
•
THRM3 is used to enable the TAU and to control the comparator output sample time. The thermal
management logic manages the thermal management interrupt generation and time multiplexed
comparisons in the dual threshold mode as well as other control functions.
Instruction cache throttling provides control of the MPC750’s overall junction temperature by determining
the interval at which instructions are fetched. This feature is accessed through the ICTC register.
2.9 Performance Monitor
The MPC750 incorporates a performance monitor facility that system designers can use to help bring up,
debug, and optimize software performance. The performance monitor counts events during execution of
code, relating to dispatch, execution, completion, and memory accesses.
The performance monitor incorporates several registers that can be read and written to by supervisor-level
software. User-level versions of these registers provide read-only access for user-level applications. These
registers are described in Section 2.1, “PowerPC Registers and Programming Model.” Performance monitor
control registers, MMCR0 or MMCR1 can be used to specify which events are to be counted and the
conditions for which a performance monitoring interrupt is taken. Additionally, the sampled instruction
address register, SIA (USIA), holds the address of the first instruction to complete after the counter
overflowed.
Attempting to write to a user-read-only performance monitor register causes a program exception,
regardless of the MSR[PR] setting.
When a performance monitoring interrupt occurs, program execution continues from vector offset 0x00F00.
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