AD AD7391AN 3 volt serial-input micropower 10-bit & 12-bit dac Datasheet

a
+3 Volt Serial-Input
Micropower 10-Bit & 12-Bit DACs
AD7390/AD7391
FEATURES
Micropower—100 mA
Single-Supply—12.7 to 15.5 V Operation
Compact 1.75 mm Height SO-8 Package
& 1.1 mm Height TSSOP-8
AD7390—12-Bit Resolution
AD7391—10-Bit Resolution
SPI & QSPI Serial Interface Compatible with Schmitt
Trigger Inputs
FUNCTIONAL DIAGRAM
AD7390
VOUT
12
CLR
GND
DAC REGISTER
LD
12
EN
CLK
SERIAL REGISTER
SDI
GENERAL DESCRIPTION
The AD7390/AD7391 family of 10-bit & 12-bit voltage-output
digital-to-analog converters is designed to operate from a single
13 V supply. Built using a CBCMOS process, these monolithic
DACs offer the user low cost, and ease-of-use in single-supply
13 V systems. Operation is guaranteed over the supply voltage
range of 12.7 V to 15.5 V consuming less than 100 µA making
this device ideal for battery operated applications.
The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail REFIN to DACOUT
allows for a full-scale voltage set equal to the positive supply
VDD or any value in between.
A doubled-buffered serial-data interface offers high speed,
three-wire, SPI and microcontroller compatible inputs using
data in (SDI), clock (CLK) and load strobe (LD) pins. Additionally, a CLR input sets the output to zero scale at power on
or upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without circuit card redesign.
The AD7390/AD7391 are specified over the extended industrial
(240°C to 185°C) temperature range. The AD7391AR is
specified for the 240°C to 1125°C automotive temperature
range. The AD7390/AD7391s are available in plastic DIP, and
low profile 1.75 mm height SO-8 surface mount packages. The
AD7391ARU is available for ultracompact applications in a thin
1.1 mm TSSOP-8 package.
2.0
1.00
AD7390
VDD = +3.0V
AD7390
0.75
1.5
0.50
1.0
0.25
0.5
INL – LSB
DNL – LSB
12-BIT DAC
REF
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
0.00
0.25
0.50
0
512
1024
1536 2048
2560
CODE – Decimal
VDD = +3.0V
VREF = +2.5V
258, 858C
0.0
20.5
2558
21.0
TA = 55 C, 25 C, 85 C
SUPERIMPOSED
0.75
1.00
VDD
21.5
3072
3584
4096
Figure 1. Differential Nonlinearity Error vs. Code
22.0
0
512
1024
1536
2048 2560
CODE – Decimal
3072
2584
4096
Figure 2. INL Error vs. Code & Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7390/AD7391–SPECIFICATIONS
AD7390 ELECTRICAL CHARACTERISTICS (@ V
REF IN
= 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
Parameter
Symbol
Conditions
3 V 6 10%
5 V 6 10%
Units
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Relative Accuracy2
Differential Nonlinearity2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Voltage Error
Full-Scale Tempco3
N
INL
INL
DNL
DNL
VZSE
VFSE
VFSE
TCVFS
TA = 125°C
TA = 240°C, 185°C
TA = 125°C, Monotonic
Monotonic
Data = 000H
TA = 125°C, 185°C, Data = FFFH
TA = 240°C, Data = FFFH
12
61.6
62.0
60.9
61
4.0
68
620
16
12
61.6
62
60.9
61
4.0
68
620
16
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
ppm/°C typ
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
VREF
RREF
CREF
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
1
3
100
1
3
100
mA typ
mA typ
pF typ
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
CIL
0.5
VDD20.6
10
10
0.8
VDD20.6
10
10
V max
V min
µA max
pF max
INTERFACE TIMING3, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
50
50
30
10
30
15
30
40
30
30
20
10
15
15
15
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS6
Output Slew Rate
Settling Time
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
Q
Q
VOUT/VREF
Data = 000H to FFFH to 000H
To 60.1% of Full Scale
Code 7FFH to 800H to 7FFH
0.05
70
65
15
263
0.05
60
65
15
263
V/µs typ
µs typ
nVs typ
nVs typ
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
IDD
PDISS
PSS
DNL < 61 LSB
VIL = 0 V, No Load, TA = 125°C
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = 65%
2.7/5.5
55
100
300
0.003
2.7/5.5
55
100
500
0.006
V min/max
µA typ
µA max
µW max
%/% max
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
No Oscillation
VREF = 1.5 VDC 11 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF /4096 V for the 12-bit AD7390.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. 0
SPECIFICATIONS
AD7390/AD7391
AD7391 ELECTRICAL CHARACTERISTICS (@ V
Parameter
Symbol
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
N
INL
INL
DNL
VZSE
VFSE
Full-Scale Voltage Error
Full-Scale Tempco3
VFSE
TCVFS
REF IN
= 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
Conditions
TA = 125°C
TA = 240°C, 185°C, 1125°C
Monotonic
Data = 000H
TA = 125°C, 185°C, 1125°C,
Data = 3FFH
TA = 240°C, Data = 3FFH
3 V 6 10%
5 V 6 10%
Units
10
61.75
62.0
60.9
9.0
632
10
61.75
62.0
60.9
9.0
632
Bits
LSB max
LSB max
LSB max
mV max
mV max
635
16
635
16
mV max
ppm/°C typ
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
1
3
100
1
3
100
mA typ
mA typ
pF typ
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
VREF
RREF
CREF
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
CIL
0.5
VDD20.6
10
10
0.8
VDD20.6
10
10
V min
V max
µA max
pF max
INTERFACE TIMING3, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
50
50
30
10
30
15
30
40
30
30
20
10
15
15
15
20
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS6
Output Slew Rate
Settling Time
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
Q
Q
VOUT/VREF
Data = 000H to 3FFH to 000H
To 60.1% of Full Scale
Code 7FFH to 800H to 7FFH
0.05
70
65
15
263
0.05
60
65
15
263
V/µs typ
µs typ
nVs typ
nVs typ
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
IDD
PDISS
PSS
DNL < 61 LSB
VIL = 0 V, No Load, TA = 125°C
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = 65%
2.7/5.5
55
100
300
0.003
2.7/5.5
55
100
500
0.006
V min/max
µA typ
µA max
µW max
%/% max
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
No Oscillation
VREF = 1.5 VDC 11 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF /1024 V for the 10-bit AD7391.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. 0
–3–
AD7390/AD7391
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 V, 18 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD 1 0.3 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . 20.3 V, 18 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . 20.3 V, VDD 1 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX 2 TA)/θJA
Thermal Resistance θJA
8-Pin Plastic DIP Package (N-8) . . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . 240°C to 1 85°C
Storage Temperature Range . . . . . . . . . . . . 265°C to 1150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 1300°C
SO-8
TSSOP-8
TOP
VIEW
(Not to
Scale)
2
3
4
8
1
8
1
7
TOP VIEW
(Not
to
Scale)
6
3
2
7
6
5
4
5
P-DIP-8
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational specification is not implied. Exposure to the above maximum rating
conditions for extended periods may affect device reliability.
LD
1
CLK
2
SDI
3
CLR
4
ORDERING GUIDE
TOP VIEW
(Not to Scale)
8
VREF
7
VDD
6
VOUT
5
GND
PIN DESCRIPTIONS
Model
Res
Temp
Package
Description
Package
Option
AD7390AN
AD7390AR
AD7391AN
AD7391AR
AD7391ARU
12
12
10
10
10
XIND
XIND
XIND
AUTO
XIND
8-Pin P-DIP
8-Lead SOIC
8-Pin P-DIP
8-Lead SOIC
TSSOP-8
N-8
SO-8
N-8
SO-8
RU-8
NOTES
XIND = 240°C to 185°C; AUTO = 240°C to 1125°C
The AD7390 contains 558 transistors. The die size measures 70 mil X 68 mil.
CLR
RESET
LD
LOAD
Pin No.
Name
Function
1
LD
2
CLK
3
SDI
4
CLR
5
6
GND
VOUT
7
VDD
8
VREF
Load Strobe. Transfers shift register
data to DAC register while active low.
See truth table for operation.
Clock Input. Positive edge clocks data
into shift register.
Serial Data Input. Data loads directly
into the shift register.
Resets DAC register to zero condition.
Active low input.
Analog & Digital Ground.
DAC Voltage Output. Full-scale output
1 LSB less than reference input voltage
REF.
Positive Power Supply Input. Specified
range of operation 12.7 V to 15.5 V.
DAC Reference Input Pin. Establishes
DAC full-scale voltage.
DAC
REGISTER
12
CLK
CLK
SDI
D
12-BIT AD7390*
SHIFT REGISTER
* NOTE: AD7391 HAS A 10-BIT SHIFT REGISTER
Figure 3. Digital Control Logic
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD7390/AD7391
SDI
D11
D10
AD7390
CLK
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AD7391
tLD1
tLD2
tLD1
LD
DAC REGISTER LOAD
SDI
tDS
tDH
tCL
CLK
tCH
tLDW
LD
CLR
tCLRW
tS
FS
0.1% FS
ERROR BAND
VOUT
ZS
tS
Figure 4. Timing Diagram
Table I. Control-Logic Truth Table
CLK
CLR
LD
Serial Shift Register Function
DAC Register Function
↑
X
X
X
X
H
H
L
↑
↑
H
L
X
H
L
Shift-Register-Data Advanced One-Bit
Disables
No Effect
No Effect
Disabled
Latched
Updated with Current Shift Register Contents
Loaded with all Zeros
Latched with all Zeros
Previous SR Contents Loaded (Avoid usage of CLR
when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)
NOTES
1
↑ = Positive logic transition.
2
X = Don’t care.
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB
AD7390
LSB
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB
AD7391
REV. 0
LSB
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
–5–
AD7390/AD7391–Typical Performance Characteristics
25
100
AD7390
SS = 100 units
TA = 25 C
VDD = 2.7V
VREF = 2.5V
SS = 300 units
TA = 258C
VDD = 2.7V
VREF = 2.5V
80
15
10
AD7391
60
50
40
SS = 100 units
TA = 2408 to 858C
VDD = 2.7V
VREF = 2.5V
24
FREQUENCY
70
FREQUENCY
FREQUENCY
20
30
AD7391
90
18
12
30
5
20
6
10
0
5.0 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
TOTAL UNADJUSTED ERROR – LSB
Figure 5. AD7390 Total Unadjusted
Error Histogram
Figure 6. AD7391 Total Unadjusted
Error Histogram
16
12
10
8
6
4
SUPPLY CURRENT – µA
90
85
AD7390
80
TA = 25 C
VDD = 3.0V
75
70
65
2
10
100
1K
FREQUENCY – Hz
10K
100K
Figure 8. Voltage Noise Density vs.
Frequency
1.0
1.5
2.0
VIN – Volts
2.5
VLOGIC = 0V TO VDD TO 0V
VREF = 2.5V
TA = 25 C
70
60
50
VDD = 3.0V, VLOGIC = 0V
40
SUPPLY CURRENT – µA
SAMPLE SIZE = 300 UNITS
VDD = 5.0V, VLOGIC = 0V
800
35
15
5 25 45 65 85 105 125
TEMPERATURE – C
Figure 11. Supply Current vs.
Temperature
VLOGIC FROM
LOW TO HIGH
1.0
1
2
3
4
5
SUPPLY VOLTAGE – V
7
6
Figure 10. Logic Threshold vs. Supply
Voltage
VDD = 5V
5%
40
600
400
a. VDD = 5.5V, CODE = 155H
b. VDD = 5.5V, CODE = 3FFH
c. VDD = 2.7V, CODE = 155H
d. VDD = 2.7V, CODE = 355H
a b
0
1K
VDD = 3V
5%
30
20
200
55
1.5
50
10
30
20
2.0
TA = 25 C
AD7391
VDD = 3.6V, VLOGIC = 2.4V
VLOGIC FROM
HIGH TO LOW
2.5
60
AD7390
80
3.0
3.0
1000
90
LOGIC VOLTAGE
VARIED
3.5
0.0
0.5
Figure 9. Supply Current vs. Logic
Input Voltage
100
CODE = FFFH
VREF = 2V
4.0
0.5
55
50
0.0
0
AD7390
4.5
VLOGIC FROM
0V TO 3.0V
60
0
1
SUPPLY CURRENT – µA
5.0
VLOGIC FROM
3.0V TO 0V
PSRR – dB
OUTPUT VOLTAGE NOISE – µV/√Hz
VDD = 5V
VREF = 2.5V
TA = 25 C
95
–33 –30 –26 –23 –20 –16 –13 –10 –6 –3
FULL SCALE TEMPCO – ppm/°C
Figure 7. AD7391 Full-Scale Output
Tempco Histogram
100
AD7390
14
0
–10 –3.3 3.3 10 16 23 30 36 43 50
TOTAL UNADJUSTED ERROR – LSB
THRESHOLD VOLTAGE – V
0
d c
10K
100K
1M
CLOCK FREQUENCY – Hz
10M
Figure 12. Supply Current vs. Clock
Frequency
–6–
0
10
100
1K
FREQUENCY – Hz
10K
Figure 13. Power Supply Rejection vs.
Frequency
REV. 0
AD7390/AD7391
40
IOUT – mA
fCLK = 50KHz
VOUT
(5mV/DIV)
30
VDD = 5V
VREF = 2.5V
5µs
AD7390
2µs
VOUT
(5mV/DIV)
VDD = +5V
VREF = +3V
CODE = ØØØH
= HIGH
20
VDD = 5V
VREF = 2.5V
10
(5V/DIV)
fCLK = 50KHz
CODE: 7FH to 80H
20mV
0
0
1
2
3
VOUT – V
4
5
Figure 14. IOUT at Zero Scale vs. VOUT
TIME – 2µs/DIV
TIME – 5µs/DIV
Figure 15. Midscale Transition
Performance
Figure 16. Digital Feedthrough
5
2.0
INTEGRAL NONLINEARITY – LSB
AD7390
100µs
0
5
GAIN – dB
VOUT
(1V/DIV)
VDD = 5V
VREF = 2.5V
(5V/DIV)
fCLK = 50KHz
CLK
(5V/DIV)
5mV
10
VDD = +5V
VREF = +100mV + 2VDC
DATA = FFFH
15
20
25
AD7390
1.8
VDD = +5V
CODE = 768H
TA = 25 C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1V
30
10
TIME – 100µs/div
Figure 17. Large Signal Settling Time
100
1K
10K
FREQUENCY – Hz
Figure 18. Reference Multiplying
Bandwidth
NOMINAL CHANGE IN VOLTAGE – mV
1.2
AD7390
SAMPLE SIZE = 50
1.0
0.8
CODE = FFFH
0.6
0.4
CODE = 000H
0.2
0.0
0
200
300
400
500
100
HOURS OF OPERATION AT 150°C
600
Figure 20. Long-Term Drift
Accelerated by Burn-In
REV. 0
100K
–7–
0.0
0
1
2
3
4
REFERENCE VOLTAGE – V
5
Figure 19. INL Error vs. Reference
Voltage
AD7390/AD7391
VDD
OPERATION
P-CH
The AD7390 and AD7391 are a set of pin compatible, 12-bit/10bit digital-to-analog converters. These single-supply operation
devices consume less than 100 microamps of current while operating from power supplies in the 12.7 V to 15.5 V range
making them ideal for battery operated applications. They contain a voltage-switched, 12-bit/10-bit, laser-trimmed digital-toanalog converter, rail-to-rail output op amps, serial-input
register, and a DAC register. The external reference input has
constant input resistance independent of the digital code setting
of the DAC. In addition, the reference input can be tied to the
same supply voltage as VDD resulting in a maximum output voltage span of 0 to VDD . The SPI compatible, serial-data interface
consists of a serial data input (SDI), clock (CLK), and load
(LD) pins. A CLR pin is available to reset the DAC register to
zero-scale. This function is useful for power-on reset or system
failure recovery to a known state.
N-CH
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage provides 61 mA of output current.
The N-channel output pull-down MOSFET shown in Figure 21
has a 35 Ω ON resistance, which sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier has also been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input-resistance independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2 MΩ inputresistance minimizes power dissipation within the AD7390/
AD7391 D/A converters. The VREF input accepts input voltages
ranging from ground to the positive-supply voltage VDD . One of
the simplest applications which saves an external reference voltage source is connection of the VREF terminal to the positive
VDD supply. This connection results in a rail-to-rail voltage output span maximizing the programmed range. The reference input will accept ac signals as long as they are kept within the
supply voltage range, 0 < VREF IN < VDD. The reference
bandwidth and integral nonlinearity error performance are plotted in the typical performance section, see Figures 18 and 19.
The ratiometric reference feature makes the AD7390/AD7391
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
VREF pin according to the following equation:
D
Equation 1
2N
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7391 using a 2.5 V reference, Equation 1
simplifies to:
VOUT = VREF 3
VOUT = 2.5 3
D
1024
Equation 2
Using Equation 2 the nominal midscale voltage at VOUT is
1.25 V for D = 512; full-scale voltage is 2.497 volts. The LSB
step size is = 2.5 3 1/1024 = 0.0024 volts.
For the 12-bit AD7390 operating from a 5.0 V reference Equation 1 becomes:
VOUT = 5.0 3
D
4096
VOUT
POWER SUPPLY
The very low power consumption of the AD7390/AD7391 is a direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for the
logic, and the low noise, tight-matching of the complementary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD7390/
AD7391 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 12.7 V to 15.5 V.
Equation 3
Using Equation 3 the AD7390 provides a nominal midscale
voltage of 2.5 V for D =2048, and a full-scale output of 4.998 V.
The LSB step size is = 5.0 3 1/4096 = 0.0012 volts.
AMPLIFIER SECTION
POWER SUPPLY BYPASSING AND GROUNDING
The internal DAC’s output is buffered by a low power consumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 21
shows an equivalent output schematic of the rail-to-rail amplifier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
Precision analog products, such as the AD7390/AD7391, require a well filtered power source. Since the AD7390/AD7391
operates from a single 13 V to 15 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which
generates noise in the 20 kHz to 1 MHz range. In addition, fast
logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistance and inductance. The power supply
noise generated thereby means that special care must be taken
to assure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the AD7390.
–8–
REV. 0
AD7390/AD7391
The AD7390 should be powered directly from the system power
supply. This arrangement, shown in Figure 22, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients.
VDD
LOGIC
IN
GND
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
Figure 24. Equivalent Digital Input ESD Protection
+5V
TTL/CMOS
LOGIC
CIRCUITS
100µF
ELECT.
10-22µF
TANT.
In order to minimize power dissipation from input-logic levels
that are near the VIH and VIL logic input voltage specifications, a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 9 shows a plot of incremental input voltage versus
supply current showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions. A
secondary advantage of this Schmitt trigger, is the prevention of
false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or opto isolators
are used. The logic inputs SDI, CLK, LD, CLR all contain the
Schmitt trigger circuits.
0.1µF
CER.
+5V
RETURN
+5V
POWER SUPPLY
Figure 22. Use Separate Traces to Reduce Power Supply Noise
Whether or not a separate power supply trace is available, however, generous supply bypassing will reduce supply-line induced
errors. Local supply bypassing consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended in all applications (Figure 23).
DIGITAL INTERFACE
The AD7390/AD7391 have a double-buffered serial data input.
The serial-input register is separate from the DAC register,
which allows preloading of a new data value into the serial register without disturbing the present DAC values. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the control logic inputs.
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit AD7390 DAC value. If
additional bits are clocked into the shift register, for example
when a microcontroller sends two 8-bit bytes, the MSBs are ignored (Figure 25). The CLK pin is only enabled when Load
(LD) is high. The lower resolution 10-bit AD7391 contains a
10-bit shift register. The AD7391 is also loaded MSB first with
10 bits of data. Again if additional bits are clocked into the shift
register, only the last 10 bits clocked in are used.
+2.7V to +5.5V
*
LD
CLK
SDI
CLR
C
8
7
REF
VDD
1
2
3
0.1 µF 1 10 µF
AD7390
or
AD7391
4
6
VOUT
GND
5
* OPTIONAL EXTERNAL
REFERENCE BYPASS
Figure 23. Recommended Supply Bypassing for the
AD7390/AD7391
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection structure (Figure 24) that allows logic input voltages to exceed the VDD supply voltage. This feature can be useful if the
user is driving one or more of the digital inputs with a 5 V
CMOS logic input-voltage level while operating the AD7390/
AD7391 on a 13 V power supply. If this mode of interface is
used, make sure that the VOL of the 5 V CMOS meets the VIL
input requirement of the AD7390/AD7391 operating at 3 V.
See Figure 10 for a graph for digital logic input threshold versus
operating VDD supply voltage.
The Load pin (LD) controls the flow of data from the shift register to the DAC register. After a new value is clocked into the
serial-input register, it will be transferred to the DAC register by
the negative transition of the Load pin (LD).
BYTE 1
BYTE 0
MSB
LSB
MSB
LSB
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
D11
D!0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11_D0: 12-BIT AD7390 DAC VALUE; D9_D0 10-BIT AD7391 DAC VALUE
X = DON’T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC
Figure 25. Typical AD7390-Microprocessor Serial Data Input Forms
REV. 0
–9–
AD7390/AD7391
RESET (CLR) PIN
Forcing the CLR pin low will set the DAC register to all zeros
and the DAC output voltage will be zero volts. The reset function is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor controllers are two of many applications which benefit from powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor. CLR has a Schmitt trigger input which results in
a clean reset function when using external resistor/capacitor
generated pulses. The CLR input overrides other logic inputs,
specifically LD. However, LD should be set high before CLR
goes high. If CLR is kept low, then the contents of the shift register will be transferred to the DAC register as soon as CLR returns high. See the Control-Logic Truth Table I.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7390. As shown
in Figure 26, the AD7390 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this operation is shown in Table IV.
+2.7V to +5.5V
R
0.01µF
0.1µF
1 10µF
7
EXT
REF
REF
LD
µC
RS
3
VDD
AD7390
CLK 2
SDI
VOUT
1
CLR 4
GND
5
sumption OP196 has been designed just for this purpose and results in only 50 microamps of maximum current consumption.
Connection of the equal valued 470 kΩ resistors results in a differential amplifier mode of operation with a voltage gain of two,
which results in a circuit output span of ten volts, that is, 25 V
to 15 V. As the DAC is programmed with zero-code 000H to
midscale 200H to full-scale 3FFH, the circuit output voltage VO
is set at 25 V, 0 V and 15 V (minus 1 LSB). The output voltage VO is coded in offset binary according to Equation 4.
VO =
D
3 1 512
2 214 3 5
Equation 4
where D is the decimal code loaded in the AD7391 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including
the 470 kΩ gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same material, such as metal film). If better stability is
required the power supply could be substituted with a precision
reference voltage such as the low dropout REF195, which can
easily supply the circuit’s 162 µA of current, and still provide
additional power for the load connected to VO. The micropower
REF195 is guaranteed to source 10 mA output drive current,
but only consumes 50 µA internally. If higher resolution is required, the AD7390 can be used with the addition of two more
bits of data inserted into the software coding, which would result in a 2.5 mV LSB step size. Table V shows examples of
nominal output voltages VO provided by the Bipolar Operation
circuit application.
6
ISY < 162µA
RL
≥ 5kΩ
CL
≤ 100pF
15V
470kΩ
Figure 26. AD7390 Unipolar Output Operation
< 100µA
Decimal
Number
in DAC Register
Output
Voltage (V)
VREF = 2.5 V
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.4994
1.2506
1.2500
1.2494
0
The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or reference depending on the application performance requirements.
< 50µA
15V
Table IV. AD7390 Unipolar Code Table
Hexadecimal
Number
in DAC Register
470kΩ
REF
VO
VDD
AD7391
BIPOLAR
OUTPUT
SWING
OP196
C
VOUT
1
25V
GND
25V
DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
Figure 27. Bipolar Output Operation
Table V. Bipolar Code Table
Hexadecimal
Number
In DAC Register
Decimal
Number
in DAC Register
Analog
Output
Voltage (V)
3FF
201
200
1FF
000
1023
513
512
511
0
4.9902
0.0097
0.0000
-0.0097
-5.0000
BIPOLAR OUTPUT OPERATION
Although the AD7391 has been designed for single-supply operation, the output can be easily configured for bipolar operation. A typical circuit is shown in Figure 27. This circuit uses a
clean regulated 15 V supply for power, which also provides the
circuit’s reference voltage. Since the AD7391 output span
swings from ground to very near 15 V, it is necessary to choose
an external amplifier with a common-mode input voltage range
that extends to its positive supply rail. The micropower con-
–10–
REV. 0
AD7390/AD7391
MICROCOMPUTER INTERFACES
The AD7390 serial data input provides an easy interface to a variety of single-chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for communicating with the DAC. In cases where no serial port is provided,
or it is being used for some other purpose (such as an RS-232
communications interface), the AD7390/AD7391 can easily be
addressed in software.
Twelve data bits are required to load a value into the AD7390.
If more than 12 bits are transmitted before the load LD input
goes high, the extra (i.e., the most-significant) bits are ignored.
This feature is valuable because most µCs only transmit data in
8-bit increments. Thus, the µC sends 16 bits to the DAC instead of 12 bits. The AD7390 will only respond to the last
12 bits clocked into the SDI input, however, so the serial-data
interface is not affected.
Ten data bits are required to load a value into the AD7391. If
more than 10 bits are transmitted before load LD returns high,
the extra bits are ignored.
REV. 0
–11–
AD7390/AD7391
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
8-Pin Plastic DIP (N-8)
0.1968 (5.00)
0.1890 (4.80)
4
0.280 (7.11)
0.240 (6.10)
1
4
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
5
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.210 (5.33)
MAX
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.0500 (1.27)
0.0160 (0.41)
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
C2151–18–7/96
1
8
0.2440 (6.20)
0.2284 (5.80)
8-Pin TSSOP (RU-8)
0.122 (3.10)
0.114 (2.90)
8
5
1
4
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
SEATING
PLANE
5
0.256 (6.50)
0.246 (6.25)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
8
0.177 (4.50)
0.169 (4.30)
0.1574 (4.00)
0.1497 (3.80)
0.430 (10.92)
0.348 (8.84)
–12–
REV. 0
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