Fairchild DM74S174N Hex/quad d flip-flop with clear Datasheet

Revised April 2000
DM74S174 • DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
Features
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (DM74S175) versions feature complementary outputs from each flip-flop.
■ DM74S174 contain six flip-flops with single-rail outputs.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
■ Individual data input to each flip-flop
■ DM74S175 contain four flip-flops with double-rail outputs.
■ Buffered clock and direct clear inputs
■ Applications include:
Buffer/storage registers
Shift registers
Pattern generators
■ Typical clock frequency 110 MHz
■ Typical power dissipation per flip-flop 75mW
Ordering Code:
Order Number
Package Number
Package Description
DM74S174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74S175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S174
© 2000 Fairchild Semiconductor Corporation
DM74S175
DS006472
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DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear
August 1986
DM74S174 • DM74S175
Function Table
(Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
Q (Note 1)
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady-state input conditions were established.
Note 1: DM74S175 only.
Logic Diagrams
DM74S174
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DM74S175
2
Supply Voltage
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
7V
Input Voltage
5.5V
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.75
5
5.25
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−1
mA
IOL
LOW Level Output Current
fCLK
Clock Frequency (Note 3)
fCLK
Clock Frequency (Note 4)
tW
Pulse Width
tSU
tH
tREL
TA
2
V
V
20
mA
0
110
75
MHz
0
90
65
MHz
Clock
7
(Note 3)
Clear
10
Pulse Width
Clock
9
(Note 4)
Clear
12
Data Setup Time (Note 3)
5
Data Setup Time (Note 4)
7
Data Hold Time (Note 3)
3
Data Hold Time (Note 4)
5
Clear Release Time (Note 3)
5
Clear Release Time (Note 4)
7
Free Air Operating Temperature
0
ns
ns
ns
ns
70
°C
Note 3: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 4: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
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DM74S174 • DM74S175
Absolute Maximum Ratings(Note 2)
DM74S174 • DM74S175
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
Min
2.7
Typ
(Note 5)
Max
Units
−1.2
V
3.4
V
0.5
V
mA
II
Input Current @ Max Input Voltage
VCC = Max, VI = 5.5V
1
IIH
HIGH Level Input Current
VCC = Max, VI = 2.7V
50
µA
IIL
LOW Level Input Current
VCC = Max, VI = 0.5V
−2
mA
IOS
Short Circuit Output Current
VCC = Max (Note 6)
−100
mA
ICC
Supply Current (DM74S174)
VCC = Max (Note 7)
90
144
mA
ICC
Supply Current (DM74S175)
VCC = Max (Note 7)
60
96
mA
−40
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN and 4.5V applied to all DATA and CLEAR inputs, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK
input.
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 280Ω
Symbol
Parameter
From (Input)
To (Output)
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output (DM74S175 Only)
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
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CL = 15 pF
Min
Max
75
CL = 50 pF
Min
Units
Max
65
MHz
Clock to Output
12
15
ns
Clock to Output
17
21
ns
Clear to Q
15
18
ns
Clear to Q
22
23
ns
4
DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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5
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