SPT5510 16-BIT, 200 MWPS ECL D/A CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • 16-Bit, 200 MWPS digital-to-analog converter Differential linearity of ±0.6 LSB (typical) Integral linearity of ±0.75 LSB (typical) Fast settling time: 35 ns to 0.0008%; 25 ns to 0.01% Low glitch energy On-chip voltage reference ECL compatibility GENERAL DESCRIPTION The SPT5510 is a 16-bit, 200 MWPS digital-to-analog converter designed for high-resolution waveform synthesis for test and measurement instrumentation applications. It features true 16-bit linearity, with differential non-linearity of typically ±0.6 LSB and integral non-linearity of ±0.75 LSB. It High-precision arbitrary waveform generation Test and measurement instrumentation Digital waveform synthesis Microwave and satellite modems Disk drive test equipment Industrial process control Military applications has a very high-speed update rate of up to 200 MHz and is ECL compatible. It has an ultrafast settling time of 25 ns to 0.01% and 35 ns to 0.0008%. The SPT5510 operates over an industrial temperature range of –40 °C to +85 °C and is available in a 10 x 10 mm, 44-lead metric quad flat pack (MQFP) plastic package. BLOCK DIAGRAM REFIN D15–D12 Digital Inputs D15–D0 16 MSB Decoder 16 MSB Latch 16 Input Latch IOUT IOUT IOUT Bias D11–D0 12 LSB Buffer LSB Latch 12 Current Cells IOUT CLK Bandgap Reference BGOUT Bias RSET AMPINB + – Ref Amp Reference Cell 20 AMPOUT 10 AMPCC ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 Supply Voltages Negative supply voltage (VEE) ................................. –7 V A/D ground voltage differential ................................ 0.5 V Output Currents Bandgap reference output current ..................... ±500 µA Ref amplifier output current ................................ ±2.5 mA Input Voltages Digital input voltage (D15–D0, Clock)... ........... –2.5 to 0 V Ref amp input voltage range .......................... –2.5 to 0 V Reference input voltage range (Ref In) ...... VEE to –2.5 V Temperature Operating temperature ............................... –40 to +85 °C Junction temperature .......................................... +150 °C Lead, soldering (10 seconds) ............................. +250 °C Storage .................................................... –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal operating conditions. ELECTRICAL SPECIFICATIONS TA= 25 °C, VEE=–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. PARAMETERS DC Performance1 Resolution Differential Linearity Differential Linearity Integral Linearity Integral Linearity Integral Linearity Drift Offset Drift Monotonicity Output Capacitance Gain Error Gain Error Tempco Gain Error Tempco Offset Error Compliance Voltage Output Resistance Dynamic Performance Conversion Rate Settling Time tST2 Delay Time tD Glitch Energy Full Scale Output Current Rise Time/Fall Time Spurious Free Dynamic Range ƒOUT=5 MHz; ƒCLOCK=30 MHz ƒOUT=10 MHz; ƒCLOCK=100 MHz 1Measured 2Measured TEST CONDITIONS TEST LEVEL TMIN–TMAX TMIN–TMAX TMIN–TMAX With Ext Reference With Internal Bandgap Ref Settling to ±0.01% Settling to ±0.0008% MIN VI IV VI IV IV IV V V I V V I IV IV –1.95 –4.0 –1.95 –4.0 –0.2 –2.5 15 IV 200 –2 –4 –1.2 0.88 SPT5510 TYP 16 ±0.6 ±1.0 ±0.75 ±1.5 10 0.4 50 50 1.1 MAX 1.95 4.0 1.95 4.0 0.2 2.5 2 4 2 1.32 UNITS Bits LSB LSB LSB LSB LSB/°C ppm FS/°C Bits pF % FS ppm FS/°C ppm FS/°C µA V kΩ MHz With On-Chip References RL = 50 Ω V V V V V V 25 35 2 30 19 2 ns ns ns pV-s mA ns 10 MHz Span 10 MHz Span V V 84 76 dB dB at 0 V output using I-V. as voltage settling for mid-scale transition; RL = 50 Ω. SPT5510 2 9/27/00 ELECTRICAL SPECIFICATIONS TA= 25 °C, VEE=–5.2 V ±5%, 50% duty cycle clock, unless otherwise specified. TEST PARAMETERS Power Supply Requirements Negative Supply Current (–5.2 V) Nominal Power Dissipation Power Supply Rejection Ratio Voltage Input and Control Bandgap Reference Voltage Bandgap Output Current Ref Amp Bandwidth3 Ref Amp Input Current Ref Amp Output Current Ref In Operating Voltage Digital Inputs Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Clock Pulse Width (tPWH) 3Ref TEST CONDITIONS LEVEL TMIN –TMAX VI V I ∆V Supply = ±5 % V IV V V V V TA=25 °C ±10 °C TMIN –TMAX TMIN –TMAX –0.8 V –1.8 V VI VI V V V IV IV IV SPT5510 MIN TYP –0.6 115 600 ±0.002 –110 –1.0 –1.2 16 40 16 200 –3.4 –0.8 –1.7 2.5 0 3 MAX UNITS 150 800 0.6 mA mW % FS 220 –1.5 3.0 0.5 1.5 V µA MHz µA µA V V V µA µA pF ns ns ns Amp Bandwidth is limited by its compensation network TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT5510 3 9/27/00 THEORY OF OPERATION POWER SUPPLY AND GROUNDING The SPT5510 is a segmented 16-bit current-output DAC. The four MSBs, D15–D12, are decoded to fifteen unit cells (current sinks). The remaining bits (D11–D0) are binary; bits D9–D0 are derived from an R-2R ladder. All cells are laser trimmed for maximum accuracy. The block diagram shows the basic architecture. The SPT5510 requires a single –5.2V power supply. All supply pins attach to a common on-chip power bus and should be treated as analog supplies. For best settling performance, each supply pin should be decoupled as shown in figure 1 – typical interface circuit. 47 pF C11 .01 µF AMPOUT AMPB 21 20 15 19 AMPCC 17 RSET 18 AMPINB 16 BGOUT REFIN Output SPT5510 D8 D7 D6 D5 IOUT AVEE AVEE AVEE AVEE AVEE AVEE AVEE 39 43 11 13 14 23 34 38 AVEE OGND OGND OGND OGND Output Complementary 36 FB R6 10 .01 µF .01 µF .01 µF C4 C5 C6 R5 10 R4 10 .01 µF C3 R3 10 R2 10 .01 µF 2.2 µF C17 C2 2.2 µF C16 .01 µF 2.2 µF C15 C1 2.2 µF R1 10 AVEE C14 C1–C13 — SURFACE MOUNT CERAMIC CHIP C14–C17 — TANTALUM R1–R6 — CARBON FILM 1/4 W R7–R10 — SURFACE MOUNT CERAMIC CHIP FB — FERRITE BEAD is to be located as closely to the device as possible. 40 42 35 37 D2 D1 D0 DGND D4 D3 44 10 24 30 31 32 41 D10 D9 DGND 28 29 IOUT 33 26 27 12 REFGND CLK 7 8 25 Input Data D12 D11 DGND 5 6 D15 D14 D13 DGND 1 2 3 4 REFGND 50 9 R10 22 R8 C8 R7 1K C7 AVEE 47 pF 10 pF C10 C12 47 pF 20 pF C9 C13 1K .01 µF Figure 1 – Typical Interface Circuit R9 The reference loop utilizes an MSB-weighted cell and provides a gain of about 16 to the output. The on-chip reference amplifier has very high open-loop gain and is offset trimmed to provide a very low temperature drift (typically <10 ppm/°C gain drift). 50 There are three separate on-chip ground busses. DGND pins should be tied together and connected to system ground through a ferrite bead. REFGND and OGND pins should be tied directly to the SPT5510’s ground plane and connected to system ground through a ferrite bead. It is critical that REFGND and OGND are very tightly coupled, as any differential signal (dc offset, noise, etc.) will be transmitted to the output. Two of the OGND pins can be disconnected from the ground plane and used as sense lines for a current-to-voltage converter, as shown in the OUTPUTS section. All output cells are always on, with the data determining whether a given cell’s current is routed from IOUT or IOUT. This provides nearly constant power dissipation independent of data and clock rate. It also reduces noise transients on power and ground lines. SPT5510 4 9/27/00 Wideband decoupling is required for optimum settling performance. This may require several capacitors in parallel, and series resistors when appropriate, to reduce resonance effects. Some applications may need only a single capacitor; however, decoupling influences both long- and shortterm settling, so caution is urged. Your application may require some research to determine the optimum power supply decoupling network. OUTPUTS The output is comprised of current sinks, R-2R ladder, and associated parasitics. See figure 3 for an equivalent output circuit. The DAC’s full-scale output current when using the internal reference amplifier is determined by the voltage at pin AMPINB and the RSET resistance. It can be found (to within an LSB) by using the following formula: DIGITAL INPUTS AND TIMING IOUT FS = (AMPINB/RSET) x 16 Each digital input is buffered, decoded, and then latched into D flip-flops which drive the output switches. Masterslave flip-flops are not used; thus, there is only a 1/2 clock period delay (max) from data change to output change. In this architecture, clock and data edge speeds (i.e., rise/fall times) may affect data feedthrough. Using a data edge of approximately 0.8 ns will cause data feedthrough of about 10 pV-s, while a 5 ns data edge will reduce the feedthrough to about 4 pV-s. Data lines may include series resistors or RC filters for edge control if desired. The inputs determine whether the current from each sink comes from IOUT or IOUT as follows: Figure 2 – Timing Diagram tH IOUT 0 (zero scale) No current IOUT All current 32768 (mid-scale) IOUT = IOUT IOUT = IOUT 65535 (full-scale) All current No current Differential outputs facilitate maximum noise rejection and signal swing. The DAC is trimmed using a current to voltage (I-V) converter which provides a virtual ground at the outputs and includes sense lines to mitigate the impact of bus drops. Operating into a load other than a virtual ground will introduce a slight bow at the output. This bow is related to the current sinks’ finite output impedance and ladder impedance. The clock signal controls when the data is latched into the flip-flops. When the CLK is high, the DAC is in track mode. A negative going CLK latches the data. If CLK is held low, the DAC is in hold mode. See figure 2. tS Code (D15 is MSB) An example circuit using an I-V converter is shown in figure 4. Note that resistor and op-amp self heating over the DAC’s full-scale range will introduce additional temperature dependence. The op-amp and feedback resistor must both have very low tempcos if the DAC’s intrinsic gain drift is to be maintained. A sense line helps reduce wire effects – both IR loss and temperature drift. tD CLK DATA IOUT Figure 4 – I-V Converter BNC "IOUT” IOUT tST tH = hold time tD = time to output valid tS = setup time tST = settling time 250 GND OGND IOUT – OGND + OGND IOUT + Figure 3 – Equivalent Output Circuit IOUT or IOUT 1.1k 10 pF OGND – GND AVEE 250 BNC "IOUT" SPT5510 5 9/27/00 The feedback resistor should be matched to RSET to reduce gain drift. Also, the op amp’s ground reference should be the same as RSET’s to reduce gain and offset errors. A composite amplifier may be required to obtain optimal dc performance. A differential circuit may be used; a common heat sink covering both sides (op amps and resistors) will help reduce temperature effects. BANDGAP VOLTAGE REFERENCE The on-chip bandgap voltage reference is designed to bias the non-inverting input of the reference amplifier (AMPINB) through a resistor equal to RSET to help compensate the reference amplifier (see the following section). If the bandgap voltage is required by another DAC, or elsewhere in the system, it must be buffered with a precision op amp configured as a high impedance (e.g., unity gain follower) buffer. A resistor, or RC filter, plus a ferrite bead will help isolate the output from the reference amplifier’s compensation and high-frequency charge pulses produced during operation. The output should always be very carefully checked for oscillations using a sensitive, wideband oscilloscope and spectrum analyzer. Achieving good settling performance requires careful board layout with multiple decoupling circuits and very clean power and ground routing. It is important that digital switching currents do not flow across analog input (REFIN) and output signals. Terminations must be broadband and near the device. Measuring settling performance is quite challenging and requires several test systems to ensure settling errors from the instruments are not included. REFERENCE AMPLIFIER Dynamic performance characteristics (e.g., settling, rise and fall times, etc.) were measured with the outputs terminated to ground through 50 Ω resistors. SFDR was determined using a transformer to convert the output from differential to single-ended as shown in figure 5. The SPT5510 is designed primarily for step and settle or narrowband RF applications. The second harmonic generally dominates wideband SFDR measurements, although close-in spurs are very small. The reference amplifier is a highly temperature-stable driver to bias the precision current sinks. The reference amplifier should only be used to drive REFIN. Additional loads will change the amplifier’s compensation, which can lead to instability and other settling issues. There are two reference amplifier outputs: AMP OUT and AMPCC. AMPOUT has a 20 ohm series resistor between the output of the reference amplifier and the AMPOUT pin; AMPCC has a 10 ohm resistor. These parallel outputs aide compensation and decoupling. The open-loop output impedance is approximately 1200 ohms. Figure 5 – Transformer Output Circuit IOUT Reference amplifier compensation is key to achieving high performance. Without proper compensation, oscillations that affect accuracy and settling time will occur. Figure 6 shows a typical reference amplifier compensation circuit. Note that several small value capacitors are used from REFIN to ground. This is to provide suitably low impedance 25 25 IOUT Figure 6 – Reference Amplifier Circuit SPT5510 DAC RSET 1 kΩ 17 18 1 kΩ + Ref Amp – 20 Ω 20 10 Ω 19 21 AMPOUT 0.01 µF 50Ω AMPCC 10 pF 16 REFIN C1 C2 C3 BGOUT 47 pF each 15 AMPB 0.01 µF VEE 20 pF All components are ceramic chip-type. SPT5510 6 9/27/00 around 300 MHz, the amplifier’s phase crossover point. The unity-gain bandwidth is roughly 700 MHz. Larger value capacitors exhibit lower self-resonance frequency and thus may not adequately compensate the reference amplifier. Large capacitors may also introduce low frequency tails which increase settling time. The DAC itself exhibits very broadband switching spikes (charge kickback) at the RSET node, which can contribute to amplifier instability if not suppressed. Note that the AMPINB input must not be directly bypassed, as this will short all feedback to ground, leading to severe oscillation. LONG-TERM STABILITY VERSUS TEMPERATURE As with all high-speed, high-resolution digital-to-analog converters, the initial accuracy of the device will degrade with both time and temperature. The graph shown in figure 7 can be used to determine the expected change in linearity performance over time when the device is operated at various ambient temperatures. This graph shows how long it will take for the SPT5510 linearity to change by 8 ppm (or 1/2 LSB) at any operating temperature. The top curve shown represents integral nonlinearity (ILE) changes; the bottom curve shows differential nonlinearity (DLE) changes. Compensation must be optimized for each application. As with any high-speed, high-resolution design, attention must be paid to grounding, decoupling, and parasitic elements that may cause instability. It may be wise to use a guard ring, and/or clear the board ground, around the reference amplifier’s inputs. All traces must be short, and capacitors with high self-resonance must be used. (Hours) Compensation is perhaps the most challenging aspect of setting up the SPT5510. By slowly switching a full-scale data input (generating a low-frequency square wave), with appropriate clock timing, the DAC’s output can be observed using a suitable oscilloscope and spectrum analyzer to observe and suppress any oscillations caused by board and decoupling parasitics. Consult Fairchild Applications for further assistance if required. 1 year 106 105 100 years 104 1000 years 107 Figure 7 – Linearity Performance over Time 102 1 month 103 ILE DLE 0 20 40 60 80 100 120 Temperature (°C) Expected time required to produce an 8 ppm (1/2 LSB) linearity (ILE or DLE) shift as a function of temperature. PACKAGE OUTLINE 44-Lead MQFP A B INCHES MAX MILLIMETERS MIN MAX SYMBOL MIN A 0.5098 0.5295 12.95 13.45 B 0.3917 0.3957 9.95 10.05 C 0.3917 0.3957 9.95 10.05 D 0.5098 0.5295 12.95 13.45 E 0.0311 0.0319 0.79 0.81 F 0.0118 0.0177 0.30 0.45 G 0.0768 0.0827 1.95 2.10 H 0.0039 0.0098 0.10 0.25 I 0.0287 0.0406 0.73 1.03 Pin 1 Index C E D F J K G 0.0630 REF 0° 7° 1.60 REF 0° 7° K I H J SPT5510 7 9/27/00 PIN FUNCTIONS PIN ASSIGNMENTS AVEE 34 38 OGND 35 39 IOUT 36 AVEE OGND 37 AVEE 41 OGND 40 IOUT OGND 42 AVEE 43 DGND 44 (MSB) D15 1 33 DGND D14 2 32 D0 (LSB) D13 3 31 D1 D12 4 30 D2 D11 5 29 D3 D10 6 28 D4 D9 7 27 D5 D8 8 26 D6 CLK 9 25 D7 DGND 10 24 DGND AVEE 11 23 AVEE SPT5510 44-Pin MQFP 12 13 14 15 16 17 18 19 20 21 22 REFGND AVEE AVEE AMPB BGOUT RSET AMPINB AMPCC AMPOUT REFIN REFGND NAME FUNCTION D15–D0 Digital Input Bits – all inputs high sends all current to IOUT, none to IOUT CLK Clock – latches D flip-flops IOUT Analog Current Output IOUT Complementary Analog Current Output BGOUT Bandgap Voltage Reference AMPINB Ref Amp’s Inverting Input RSET Ref Amp’s Non-Inverting Input – connection for reference-current-setting resistor, nominally 1kΩ to ground AMPOUT Bias Voltage for Output Current Switches – drives REFIN (on-chip 20 Ω resistor for compensation) REFIN Bias Voltage Node for Output Current Switches – driven by AMPOUT AMPB Used to Decouple Ref Amp’s Circuits to AVEE AMPCC AMPOUT plus on-chip 10 Ω series resistor for compensation AVEE Negative Supply – –5.2 V DGND Digital Ground Return OGND Output Ground Return REFGND Reference Amplifier Ground Return ORDERING INFORMATION PART NUMBER SPT5510SIM TEMPERATURE RANGE PACKAGE –40 to +85 °C 44L MQFP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT5510 8 9/27/00