LT1468 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT®1468 is a precision high speed operational amplifier with 16-bit accuracy and 900ns settling to 150µV for 10V signals. This unique blend of precision and AC performance makes the LT1468 the optimum choice for high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. 90MHz Gain Bandwidth, f = 100kHz 22V/µs Slew Rate Settling Time: 900ns (AV = –1, 150µV, 10V Step) Low Distortion, – 96.5dB for 100kHz, 10VP-P Maximum Input Offset Voltage: 75µV Maximum Input Offset Voltage Drift: 2µV/°C Maximum (–) Input Bias Current: 10nA Minimum DC Gain: 1000V/mV Minimum Output Swing into 2k: ±12.8V Unity Gain Stable Input Noise Voltage: 5nV/√Hz Input Noise Current: 0.6pA/√Hz Total Input Noise Optimized for 1k < RS < 20k Specified at ±5V and ±15V The 90MHz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC accuracy allow full 16-bit AC and DC performance. The 22V/µs slew rate of the LT1468 improves large-signal performance in applications such as active filters and instrumentation amplifiers compared to other precision op amps. U APPLICATIONS ■ ■ ■ ■ ■ 16-Bit DAC Current-to-Voltage Converter Precision Instrumentation ADC Buffer Low Distortion Active Filters High Accuracy Data Acquisition Systems Photodiode Amplifiers The LT1468 is manufactured on Linear Technology’s complementary bipolar process. , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATIO Total Harmonic Distortion vs Frequency – 80 20pF DAC INPUTS 16 6k – LTC 1597 2k LT1468 ® + VOUT 50pF OPTIONAL NOISE FILTER OFFSET: VOS + IB (6kΩ) < 1LSB SETTLING TIME TO 150µV = 1.7µs SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE 1468 TA01 TOTAL HARMONIC DISTORTION (dB) 16-Bit DAC I-to-V Converter – 90 VS = ±15V AV = 2 RL = 2k VOUT = 10VP-P –100 –110 –120 –130 100 1k 10k FREQUENCY (Hz) 100k 1468 TA02 1 LT1468 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Total Supply Voltage (V+ to V –) ............................... 36V Maximum Input Current (Note 2) ......................... 10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range ................ – 40°C to 85°C Specified Temperature Range (Note 4) ... – 40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW NULL 1 8 DNC* – IN 2 7 V+ + IN 3 6 VOUT V– 4 5 NULL N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO *DO NOT CONNECT LT1468CN8 LT1468CS8 LT1468IN8 LT1468IS8 S8 PART MARKING TJMAX = 150°C, θJA = 130°C/W (N8) TJMAX = 150°C, θJA = 190°C/W (S8) 1468 1468I Consult factory for Military Grade parts. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VOS Input Offset Voltage IOS TA = 25°C, VCM = 0V unless otherwise noted. CONDITIONS VSUPPLY MIN TYP MAX UNITS ±15V ±5V 30 50 75 175 µV µV Input Offset Current ±5V to ±15V 13 50 nA IB – Inverting Input Bias Current ±5V to ±15V 3 ±10 nA IB + Noninverting Input Bias Current ±40 ±5V to ±15V – 10 Input Noise Voltage 0.1Hz to 10Hz ±5V to ±15V 0.3 en Input Noise Voltage f = 10kHz ±5V to ±15V 5 nV/√Hz in Input Noise Current f = 10kHz ±5V to ±15V RIN Input Resistance VCM = ±12.5V Differential CIN Input Capacitance ±15V Input Voltage Range + ±15V ±5V Input Voltage Range – ±15V ±5V CMRR Common Mode Rejection Ratio VCM = ±12.5V VCM = ±2.5V PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V AVOL Large-Signal Voltage Gain VOUT ±15V ±15V nA µVP-P 0.6 pA/√Hz 100 50 240 150 MΩ kΩ 4 pF 12.5 2.5 13.5 3.5 V V –14.3 – 4.3 –12.5 –2.5 V V ±15V ±5V 96 96 100 112 dB VOUT = ±12.5V, RL = 10k VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V 1000 500 1000 500 9000 5000 6000 3000 V/mV V/mV V/mV V/mV Output Swing RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV ±15V ±15V ±5V ±5V ±13.0 ±12.8 ±3.0 ±2.8 ±13.6 ±13.5 ±3.6 ±3.5 V V V V IOUT Output Current VOUT = ±12.5V VOUT = ±2.5V ±15V ±5V ±15 ±15 ±22 ±22 mA mA ISC Short-Circuit Current VOUT = 0V, VIN = ±0.2V ±15V ±25 ±40 mA 2 110 112 dB dB LT1468 ELECTRICAL CHARACTERISTICS TA = 25°C, VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VSUPPLY MIN TYP SR Slew Rate AV = –1, RL = 2k (Note 5) ±15V ±5V 15 11 22 17 V/µs V/µs Full-Power Bandwidth 10V Peak, (Note 6) 3V Peak, (Note 6) ±15V ±5V 350 900 kHz kHz GBW Gain Bandwidth f = 100kHz, RL = 2k ±15V ±5V 90 88 MHz MHz THD Total Harmonic Distortion AV = 2, VO = 10VP-P, f = 1kHz AV = 2, VO = 10VP-P, f = 100kHz ±15V ±15V 0.00007 0.0015 % % tr, tf Rise Time, Fall Time AV = 1, 10% to 90%, 0.1V ±15V ±5V 11 12 ns ns Overshoot AV = 1, 0.1V ±15V ±5V 30 35 % % Propagation Delay AV = 1, 50% VIN to 50% VOUT, 0.1V ±15V ±5V 9 10 ns ns ts Settling Time 10V Step, 0.01%, AV = –1 10V Step, 150µV, AV = –1 5V Step, 0.01%, AV = –1 ±15V ±15V ±5V 760 900 770 ns ns ns RO Output Resistance AV = 1, f = 100kHz ±15V 0.02 IS Supply Current ±15V ±5V 3.9 3.6 5.2 5.0 mA mA TYP MAX UNITS 150 250 µV µV 2.0 µV/°C 60 55 MAX UNITS Ω 0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted. SYMBOL PARAMETER VOS Input Offset Voltage IB – VSUPPLY MIN ±15V ±5V ● ● ±5V to ±15V ● Input Offset Current ±5V to ±15V ● Input Offset Current Drift ±5V to ±15V Inverting Input Bias Current ±5V to ±15V Input VOS Drift IOS CONDITIONS (Note 7) 0.7 65 60 ±15 ● nA pA/°C nA Negative Input Current Drift ±5V to ±15V IB + Noninverting Input Bias Current ±5V to ±15V ● CMRR Common Mode Rejection Ratio VCM = ±12.5V VCM = ±2.5V ±15V ±5V ● ● 94 94 dB dB PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 98 dB AVOL Large-Signal Voltage Gain VOUT = ±12.5V, RL = 10k VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V ● ● ● ● 500 250 500 250 V/mV V/mV V/mV V/mV VOUT Output Swing RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV ±15V ±15V ±5V ±5V ● ● ● ● ±12.9 ±12.7 ±2.9 ±2.7 V V V V IOUT Output Current VOUT = ±12.5V VOUT = ±2.5V ±15V ±5V ● ● ±12.5 ±12.5 mA mA ISC Short-Circuit Current VOUT = 0V, VIN = ±0.2V ±15V ● ±17 mA SR Slew Rate AV = –1, RL = 2k (Note 5) ±15V ±5V ● ● 13 9 V/µs V/µs 40 pA/°C ±50 nA 3 LT1468 ELECTRICAL CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS GBW Gain Bandwidth f = 100kHz, RL = 2k IS Supply Current VSUPPLY MIN ±15V ±5V ● ● ±15V ±5V ● ● TYP MAX 55 50 UNITS MHz MHz 6.5 6.3 mA mA MAX UNITS 230 330 µV µV 2.5 µV/°C – 40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted (Note 4). SYMBOL PARAMETER VOS Input Offset Voltage IB – VSUPPLY MIN ±15V ±5V ● ● ±5V to ±15V ● Input Offset Current ±5V to ±15V ● Input Offset Current Drift ±5V to ±15V Inverting Input Bias Current ±5V to ±15V Input VOS Drift IOS CONDITIONS (Note 7) TYP 0.7 80 120 ±30 ● nA pA/°C nA Negative Input Current Drift ±5V to ±15V IB + Noninverting Input Bias Current ±5V to ±15V ● CMRR Common Mode Rejection Ratio VCM = ±12.5V VCM = ±2.5V ±15V ±5V ● ● 92 92 dB dB PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 96 dB AVOL Large-Signal Voltage Gain VOUT = ±12V, RL = 10k VOUT = ±10V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V ● ● ● ● 300 150 300 150 V/mV V/mV V/mV V/mV VOUT Output Swing RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV RL = 10k, VIN = ±1mV RL = 2k, VIN = ±1mV ±15V ±15V ±5V ±5V ● ● ● ● ±12.8 ±12.6 ±2.8 ±2.6 IOUT Output Current VOUT = ±12.5V VOUT = ±2.5V ±15V ±5V ● ● ±7 ±7 mA mA ISC Short-Circuit Current VOUT = 0V, VIN = ±0.2V ±15V ● ±12 mA SR Slew Rate AV = –1, RL = 2k (Note 5) ±15V ±5V ● ● 9 6 V/µs V/µs GBW Gain Bandwidth f = 100kHz, RL = 2k ±15V ±5V ● ● 45 40 MHz MHz IS Supply Current ±15V ±5V ● ● The ● denotes specifications that apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes and two 100Ω series resistors. If the differential input voltage exceeds 0.7V, the input current should be limited to 10mA. Input voltages outside the supplies will be clamped by ESD protection devices and input currents should also be limited to 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. 4 80 pA/°C ±60 nA V V V V 7.0 6.8 mA mA Note 4: The LT1468C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at – 40°C and at 85°C. The LT1468I is guaranteed to meet the extended temperature limits. Note 5: Slew rate is measured between ±8V on the output with ±12V input for ±15V supplies and ±2V on the output with ±3V input for ±5V supplies. Note 6: Full power bandwidth is calculated from the slew rate measurement: FPBW = SR/2πVP Note 7: This parameter is not 100% tested. LT1468 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage and Temperature Input Common Mode Range vs Supply Voltage V+ 7 80 TA = 25°C ∆VOS < 100µV – 0.5 5 4 25°C 3 – 55°C INPUT BIAS CURRENT (nA) 125°C 60 –1.0 COMMON MODE RANGE (V) SUPPLY CURRENT (mA) 6 Input Bias Current vs Input Common Mode Voltage –1.5 – 2.0 2.0 1.5 1.0 2 5 10 15 SUPPLY VOLTAGE (± V) V– 20 3 0 9 12 6 SUPPLY VOLTAGE (± V) 1468 G01 IB– –10 IB+ – 20 – 30 – 40 – 50 –25 in 100 100 125 1 en 10 0.1 1 10 100 1k FREQUENCY (Hz) 10k 140 5 S0-8 ±5V –15 N8 ±15V – 20 – 25 S0-8 ±15V –30 1468 G06 Open-Loop Gain vs Temperature 160 VS = ±15V VS = ±15V VS = ±5V 130 125 120 115 20 40 60 80 100 120 TIME AFTER POWER UP (s) 140 1468 G07 140 130 VS = ±5V 120 110 100 110 – 40 RL = 2k 150 –35 0 TIME (1s/DIV) TA = 25°C 135 OPEN-LOOP GAIN (dB) OFFSET VOLTAGE DRIFT (µV) N8 ±5V –10 0.01 100k Open-Loop Gain vs Resistive Load Warm-Up Drift vs Time –5 VS = ±15V 1468 G05 1468 G04 0 15 0.1Hz to 10Hz Voltage Noise 10 VS = ±15V TA = 25°C AV = 101 RS = 100k FOR in 1 50 25 75 0 TEMPERATURE (°C) –10 –5 5 10 0 INPUT COMMON MODE VOLTAGE (V) VOLTAGE NOISE (100nV/DIV) INPUT VOLTAGE NOISE (nV/√Hz) INPUT BIAS CURRENT (nA) 10 0 – 40 1468 G03 INPUT CURRENT NOISE (pA/√Hz) 20 IB+ –20 Input Noise Spectral Density 1000 VS = ±15V IB– 0 1468 G02 Input Bias Current vs Temperature 30 20 – 80 –15 18 15 OPEN-LOOP GAIN (dB) 0 40 – 60 0.5 1 VS = ±15V TA = 25°C 10 100 1k LOAD RESISTANCE (Ω) 10k 1468 G08 90 – 50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1468 G09 5 LT1468 U W TYPICAL PERFOR A CE CHARACTERISTICS –1 –2 –3 –4 4 3 2 RL = 2k 1 RL = 10k TA = 25°C V– 0 85°C 25°C – 40°C –1.5 –2.0 –2.5 2.5 40°C 2.0 1.5 85°C 1.0 5 10 15 SUPPLY VOLTAGE (± V) 60 VS = ±15V –1.0 RL = 10k OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) V + – 0.5 RL = 2k Output Short-Circuit Current vs Temperature 25°C V – 0.5 – 20 –15 –10 – 5 0 10 5 OUTPUT CURRENT (mA) 20 15 5 AV = –1 4 AV = 1 2 0 –2 –4 AV = 1 –8 0 200 AV = –1 1 –1 –2 AV = 1 AV = –1 400 600 700 500 SETTLING TIME (ns) 800 34 GAIN BANDWIDTH 32 84 20 1468 G17 GAIN BANDWIDTH (MHz) GAIN BANDWIDTH (MHz) 36 10 5 15 SUPPLY VOLTAGE (±V) 2 –2 –4 200 0 600 800 400 SETTLING TIME (ns) PHASE MARGIN Output Impedance vs Frequency VS = ±15V 42 40 VS = ±5V 38 36 94 92 GAIN BANDWIDTH 34 VS = 15V 32 90 88 30 86 28 84 –55 –25 100 44 98 96 1000 1468 G15 30 VS = 5V VS = ±15V TA = 25°C 10 PHASE MARGIN (DEG) 38 PHASE MARGIN (DEG) 40 86 VS = ±15V AV = –1 RF = RG = 2k CF = 8pF 0 –10 46 100 PHASE MARGIN 88 6 102 125 –6 104 42 90 100 4 Gain Bandwidth and Phase Margin vs Temperature 92 50 25 0 75 TEMPERATURE (°C) 1468 G14 44 0 15 –8 –5 300 1000 98 82 20 6 0 Gain Bandwidth and Phase Margin vs Supply Voltage 94 25 8 AV = –1 AV = 1 –4 600 800 400 SETTLING TIME (ns) TA = 25°C AV = –1 RF = RG = 5.1k CF = 5pF RL = 2k 30 10 1468 G13 96 35 Settling Time to 150µV vs Output Step 2 –3 –6 –10 VS = ±5V RL = 1k 3 4 OUTPUT STEP (V) OUTPUT STEP (V) 6 SINK 40 1468 G12 OUTPUT STEP (V) VS = ±15V RL = 1k SOURCE 45 Settling Time to 0.01% vs Output Step, VS = ±5V Settling Time to 0.01% vs Output Step, VS = ±15V 8 50 1468 G11 1468 G10 10 VS = ±15V VIN = ± 0.2V 55 10 – 50 –25 20 OUTPUT IMPEDANCE (Ω) V+ Output Voltage Swing vs Load Current OUTPUT SHORT-CIRCUIT CURRENT (mA) Output Voltage Swing vs Supply Voltage AV = 100 1 AV = 10 0.1 AV = 1 0.01 28 50 25 0 75 TEMPERATURE (°C) 100 26 125 1468 G18 0.001 10k 100k 1M 10M FREQUENCY (Hz) 100M 1468 G19 LT1468 U W TYPICAL PERFOR A CE CHARACTERISTICS 60 80 160 PHASE ±15V 40 40 ±5V 20 30 GAIN 20 10 0 –10 10k 100k 0 ±15V TA = 25°C AV = – 1 RF = RG = 5.1k CF = 5pF RL = 2k PHASE (DEG) GAIN (dB) 60 –20 ±5V – 40 1M 10M FREQUENCY (Hz) 140 120 VS = ±15V TA = 25°C COMMON MODE REJECTION RATIO (dB) 100 POWER SUPPLY REJECTION RATIO (dB) 70 50 +PSRR 120 100 – PSRR 80 60 40 20 – 60 100M 0 100 1k 10k 1M 100k FREQUENCY (Hz) 10M 1468 G16 TA = 25°C AV = 1 RL = 2k –1 –4 TA = 25°C AV = –1 RL = 2k CF = 5pF –5 100k 6 4 1M 10M FREQUENCY (Hz) TA = 25°C 28 AV = –1 RL = 2k 300pF 2 0 –2 50pF –4 –6 100k 1M 10M FREQUENCY (Hz) 100M 1468 G25 1M 10M FREQUENCY (Hz) Slew Rate vs Temperature 45 40 – SR VS = ±15V AV = – 1 RL = 2k 35 24 + SR 22 20 – SR 30 25 15 16 10 0 10 5 15 SUPPLY VOLTAGE (±V) 20 1468 G26 + SR 20 18 14 100M 1468 G24 26 100pF 10pF –6 100k 100M Slew Rate vs Supply Voltage 200pF 20pF –2 SLEW RATE (V/µs) GAIN (dB) 8 4 2 –4 30 SLEW RATE (V/µs) 10 100pF 50pF 6 1468 G23 Frequency Response vs Capacitive Load, AV = –1 100M 0 1468 G22 VS = ±15V TA = 25°C AV = – 1 RF = RG = 5.1k CF = 5pF NO RL 10M VS = ±15V TA = 25°C AV = 1 NO RL 8 –1 –4 100M 10 0 –3 12 10k 100k 1M FREQUENCY (Hz) Frequency Response vs Capacitive Load, AV = 1 RF = RG = 2k ±5V ±15V RF = RG = 5.1k ±5V ±15V 1 –3 1M 10M FREQUENCY (Hz) 1k 1468 G21 14 –2 14 20 12 –2 –5 100k 40 0 100 100M GAIN (dB) GAIN (dB) GAIN (dB) ±15V 0 60 5 2 ±5V 1 80 4 3 2 100 Frequency Response vs Supply Voltage, AV = – 1 5 3 VS = ±15V TA = 25°C 1468 G20 Frequency Response vs Supply Voltage, AV = 1 4 Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Gain and Phase vs Frequency 5 – 50 – 25 0 50 75 25 TEMPERATURE (°C) 100 125 1468 G27 7 LT1468 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Harmonic Distortion + Noise vs Frequency – 60 ± 5V AV = 10 0.001 AV = 1 MEASUREMENT LIMIT 0.0001 100 1k FREQUENCY (Hz) 10k 20k ±15V – 70 – 80 – 90 –100 20 30 TA = 25°C AV = 10 RL = 600Ω f = 10kHz NOISE BW = 80kHz –110 0.01 25 AV = 1 20 AV = –1 15 10 5 VS = ±15V RL = 2k 0 0.1 1 OUTPUT SIGNAL (VRMS) 10 1468 G28 Small-Signal Transient, AV = 1 OUTPUT VOLTAGE SWING (VP-P) – 50 VS = ±15V TA = 25°C RL = 600Ω VO = 20VP-P NOISE BW = 80kHz THD + NOISE (dB) THD + NOISE (%) 0.010 Undistorted Output Swing vs Frequency, ±15V Total Harmonic Distortion + Noise vs Amplitude 1468 G30 Undistorted Output Swing vs Frequency, ±5V Small-Signal Transient, AV = – 1 VS = ± 5V RL = 2k VS = ±15V 1468 G32 OUTPUT VOLTAGE SWING (VP-P) 9 1468 G31 1000 1468 G29 10 VS = ±15V 10 100 FREQUENCY (kHz) 1 8 AV = 1 7 6 AV = – 1 5 4 3 2 1 0 1 10 100 FREQUENCY (kHz) 1000 1468 G33 Large-Signal Transient, AV = 1 Total Noise vs Unmatched Source Resistance Large-Signal Transient, AV = – 1 VS = ±15V 1468 G34 VS = ±15V 1468 G32 TOTAL NOISE VOLTAGE (nV/√Hz) 100 VS = ±15V TA = 25°C f = 10kHz TOTAL NOISE 10 RESISTOR NOISE ONLY 1 RS + – 0.1 10 100 1k 10k SOURCE RESISTANCE, RS (Ω) 100k 1468 G36 8 LT1468 U U W U APPLICATIONS INFORMATION The LT1468 may be inserted directly into many operational amplifier applications improving both DC and AC performance, provided that the nulling circuitry is removed. The suggested nulling circuit for the LT1468 is shown below. CF > (RG)(CIN/RF) Offset Nulling V+ 3 + LT1468 2 76 0.1µF 2.2µF 0.1µF 2.2µF 4 – 5 1 100k V– The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause peaking or even oscillations. For feedback resistors greater than 2k, a feedback capacitor of the value: 1468 AI01 Layout and Passive Components The LT1468 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example fast settling time) use a ground plane, short lead lengths, and RF-quality bypass capacitors (0.01µF to 0.1µF) in parallel with low ESR bypass capacitors (1µF to 10µF tantalum). For best DC performance, use “star” grounding techniques, equalize input trace lengths and minimize leakage (i.e., 1.5GΩ of leakage between an input and a 15V supply will generate 10nA—equal to the maximum IB– specification.) Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs. For inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below.) Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short, and the two input leads should be as close together as possible and maintained at the same temperature. Make no connection to Pin 8. This pin is used for factory trim of the inverting input current. should be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, CF should be greater than or equal to CIN. An example would be a DAC I-to-V converter as shown on the front page of this data sheet where the DAC can have many tens of pF of output capacitance. Another example would be a gain of –1 with 5k resistors; a 5pF to 10pF capacitor should be added across the feedback resistor. The frequency response in a gain of –1 is shown in the Typical Performance curves with 2k and 5.1k resistors with a 5pF feedback capacitor. Nulling Input Capacitance RF CF RG – CIN VIN LT1468 VOUT + 1468 AI02 Input Considerations Each input of the LT1468 is protected with a 100Ω series resistor and back-to-back diodes across the bases of the input devices. If the inputs can be pulled apart, the input current should be limited to less than 10mA with an external series resistor. Each input also has two ESD clamp diodes—one to each supply. If an input is driven above the supply, limit the current with an external resistor to less than 10mA. The LT1468 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as I-to-V converters. The noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. As the input offset 9 LT1468 U W U U APPLICATIONS INFORMATION Driving Capacitive Loads current can be greater than either input current, the use of balanced source resistance is NOT recommended as it actually degrades DC accuracy and also increases noise. The input bias currents vary with common mode voltage as shown in the Typical Performance Characteristics. The cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. The LT1468 inputs can be driven to the negative supply and to within 0.5V of the positive supply without phase reversal. As the input moves closer than 0.5V to the positive supply, the output reverses phase. Input Stage Protection R1 100Ω + IN Q1 Q2 R2 100Ω – IN 1468 AI03 Total Input Noise The curve of Total Noise vs Unmatched Source Resistance in the Typical Performance Characteristics shows that with source resistance below 1k, the voltage noise of the amplifier dominates. In the 1k to 20k region the increase in noise is due to the source resistance. Above 20k the input current noise component is larger than the resistor noise. Capacitive Loading The LT1468 drives capacitive loads of up to 100pF in unity gain and 300pF in a gain of –1. When there is a need to drive a larger capacitive load, a small series resistor should be inserted between the output and the load. In addition, a capacitor should be added between the output and the inverting input as shown in Driving Capacitive Loads. Settling Time The LT1468 is a single stage amplifier with an optimal thermal layout that leads to outstanding settling performance. Measuring settling, even at the 12-bit level is very challenging, and at the 16-bit level requires a great deal of subtlety and expertise. Fortunately, there are two 10 RF CF RG – RO LT1468 VIN + RO ≥ (1 + RF /RG)/(2πCL5MHz) RF ≥ 10RO CF = (2RO /RF)CL VOUT CL 1468 AI04 excellent Linear Technology reference sources for settling measurements, Application Notes 47 and 74. Appendix B of AN47 is a vital primer on 12-bit settling measurements, and AN74 extends the state of the art while concentrating on settling time with a 16-bit current output DAC input. The 150µV settling curve in the Typical Performance Characteristics is measured using the Differential Amplifier method of AN74 followed by a clamped, nonsaturating gain of 100. The total gain of 500 allows a resolution of 100µV/DIV with an oscilloscope setting of 0.05V/DIV The settling of the DAC I-to-V converter on the front page was measured using the exact methods of AN74. The optimum nulling of the DAC output capacitance requires 20pF across the 6k feedback resistor. The theoretical limit for 16-bit settling is 11.1 times this RC time constant or 1.33µs. The actual settling time is 1.7µs at the output of the LT1468. The LT1468 is the fastest Linear Technology amplifier in this application. The optional noise filter adds a slight delay of 100ns, but reduces the noise bandwidth to 1.6MHz which increases the output resolution for 16-bit accuracy. Distortion The LT1468 has outstanding distortion performance as shown in the Typical Performance curves of Total Harmonic Distortion + Noise vs Frequency and Amplitude. The high open-loop gain and inherently balanced architecture reduce errors to yield 16-bit accuracy to frequencies as high as 100kHz. An example of this performance is the Typical Application titled 100kHz Low Distortion Bandpass Filter. This circuit is useful for cleaning up the output of a high performance signal generator such as the B & K type 1051 or HP3326A. LT1468 U U W U APPLICATIONS INFORMATION Another key application for LT1468 is buffering the input to a 16-bit A/D converter. In a gain of 1 or 2 this straightforward circuit provides uncorrupted AC and DC levels to the converter, while buffering the A/D input sample-and- hold circuit from high source impedance which can reduce the maximum sampling rate. The front page graph shows better than 16-bit distortion for a gain of 2 with a 10VP-P output. W W SI PLIFIED SCHEMATIC V+ I1 I5 I2 Q10 Q8 + IN Q1 Q2 – IN Q5 OUT Q9 Q6 Q7 Q3 I3 Q4 Q11 C BIAS I4 I6 V– 1468 SS U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1510) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 0.400* (10.160) MAX 8 7 6 8 0.255 ± 0.015* (6.477 ± 0.381) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 2 3 5 0.150 – 0.157** (3.810 – 3.988) 4 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) 6 0.228 – 0.244 (5.791 – 6.197) 1 0.300 – 0.325 (7.620 – 8.255) 7 5 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP SO8 0996 11 LT1468 U TYPICAL APPLICATIONS Instrumentation Amplifier R5 1.1k 16-Bit ADC Buffer 10pF R4 50k R2 5k C2 2pF 2k C1 10pF R1 50k 2k – 16 BITS 200Ω LT1468 R3 5k – VIN 1000pF – LT1468 + – + LTC1605 33.2k LT1468 VOUT + VIN CAP 1468 TA04 2.2µF 1468 TA03 + GAIN = [R4/R3][1 + (1/2)(R2/R1 + R3/R4) + (R2 + R3)/R5] = 102 TRIM R5 FOR GAIN TRIM R1 FOR COMMON MODE REJECTION BW = 480kHz 100kHz Low Distortion Bandpass Filter 1000pF 22.1k 1000pF 11k – VIN 121Ω LT1468 + VOUT RL 100kHz Distortion SIGNAL LEVEL 1VRMS 2VRMS 3.5VRMS 1VRMS 2VRMS 3.5VRMS RL 1M 1M 1M 2k 2k 2k 2ND HARMONIC – 106dB – 105dB – 106dB – 103dB – 99dB – 96.5dB 3RD HARMONIC – 103dB – 105dB – 104dB – 103dB – 103dB – 102dB 1468 TA05 fO = 100kHz Q=7 AV = –1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1167 Precision Instrumentation Amplifier Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity LTC1595/LTC1596 16-Bit Serial Multiplying IOUT DACs ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade LTC1597 16-Bit Parallel Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors LTC1604 16-Bit, 333ksps Sampling ADC ±2.5V Input, SINAD = 90dB, THD = –100dB LTC1605 Single 5V, 16-Bit, 100ksps Sampling ADC Low Power, ±10V Inputs, Parallel/Byte Interface 12 Linear Technology Corporation 1468f LT/TP 1098 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998