NSC ADC10464CIWM 10-bit 600 ns a/d converter with input multiplexer and sample/hold Datasheet

ADC10461/ADC10462/ADC10464
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Features
Using an innovative, patented multistep* conversion technique, the 10-bit ADC10461, ADC10462, and ADC10464
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
These converters perform 10-bit conversion in two lowerresolution “flashes”, yielding a fast A/D without the cost,
power consumption, and other problems associated with
true flash approaches. Dynamic performance (THD, S/N) is
guaranteed. The ADC10461 is pin-compatible with the
ADC1061 but is much faster, providing a convenient upgrade path for the ADC1061.
n
n
n
n
n
The analog input voltage is sampled and held by an internal
sampling circuit. Input signals at frequencies from dc to over
200 kHz can, therefore, be digitized accurately without the
need for an external sample-and-hold circuit.
The ADC10462 and ADC10464 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10461,
ADC10462, and ADC10464 have been designed to appear
as a memory location or I/O port without the need for external interface logic.
Built-in sample-and-hold
Single +5V supply
1, 2, or 4-input multiplexer options
No external clock required
Speed adjust pin for faster conversions (ADC10462 and
ADC10464)
Key Specifications
n
n
n
n
n
Conversion Time
Sampling Rate
Low Power Consumption
Total Harmonic Distortion (50 kHz)
No Missing Codes
600 ns (typical)
800 kHz
235 mW (max)
−60 dB (max)
Over Temperature
Applications
n
n
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Digital signal processor front ends
Instrumentation
Disk drives
Mobile telecommunications
Note: *U.S. Patent Number 4918449
Simplified Block Diagram
01110809
*ADC10461 Only
**ADC10462 and ADC10464 Only
***ADC10464 Only
© 2005 National Semiconductor Corporation
DS011108
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ADC10461/ADC10462/ADC10464 10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
November 2005
ADC10461/ADC10462/ADC10464
Ordering Information
Industrial Temp Range
(−40˚C ≤ TA ≤ +85˚C)
Channels
Package
ADC10461CIWM
1
M20B Small Outline
ADC10461CIWMX
1
M20B Small Outline Tape & Real
ADC10462CIWM
2
M24B Small Outline
ADC10462CIWMX
2
M24B Small Outline Tape & Real
ADC10464CIWM
4
M28B Small Outline
ADC10464CIWMX
4
M28B Small Outline Tape & Real
Connection Diagrams
01110810
Top View
01110811
Top View
01110812
Top View
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Pin Function
Description
DVCC, AVCC
Digital and analog positive supply voltage inputs. Connect both to the same voltage source, but
bypass separately with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to
ground at each pin.
INT
Active low interrupt output. INT goes low at the end of each conversion, and returns high
following the rising edge of RD.
S/H
Sample/Hold control input. When this pin is forced low (and CS is low), the analog input signal is
sampled and a new conversion is initiated.
RD
Active low read control input. When this RD and CS are low, any data present in the output
registers will be placed onto the data bus.
CS
Active low Chip Select control input. When low, this pin enables the RD and S/H pins.
S0, S1
On the multiple-input devices (ADC10462 and ADC10464), these pins select the analog input
that will be connected to the A/D during the conversion. The input is selected based on the state
of S0 and S1 when S/H makes its High-to-Low transition (See the Timing Diagrams). The
ADC10464 includes both S0 and S1. The ADC10462 includes just S0, and the ADC10461 has
neither.
VREF−, VREF+
Reference voltage inputs. They may be placed at any voltage between GND and VCC, but VREF+
must be greater than VREF−. An input voltage equal to VREF− produces an output code of 0, and
an input voltage equal to (VREF+ − 1 LSB) produces an output code of 1023.
VIN, VIN0, VIN1, Analog input pins. The ADC10461 has one input (VIN), the ADC10462 has two inputs (VIN0 and
VIN2, VIN3
VIN1), and the ADC10464 has four inputs (VIN0, VIN1, VIN2 and VIN3). The impedance of the input
source should be less than 500Ω for best accuracy and conversion speed. For accurate
conversions, no input pin (even one that is not selected) should be driven more than 50 mV
above VCC or 50 mV below ground.
GND, AGND,
DGND
Power supply ground pins. The ADC10461 has a single ground pin (GND), and the ADC10462
and ADC10464 have separate analog and digital ground pins (AGND and DGND) for separate
bypassing of the analog and digital supplies. The ground pins should be connected to a stable,
noise-free system ground. For the devices with two ground pins, both pins should be returned to
the same potential.
DB0–DB9
TRI-STATE ® data output pins.
SPEED ADJ
(ADC10462 and ADC10464 only). This pin is normally left unconnected, but by connecting a
resistor between this pin and ground, the conversion time can be reduced. See the Typical
Performance Curves and the table of Electrical Characteristics.
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ADC10461/ADC10462/ADC10464
Pin Descriptions
ADC10461/ADC10462/ADC10464
Absolute Maximum Ratings
Operating Ratings (Notes 1, 2)
(Notes 1, 2)
Temperature Range
TMIN ≤ TA ≤ TMAX
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ADC10461CIWM,
ADC10462CIWM,
ADC10464CIWM
−40˚C ≤ TA ≤ +85˚C
Supply Voltage (V+ = AVCC = DVCC)
Voltage at Any Input or Output
−0.3V to +6V
Supply Voltage Range
4.5V to 5.5V
−0.3V to V+ + 0.3V
Input Current at Any Pin (Note 3)
5 mA
Package Input Current (Note 3)
20 mA
Power Consumption (Note 4)
875 mW
ESD Susceptibility (Note 5)
Package Thermal Resistance
2000V
Device
Soldering Information (Note 6)
N Package (10 Sec)
260˚C
SO Package:
Vapor Phase (60 Sec)
215˚C
Infrared (15 Sec)
θJA (˚C/W)
ADC10461CIWM
85
ADC10462CIWM
82
ADC10464CIWM
78
220˚C
Storage Temperature Range
−65˚C to +150˚C
Junction Temperature
150˚C
Converter Characteristics
The following specifications apply for V+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMin to TMax; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Resolution
Integral Linearity Error
RSA ≥ 18 kΩ
Full-Scale Error
10
Bits
± 1.5
±1
LSB (max)
LSB
LSB (max)
RSA ≥ 18 kΩ
± 0.5
V+ = 5V ± 5%, VREF = 4.5V
± 1/16
± 1⁄8
LSB
1 kHz, 4.85 VP-P
50 kHz, 4.85 VP-P
100 kHz, 4.85 VP-P
240 kHz, 4.85 VP-P
−68
−66
−62
−58
−60
dB
dB (max)
dB
dB
58
dB
dB (min)
dB
Missing Codes
Power Supply Sensitivity
Units
(Limit)
± 0.5
Offset Error
Total Unadjusted Error
Limit
(Note 8)
LSB
0
V+ = 5V ± 10%, VREF = 4.5V
(max)
LSB
THD
Total Harmonic Distortion
fIN
fIN
fIN
fIN
SNR
Signal-to-Noise Ratio
fIN = 1 kHz, 4.′85 VP-P
fIN = 50 kHz, 4.85 VP-P
fIN = 100 kHz, 4.85 VP-P
61
60
60
ENOB
Effective Number of Bits
fIN = 1 kHz, 4.85 VP-P
fIN = 50 kHz, 4.85 VP-P
9.6
9.5
9
RREF
Reference Resistance
650
400
Ω (min)
RREF
Reference Resistance
650
900
Ω (max)
VREF(+)
VREF(+) Input Voltage
V+ + 0.05
V (max)
VREF(−)
VREF(−) Input Voltage
GND − 0.05
V (min)
=
=
=
=
Bits
Bits (min)
VREF(+)
VREF(+) Input Voltage
VREF(−)
V (min)
VREF(−)
VREF(−) Input Voltage
VREF(+)
V (max)
VIN
Input Voltage
V+ + 0.05
V (max)
VIN
Input Voltage
GND − 0.05
V (min)
OFF Channel Input Leakage Current
CS = V+, VIN = V+
0.01
3
µA (max)
ON Channel Input Leakage Current
CS = V+, VIN = V+
±1
−3
µA (max)
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The following specifications apply for V+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit (Note
8)
Units
(Limits)
VIN(1)
Logical “1” Input Voltage
V+ = 5.5V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
V+ = 4.5V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN(1) = 5V
0.005
3.0
µA (max)
IIN(0)
Logical “0” Input Current
VIN(0) 0V
−0.005
VOUT(1)
VOUT(0)
Logical “1” Output Voltage
−3.0
µA (max)
V+ = 4.5V, IOUT = −360 µA
2.4
V (min)
V+ = 4.5V, IOUT = −10 µA
4.25
V (min)
+
Logical “0” Output Voltage
V = 4.5V, IOUT = 1.6 mA
0.4
V (max)
IOUT
TRI-STATE Output Current
VOUT = 5V
VOUT = 0V
0.1
−0.1
50
−50
µA (max)
µA (max)
DICC
DVCC Supply Current
CS = S /H = RD = 0, RSA = ∞
CS = S /H = RD = 0, RSA = 18 kΩ
1.0
1.0
2
mA (max)
mA (max)
AICC
AVCC Supply Current
CS = S /H = RD = 0, RSA = ∞
CS = S /H = RD = 0, RSA = 18 kΩ
30
30
45
mA (max)
mA (max)
AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit (Note
8)
Units
(Limits)
tCONV
Mode 1 Conversion Time from Rising
Edge of S /H to Falling Edge of INT
CIN, CIWM Suffixes
RSA = 18k
600
375
750/900
ns (max)
ns
tCRD
Mode 2 Conversion Time
CIN, CIWM Suffixes
Mode 2, RSA = 18k
850
530
1400
ns (max)
ns
tACC1
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 1; CL = 100 pF
30
60
ns (max)
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 2; CL = 100 pF
900
tCRD + 50
ns (max)
tSH
Minimum Sample Time
(Figure 1) ; (Note 9)
250
ns (max)
t1H, t0H
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
RL = 1k, CL = 10 pF
30
60
ns (max)
tINTH
Delay from Rising Edge of RD to
Rising Edge of INT
CL = 100 pF
25
50
ns (max)
tP
Delay from End of Conversion to
Next Conversion
50
ns (max)
tMS
Multiplexer Control Setup Time
10
75
ns (max)
tMH
Multiplexer Hold Time
10
40
CVIN
Analog Input Capacitance
35
pF (max)
COUT
Logic Output Capacitance
5
pF (max)
CIN
Logic Input Capacitance
5
pF (max)
tACC2
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be in from the
Package Thermal Tables.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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ADC10461/ADC10462/ADC10464
DC Electrical Characteristics
ADC10461/ADC10462/ADC10464
AC Electrical Characteristics
(Continued)
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typical figures represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs. tSH.
TRI-STATE Test Circuits and Waveforms
01110804
01110803
01110806
01110805
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ADC10461/ADC10462/ADC10464
Timing Diagrams
01110807
FIGURE 1. Mode 1. The conversion time (tCONV) is set by the internal timer.
01110808
FIGURE 2. Mode 2 (RD Mode). The conversion time (tCRD) includes the
sampling time and is determined by the internal timer.
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ADC10461/ADC10462/ADC10464
Typical Performance Characteristics
Zero (Offset) Error
vs. Reference Voltage
Linearity Error
vs. Reference Voltage
01110815
01110816
Analog Supply Current
vs. Temperature
Digital Supply Current
vs. Temperature
01110818
01110817
Conversion Time
vs. Temperature
Conversion Time
vs. Temperature
01110819
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01110820
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ADC10461/ADC10462/ADC10464
Typical Performance Characteristics
(Continued)
Conversion Time
vs. Speed-Up Resistor
(ADC10462 and ADC10464 Only)
Conversion Time
vs. Speed-Up Resistor
(ADC10462 and ADC10464 Only)
01110821
01110822
Spectral Response with
100 kHz Sine Wave Input
Spectral Response with
100 kHz Sine Wave Input
01110823
01110824
Linearity Change
vs. Speed-Up Resistor
(ADC10462 and ADC10464 Only)
Signal-to-Noise + THD Ratio
vs. Signal Frequency
01110826
01110825
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ADC10461/ADC10462/ADC10464
Typical Performance Characteristics
(Continued)
Linearity Change
vs. Speed-Up Resistor
(ADC10462 and ADC10464 Only)
Linearity Error Change
vs. Sample Time
01110828
01110827
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The ADC10461, ADC10462 and ADC10464 digitize an analog input signal to 10 bits accuracy by performing two lowerresolution “flash” conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the
second flash conversion provides the four least significant
bits LSBs).
Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024 the resistance of the whole resistor
string. These lower 16 resistors (the LSB Ladder ) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (VREF+ − VREF−) across them. The remainder of the
resistor string is made up of eight groups of eight resistors
connected in series. These comprise the MSB Ladder .
Each section of the MSB Ladder has 1⁄8 of the total reference
voltage across it, and each of the LSB resistors has 1/64 of
the total reference voltage across it. Tap points across these
resistors can be connected, in groups of sixteen, to the
sixteen comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between VREF+ and VREF−. Six comparators compare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input
voltage. This estimate is then used to control the multiplexer
that connects the MSB Ladder to the sixteen comparators on
the right. Note that the comparators on the left needn’t be
very accurate; they simply provide an estimate of the input
voltage. Only the sixteen comparators on the right and the
six on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
01110813
FIGURE 3. Block Diagram of the Multistep Converter Architecture
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ADC10461/ADC10462/ADC10464
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen comparators on the right. For example, assume that the estimator
determines that VIN is between 11/16 and 13/16 of VREF. The
estimator decoder will instruct the comparator MUX to connect the 16 comparators to the taps on the MSB ladder
between 10/16 and 14/16 of VREF. The 16 comparators will
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion produces the six most significant bits of data — four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the multistep conversion technique used in the ADC10461,
ADC10462, and ADC10464 needs only a small fraction of
the number of comparators that would be required for a
traditional flash converter, and far fewer than would be used
in a conventional half-flash approach. This allows the
ADC10461, ADC10462, and ADC10464 to perform highspeed conversions without excessive power drain.
Functional Description
ADC10461/ADC10462/ADC10464
Functional Description
completed. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but until
INT goes low the data at the output pins will be the result of
the previous conversion.
(Continued)
SIMILAR PRODUCT DIFFERENCES
The ADC1046x, ADC1046x and ADC1066x (where "x" indicates the number of multiplexer inputs) are similar devices
with different specification limits. The differences in these
device families are summarized below.
Device
Family
ILE, TUE,
PSS
THD, SNR,
ENOB
Max.
Conversion
Time
ADC1046x
Guaranteed
-
900ns
ADC1046x
-
Guaranteed
900ns
ADC1066x
-
Guaranteed
466ns
2.0 REFERENCE CONSIDERATIONS
The ADC10461, ADC10462, and ADC10464 each have two
reference inputs. These inputs, VREF+ and VREF−, are fully
differential and define the zero to full-scale range of the input
signal. The reference inputs can be connected to span the
entire supply voltage range (VREF− = 0V, VREF+ = VCC) for
ratiometric applications, or they can be connected to different voltages (as long as they are between ground and VCC)
when other input spans are required.
Reducing the overall VREF span to less than 5V increases
the sensitivity of the converter (e.g., if VREF = 2V, then 1 LSB
= 1.953 mV). Note, however, that linearity and offset errors
become larger when lower reference voltages are used. See
the Typical Performance Curves for more information. For
this reason, reference voltages less than 2V are not recommended.
In most applications, VREF− will simply be connected to
ground, but it is often useful to have an input span that is
offset from ground. This situation is easily accommodated by
the reference configuration used in the ADC10461,
ADC10462, and ADC10464. VREF− can be connected to a
voltage other than ground as long as the voltage source
connected to this pin is capable of sinking the converter’s
reference current (12.5 mA Max @ VREF = 5V). If VREF− is
connected to a voltage other than ground, bypass it with
multiple capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on
either reference input is a potential cause of conversion
errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should be
bypassed with a 10 µF tantalum and a 0.1 µF ceramic.
Applications Information
1.0 MODES OF OPERATION
The ADC10461, ADC10462, and ADC10464 have two basic
digital interface modes. Figure 1 and Figure 2 are timing
diagrams for the two modes. The ADC10462 and ADC10464
have input multiplexers that are controlled by the logic levels
on pins S0 and S1 when S/H goes low. Tables 1, 2 are truth
tables showing how the input channels are assigned.
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 250 ns. This causes the
comparators in the “coarse” flash converter to become active. When S/H goes high, the result of the coarse conversion is latched and the “fine” conversion begins. After 600 ns
(typical), INT goes low, indicating that the conversion results
are latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
3.0 THE ANALOG INPUT
The ADC10461, ADC10462, and ADC10464 sample the
analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance
approximately equal to 600Ω in series with 35 pF. Shortduration current spikes can be observed at the analog input
during normal operation. These spikes are normal and do
not degrade the converter’s performance.
Large source impedances can slow the charging of the
sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500Ω should be used if rated accuracy is to be
achieved at the minimum sample time (250 ns maximum). If
the sampling time is increased, the source impedance can
be larger. If a signal source has a high output impedance, its
output should be buffered with an operational amplifier. The
operational amplifier’s output should be well-behaved when
driving a switched 35 pF/600Ω load. Any ringing or voltage
shifts at the op amp’s output during the sampling period can
result in conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V+ + 50 mV. Do not
allow the signal source to drive the analog input pin beyond
the Absolute Maximum Rating. If an analog input pin is
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
TABLE 1. Input Multiplexer Programming
ADC10464
S1
S0
Channel
0
0
VIN0
0
1
VIN1
1
0
VIN2
1
1
VIN3
TABLE 2. Input Multiplexer Programming
ADC10462
S0
Channel
0
VIN0
1
VIN1
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S/H and RD are
pull low, INT goes low, indicating that the conversion is
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capacitors on the reference and power supply pins. If VREF−
is not grounded, it should also be bypassed to analog ground
using multiple capacitors (see 5.0 “Power Supply Considerations”). AGND and DGND should be at the same potential.
VIN0 is shown with an input protection network. Pin 17 is
normally left open, but optional “speedup” resistor RSA can
be used to reduce the conversion time.
(Continued)
damage to the IC. The sum of all the overdrive currents into
all pins must be less than the Absolute Maximum Rating for
Package Input Current. When the input signal is expected to
extend beyond this limit, an input protection scheme should
be used. A simple input protection network using diodes and
resistors is shown in Figure 4. Note the multiple bypass
01110814
FIGURE 4. Typical Connection
ground pins should have their ground pins connected to the
same potential, and all grounds should be “clean” and free of
noise.
4.0 INHERENT SAMPLE-AND-HOLD
Because the ADC10461, ADC10462, and ADC10464
sample the input signal once during each conversion, they
are capable of measuring relatively fast input signals without
the help of an external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
speed, the input signal must be stable to better than ± 1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input
signals, the signals must be externally sampled and held
constant during each conversion if a SAR with no internal
sample-and-hold is used.
Because they incorporate a direct sample/hold control input,
the ADC10461, ADC10462, and ADC10464 are suitable for
use in DSP-based systems. The S/H input allows synchronization of the A/D converter to the DSP system’s sampling
rate and to other ADC10461s, ADC10462s, and
ADC10464s.
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid overdriving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10461, ADC10462, and ADC10464, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital
circuitry can be especially troublesome.
All bypass capacitors should be located as close to the
converter as possible and should connect to the converter
and to ground with short traces. The analog input should be
isolated from noisy signal traces to avoid having spurious
signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter’s input
should be connected to a very clean ground return point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10461, ADC10462, and ADC10464 are designed to
operate from a +5V (nominal) power supply. There are two
supply pins, AVCC and DVCC. These pins allow separate
external bypass capacitors for the analog and digital portions
of the circuit. To guarantee accurate conversions, the two
supply pins should be connected to the same voltage
source, and each should be bypassed with a 0.1 µF ceramic
capacitor in parallel with a 10 µF tantalum capacitor. Depending on the circuit board layout and other system considerations, more bypassing may be necessary.
The ADC10461 has a single ground pin, and the ADC10462
and ADC10464 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
supplies. The devices with separate analog and digital
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlinearity specifications don’t accurately predict the A/D converter’s performance with AC input signals. The important specifications for AC applications reflect the converter’s ability to
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic char-
13
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ADC10461/ADC10462/ADC10464
Applications Information
ADC10461/ADC10462/ADC10464
Applications Information
(Continued)
acteristics such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), are quantitative measures of this
capability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. The resulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamental frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamental frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Guaranteed limits for THD are given in the
table of Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the
fundamental frequency to the rms value at all other frequencies, excluding any harmonic distortion components. Guaranteed limits are given in the Electrical Characteristics table.
An alternative definition of signal-to-noise ratio includes the
distortion components along with the random noise to yield a
signal-to-noise-plus-distortion ration, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more
distortion and noise occurring at higher signal frequencies.
One way of describing the A/D’s performance as a function
of signal frequency is to make a plot of “effective bits” versus
frequency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
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where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
As an example, an ADC10461 with a 4.85 VP-P, 100 kHz
sine wave input signal will typically have a signal-to-noiseplus-distortion ratio of 59.2 dB, which is equivalent to 9.54
effective bits. As the input frequency increases, noise and
distortion gradually increase, yielding a plot of effective bits
or S/(N + D) as shown in the typical performance curves.
8.0 SPEED ADJUST
In applications that require faster conversion times, the
Speed Adjust pin (pin 14 on the ADC10462, pin 17 on the
ADC10464) can significantly reduce the conversion time.
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming
current is increased, which reduces the conversion time. As
an example, an 18k resistor reduces the conversion time of
a typical part from 600 ns to 350 ns with no significant effect
on linearity. Using smaller resistors to further decrease the
conversion time is possible as well, although the linearity will
begin to degrade somewhat (see curves). Note that the
resistor value needed to obtain a given conversion time will
vary from part to part, so this technique will generally require
some “tweaking” to obtain satisfactory results.
For applications that require guaranteed performance using
the speed adjust pin, the ADC10662 and ADC10664 are
tested and guaranteed for static and dynamic performance
with a fixed value of speed-up resistor.
14
ADC10461/ADC10462/ADC10464
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number ADC10461CIWM
NS Package Number M20B
Order Number ADC10462CIWM
NS Package Number M24B
15
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ADC10461/ADC10462/ADC10464 10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Order Number ADC10464CIWM
NS Package Number M28B
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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