MOTOROLA MTB40N10E

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SEMICONDUCTOR TECHNICAL DATA

N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
40 AMPERES
100 VOLTS
RDS(on) = 0.04 OHM
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
N–Channel
D
CASE 418B–03, Style 2
D2PAK
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
VDSS
VDGR
VGS
VGSM
100
Vdc
100
Vdc
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
40
29
140
Adc
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD
169
1.35
2.5
Watts
W/°C
Watts
TJ, Tstg
EAS
– 55 to 150
RθJC
RθJA
RθJA
0.74
62.5
50
°C/W
TL
260
°C
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
°C
mJ
800
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 1
TMOS
 Motorola
Motorola, Inc.
1997
Power MOSFET Transistor Device Data
1
MTB40N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
—
—
112
—
—
—
—
—
—
10
100
—
—
100
2.0
—
2.9
6.7
4.0
—
—
0.033
0.04
—
—
—
—
1.9
1.7
gFS
17
21
—
mhos
Ciss
—
2305
3230
pF
Coss
—
620
1240
Crss
—
205
290
td(on)
—
19
40
tr
—
165
330
td(off)
—
75
150
tf
—
97
190
QT
—
80
110
Q1
—
15
—
Q2
—
40
—
Q3
—
29
—
—
—
0.96
0.88
1.0
—
trr
—
152
—
ta
—
117
—
tb
—
35
—
QRR
—
1.0
—
—
—
3.5
4.5
—
—
—
7.5
—
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
(Cpk ≥ 2.0) (3)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (1)
(Cpk ≥ 2.0) (3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 20 Adc)
(Cpk ≥ 2.0) (3)
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 40 Adc)
(ID = 20 Adc, TJ = 125°C)
VGS(th)
Vdc
RDS(on)
Ohms
VDS(on)
Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc)
mV/°C
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
(VDD = 50 Vdc,
Vd ID = 40 Adc,
Ad
VGS = 10 Vdc
Vdc,
RG = 9.1 Ω))
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
((VDS = 80 Vdc,
Vd , ID = 40 Adc,
Ad ,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
VSD
(IS = 40 Adc, VGS = 0 Vdc)
(IS = 40 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
((IS = 40 Adc,
Ad , VGS = 0 Vdc,
Vd ,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
Vdc
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
Ť
nH
Ť
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Max limit – Typ
(3) Reflects typical values. Cpk
3 sigma
+
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB40N10E
TYPICAL ELECTRICAL CHARACTERISTICS
80
VGS = 10 V
80
TJ = 25°C
8V
70
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
9V
7V
60
50
40
6V
30
20
5V
10
50
TJ = –55°C
40
30
20
0
0
1
2
3
4
5
6
7
8
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
9
10
2
3
4
5
6
7
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0.07
VGS = 10 V
0.06
TJ = 100°C
0.05
0.04
25°C
0.03
–55°C
0.02
0.01
0
0
10
20
30
40
50
60
70
80
0.050
TJ = 25°C
0.045
0.040
VGS = 10 V
0.035
0.030
15 V
0.025
0.020
0.015
0.010
0
10
20
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
1.6
30
40
50
60
ID, DRAIN CURRENT (AMPS)
70
80
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
2.0
1.8
8
Figure 2. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
25°C
60
10
0
VGS = 0 V
VGS = 10 V
ID = 20 A
1.4
I DSS , LEAKAGE (nA)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
100°C
VDS ≥ 10 V
70
1.2
1.0
0.8
0.6
TJ = 125°C
100
100°C
10
0.4
0.2
0
–50
1.0
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
0
10
50
20
30
40
60
70
80
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
90
100
Figure 6. Drain–To–Source Leakage
Current versus Voltage
3
MTB40N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
VGS = 0 V
VDS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
7000
6000
5000
Ciss
Crss
4000
3000
Ciss
2000
Coss
1000
0
–10
Crss
–5
0
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
80
VGS
9
72
QT
8
64
7
56
6
48
Q1
Q2
5
40
4
32
3
1
0
24
ID = 40 A
TJ = 25°C
2
VDS
Q3
0
10
16
20
30
40
8
0
50
60
70
10,000
t, TIME (ns)
10
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTB40N10E
VDD = 50 V
ID = 40 A
VGS = 10 V
TJ = 25°C
1000
tr
tf
100
td(off)
td(on)
10
1.0
80
10
QG, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
35
30
25
20
15
10
5
0
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.0
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
Motorola TMOS Power MOSFET Transistor Device Data
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTB40N10E
SAFE OPERATING AREA
800
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
100 ms
100
EAS , SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
1.0 ms
10
10 ms
dc
1.0
0.1
100
10
1.0
ID = 40 A
700
600
500
400
300
200
100
0
25
1000
50
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
t2
DUTY CYCLE, D = t1/t2
0.0
SINGLE PULSE
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (seconds)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
PD, POWER DISSIPATION (WATTS)
3
2.5
2.0
1.5
1
0.5
0
IS
RθJA = 50°C/W
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (°C)
Figure 14. Diode Reverse Recovery Waveform
6
Figure 15. D2PAK Power Derating Curve
Motorola TMOS Power MOSFET Transistor Device Data
MTB40N10E
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.33
8.38
0.08
2.032
0.42
10.66
0.24
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.
PD = 150°C – 25°C = 2.5 Watts
50°C/W
The 50°C/W for the D2PAK package assumes the use of the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Motorola TMOS Power MOSFET Transistor Device Data
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
RθJA versus drain pad area is shown in Figure 16.
RθJA , THERMAL RESISTANCE, JUNCTION
TO AMBIENT (°C/W)
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
70
Board Material = 0.0625″
G–10/FR–4, 2 oz Copper
60
TA = 25°C
2.5 Watts
50
3.5 Watts
40
5 Watts
30
20
0
2
4
6
8
10
A, AREA (SQUARE INCHES)
12
14
16
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
7
MTB40N10E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇÇÇÇÇÇ ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 17. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
8
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.
Motorola TMOS Power MOSFET Transistor Device Data
MTB40N10E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 –189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 6
VENT
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SPIKE”
“SOAK”
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
170°C
160°C
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 18. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
MTB40N10E
PACKAGE DIMENSIONS
C
E
V
–B–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
A
1
2
3
S
–T–
SEATING
PLANE
STYLE 2:
PIN 1.
2.
3.
4.
K
J
G
D 3 PL
0.13 (0.005)
H
M
T B
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
E
G
H
J
K
S
V
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
M
CASE 418B–03
ISSUE C
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10
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Motorola TMOS Power MOSFET Transistor MTB40N10E/D
Device Data