EM EM4150A6WS27E 1 kbit read / write contactless identification device Datasheet

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EM4150
EM4350
EM MICROELECTRONIC - MARIN SA
1 KBit READ / WRITE
CONTACTLESS IDENTIFICATION DEVICE
Description
Features
The EM4150/EM4350 (previously named P4150/P4350)
is a CMOS integrated circuit intended for use in electronic
Read/Write RF Transponders. The chip contains 1 KBit of
EEPROM which can be configured by the user, allowing a
write inhibited area, a read protected area, and a read
area output continuously at power on. The memory can
be secured by using the 32 bit password for all write and
read protected operations. The password can be updated,
but never read. The fixed code serial number and device
identification are laser programmed making every chip
unique.
The EM4150 will transmit data to the transceiver by
modulating the amplitude of the electromagnetic field, and
receive data and commands in a similar way. Simple
commands will enable write to EEPROM, to update the
password, to read a specific memory area, and to reset
the logic.
The coil of the tuned circuit is the only external component
required, all remaining functions are integrated in the chip.
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The only difference between EM4150 and EM4350 is that
EM4150 comes with standard sized pads, whereas
EM4350 comes with oversized (mega) pads, ideal for use
with bumps on die (Fig. 27).
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Typical Operating Configuration
Pin Assignment
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1 KBit of EEPROM organized in 32 words of 32 bits
32 bit Device Serial Number (Read Only Laser ROM)
32 bit Device Identification (Read Only Laser ROM)
Power-On Reset sequence
Power Check for EEPROM write operation
User defined Read Memory Area at Power On
User defined Write Inhibited Memory Area
User defined Read Protected Memory Area
Data Transmission performed by Amplitude
Modulation
Two Data Rate Options 2 KBd (Opt64) or 4 KBd
(Opt32)
Bit Period = 64 or 32 periods of field frequency
170 pF ± 2% on chip Resonant Capacitor
-40 to +85°C Temperature range
100 to 150 kHz Field Frequency range
On chip Rectifier and Voltage Limiter
No external supply buffer capacitance needed due to
low power consumption
Applications
Ticketing
Automotive Immobilizer with rolling code
High Security Hands Free Access Control
Industrial automation with portable database
Manufacturing automation
Prepayment Devices
Coil 2
L
COIL2
COIL2
EM4150
COIL1
COIL1
EM4150
Coil 1
COIL 1
COIL 2
Coil terminal / Clock input
Coil terminal
Typical value of inductance at 125 KHz is 9.5 mH
Fig. 2
Fig. 1
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EM4150
EM4350
Absolute Maximum Ratings
Parameter
Maximum AC peak current
induced on COIL1 and COIL2
Handling Procedures
Symbol
ICOIL
Conditions
Power Supply
VDD
-0.3 to 6.0V
Maximum voltage other pads
Vmax
VDD + 0.3V
± 30 mA
Minimum voltage other pads
Vmin
VSS – 0.3V
Storage temperature
Tstore
-55 to °125°C
Electrostatic discharge
maximum to MIL-STD-883C
method 3015
VESD
1000V
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions should be taken as for any other CMOS
component.
Unless otherwise specified, proper operation can only
occur when all terminal voltages are kept within the
supply voltage range.
Operating Conditions
Parameter
Operating
temperature
Maximum coil
current
AC Voltage on
coil
Supply frequency
Symbol
Top
Min
-40
Typ
ICOIL
Vcoil
Max
+85
Units
°C
10
mA
1)
fcoil
100
Vpp
150
kHz
Note 1): Maximum voltage is defined by forcing 10mA on Coil1Coil2
Tranceiver
Data to be sent
to transponder
Modulator
Oscillator
Antenna
Driver
Transponder
Coil1
EM4150
Coil2
Filter
and
Gain
Demodulator
Data received
from transponder
Data decoder
READ MODE
RECEIVE MODE
Signal on
Transponder coil
Signal on
Transceiver coil
Signal on
Transceiver coil
Signal on
Transponder coil
RF Carrier
RF Carrier
Data
Data
Fig. 3
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EM4150
EM4350
Electrical Characteristics
VDD = 2.5V, VSS = 0V, fcoil = 125 kHz Sine wave, Vcoil = 1Vpp, Top = 25°C unless otherwise stated
Parameter
Symbol Test Conditions
Min
Supply voltage
VDD
2.0
2.6
VDDee
Minimum EEPROM write
voltage
Power Check EEPROM write
IPWcheck
VDD = 3V
Supply current / read
Suppy current / write
Ird
Iwr
Modulator ON voltage drop
VON
Resonance Capacitor
Power On Reset level high
Clock extractor input min.
Clock extractor input max.
EEPROM data endurance
EEPROM retention
Cr
Vprh
Vclkmin
Vclkmax
Ncy
Tret
Read Mode
Write mode (VDD = 3V)
Typ
Max
5.5
Units
V
V
80
µA
3.0
40
5.0
70
0.50
2.50
µA
170
2.0
173.5
2.6
pF
V
Vpp
mVpp
cycles
years
V(COIL1–Vss) and V(COIL2-Vss) Icoil = 100µA
V(COIL1–Vss) and V(COIL2-Vss) Icoil = 5mA
166.5
Rising Supply
Minimum voltage for Clock Extraction
Maximum voltage to detect modulation stop
Erase all / Write all at VDD = 5V
Top = 55°C after 100'000 cycles (Note 1)
1.0
50
100'000
10
µA
V
V
Note 1: Based on 1000 hours at 150°C
Timing Characteristics
VDD = 2.5V, VSS = 0V, fcoil = 125 kHz Sine wave, Vcoil = 1Vpp, Top = 25°C unless otherwise stated
All timings are derived from the field frequency and are specified as a number of RF periods.
Parameters
Option : 64 clocks per bit
Symbol
Value
Units
64
320
3200
64
64
2112
3200
RF periods
RF periods
RF periods
RF periods
RF periods
RF periods
RF periods
32
160
1600
32
32
1056
2624
RF periods
RF periods
RF periods
RF periods
RF periods
RF periods
RF periods
Opt64
Read Bit Period
LIW/ACK/NACK pattern Duration
Read 1 Word Duration
Processing Pause Time
Write Access Time
Initialization Time
EEPROM write time
Option : 32 clocks per bit
Test conditions
trdb
tpatt
trdw
tpp
twa
tinit
twee
including LIW
VDD = 3 V
Opt32
Read Bit Period
LIW/ACK/NACK pattern Duration
Read 1 Word Duration
Processing Pause Time
Write Access Time
Initialization Time
EEPROM write time
trdb
tpatt
trdw
tpp
twa
tinit
twee
including LIW
VDD = 3 V
RF periods represent periods of the carrier frequency emitted by the transciever unit. For example, if 125 kHz is used :
The Read bit period (Opt64) would be : 1/125'000*64 = 512 µs, and the time to read 1 word : 1/125'000*3200 = 25.6 ms.
The Read bit period (Opt32) would be : 1/125'000*32 = 256 µs, and the time to read 1 word : 1/125'000*1600 = 12.8 ms.
ATTENTION
Due to amplitude modulation of the coil-signal, the clock-extractor may miss clocks or add spurious clocks close
to the edges of the RF-envelope. This desynchronisation will not be larger than ±3 clocks per bit and must be
taken into account when developing reader software.
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EM4150
EM4350
Block Diagram
+V
Coil 2
Cr
Coil 1
Voltage
Regulation
AC/DC
converte
r
ROM
Serial Data
Encoder
Modulator
EEPROM
VDD
Power
Control
Cs
Reset
GND
Write Enable
Clock
Extractor
Sequencer
Control
Logic
Command
Decoder
Data
Extractor
Fig. 4
Functional Description
General
The EM4150 is supplied by means of an electromagnetic
field induced on the attached coil. The AC voltage is
rectified in order to provide a DC internal supply voltage.
When the DC voltage crosses the Power-On level, the
chip enters the Standard Read Mode and sends data
continuously. The data to be sent in this mode is user
defined by storing the first and last addresses to be
output. When the last address is sent, the chip will
continue with the first address until the transceiver sends
a request. In the read mode, a Listen Window (LIW) is
generated before each word. During this time, the
EM4150 will turn to the Receive Mode (RM) if it receives
a valid RM pattern. The chip then expects a valid
command.
Memory Organisation
The 1024 bit EEPROM is organised in 32 words of 32
bits. The first three words are assigned to the Password,
the Protection word, and the Control word. In order to
write one of these three words, it is necessary to send
the valid password. At fabrication, the EM4150 comes
with all bits of the password programmed to a logic "0".
The Password cannot be read out. The memory contains
two extra words of Laser ROM. These words are laser
programmed during fabrication for every chip, are unique
and cannot be altered.
Memory Map
Bit 0
Word 0
1
2
Mode of Operation
Init
Standard
Read Mode
No
31
32
33
Get Command
Yes
DEVICE SERIAL NUMBER
DEVICE IDENTIFICATION
Control Word
0 - 7 First Word Read
8 - 15 Last Word Read
16 Password Check On/Off
17 Read After Write On/Off
18 - 31 User available
Execute Command
Login
Write Word
Laser
Laser
Protection Word
0 - 7 First Word Read Protected
8 - 15 Last Word Read Protected
16 - 23 First Word Write Inhibited
24 - 31 Last Word Write Inhibited
Password
Write Only - NO Read Access
Write Password
Send word
Bit 31
EE
EE
EE
EE
928 Bits of USER
EEPROM
Power-On
Receive
Mode
request ?
PASSWORD
PROTECTION WORD
CONTROL WORD
Selective Read
Reset
On means bit set to logic '1'
Off means bit set to logic '0'
Device Identification Word &
Serial Number Word
Laser Programmed - Read Only
Fig. 6
Fig. 5
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EM4150
EM4350
Standard Read Mode
Receive Mode
After a Power-On Reset and upon completion of a
command, the chip will execute the Standard Read
Mode, in which it will send data continuously, word by
word from the memory section defined between the First
Word Read (FWR) and Last Word Read (LWR). When
the last word is output, the chip will continue with the first
word until the transceiver sends a request. If FWR and
LWR are the same, the same word will be sent
repetitively. The Listen Window (LIW) is generated
before each word to check if the transceiver is sending
data. The LIW has a duration of 320 (160 opt 32) periods
of the RF field. FWR and LWR have to be programmed
as valid addresses (FWR ≤ LWR and ≤ 33).
The words sent by the EM4150 comprise 32 data bits
and parity bits. The parity bits are not stored in the
EEPROM, but generated while the message is sent as
described below. The parity is even for rows and
columns, meaning that the total number of "1's" is even
(including the parity bit).
To activate the Receive Mode, the Transceiver sends to
the chip the RM pattern (while in the modulated phase of
a Listen Window LIW). The EM4150 will stop sending
data upon reception of a valid RM. The chip then expects
a command. The RM pattern consists of 2 bits "0" sent
by the transceiver. The first bit "0" transmitted is to be
detected during the 64 (32 opt 32) periods where the
modulation is "ON" in LIW.
OUTPUT
D0
D8
D16
D24
PC0
D1
D9
D17
D25
PC1
D3
D11
D19
D27
PC3
D2
D10
D18
D26
PC2
D4
D12
D20
D28
PC4
Column Even Parity
D5
D13
D21
D29
PC5
D6
D14
D22
D30
PC6
D7
D15
D23
D31
PC7
RM
COMMAND
RM : Two Consecutive bits set to logic "0"
Fig. 9
Commands
The commands are composed of nine bits : eight data
bits and one even parity bit (total amount of "ones" is
even including the parity bit).
Row Even Parity
Data
LIW
INPUT
Word Organisation (Words 0 to 32)
First bit output
WORD n
P0
P1
P2
P3
0
Last bit output
logic "0"
Fig. 7a
When a word is read protected, the output will consist of
45 bits set to logic "0". The password has to be used to
output correctly a read protected memory area.
COMMAND BITS
FUNCTION
00000001 1
LOGIN
00010001 0
WRITE PASSWORD
00010010 0
WRITE WORD
00001010 0
SELECTIVE READ MODE
10000000 1
RESET
Word Organisation (Word 33)
C0
ID2
R0
CK0
PC0
C1
C2
ID3 ID4
R1
R2
CK1 CK2
PC1 PC2
C3
C4
ID5 ID6
R3
R4
CK3 CK4
PC3 PC4
C5 ID0
ID7 ID8
R5
R6
CK5 CK6
PC5 PC6
ID1
ID9
R7
CK7
PC7
First bit
Received
P0
P1
P2
P3
0
Fig. 10
Selective Read Mode
C0 - C5
: P4150 Code set to Hexadecimal 32
ID0 - ID9
: Version Code
R0 - R7 / CK0 - CK7 : EM reserved, and Check bits
The Selective Read Mode is used to read other data than
that defined between FWR and LWR. To enter Selective
Read Mode, the Transceiver has to send during LIW a
Receive mode pattern (RM) to turn the EM4150 in
Receive Mode. Then the Selective Read Mode
Command is sent by the transceiver followed by the First
and Last addresses to be read. The FWR and LWR are
then replaced by the new addresses and the chip is
operating in the same way as the Standard Read Mode.
The control word is not modified by this command, and
the next standard read mode operation will work with
original FWR and LWR (Selected area is read once and
then the chip returns to Standard Read Mode).
To read words which are Read Protected, a Login
command has to be sent by the transceiver prior to the
Selective Read command. The Login command is to be
used only once for all subsequent commands requiring a
password.
Fig. 7b
Read Sequence
POR
INIT
LIW LIW
OUTPUT
LIW
T0 periods :
32 32
128
16 16
64
D0-D7
FWR
P0 D8-D15
LIW FWR+1
LWR LIW LIW
FWR
P1 D16-D23 P2 D24-D31 P3 PC0-PC7
LIW
"0"
1 bit - 64 T0 periods (Opt64)
32 T0 periods (Opt32)
64
64
(Opt64)
32
32
(Opt32)
Parity bit
Data
Coded Data
T0 = Period of RF carrier frequency
Fig. 8
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EM4150
EM4350
Selective Read Mode cont.
The Selective Read mode command is followed by a single 32-bit word containing the new first and last addresses. Bits 0
to 7 correspond to the First Word Read and bits 8 to 15 correspond to the Last Word Read. Bits 16 to 31 have to be sent
but are not used in the chip. The parities must be sent according to the word organisation as described in fig.7. Note that
bit 31 is transmitted first.
To read the device Identification or the Serial Number, the Selective Read Command allows direct access to the Laser
programmed words. These words can also be addressed in the standard read mode by selecting the addresses
accordingly.
OUTPUT
WORD n
INPUT
LIW
ACK/NAK
RM
Selective RD
LIW
LIW
FWR
LIW
ADDRESSES
t pp
Fig. 11
First bit received
XX
XX
XX
XX
XX
XX
Addresses Bit Stream Format
XX
XX
P3 XX
XX
XX
XX
XX
XX
XX
XX
P2
LW7 LW6 LW5 LW4 LW3 LW2 LW1 LW0 P1 FW7 FW6 FW5 FW4 FW3 FW2 FW1 FW0 P0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 "0"
Fig. 12
Reset Command
The Reset Command will return from any mode to the Standard Read Mode. The next word out is the FWR.
OUTPUT
LIW
WORD n
RM
INPUT
ACK/NAK
LIW
LIW
FWR
LIW
RESET
t pp
t init
Fig. 13
Login
The Login command is used to access protected memory areas. This command has to be used only once to perform
several password protected commands. The Power-On sequence and the Reset command will reset the password entry,
and a new Login command has to be received to perform further password protected operations.
Upon reception of a correct password, the EM4150 will respond with an acknowledge pattern (ACK) and then continue in
Standard Read Mode. If the Login is correct then password protected operations are allowed. If the password is incorrect, a
NAK pattern is issued and password protected operations will not be possible (refer to Write Word for password data
structure).
OUTPUT
INPUT
WORD n
LIW
RM
ACK/NAK
LOGIN
LIW
LIW
FWR
LIW
PASSWORD
t pp
Fig. 14
If bit 16 of the control word is disabled (Password Check ON/OFF), the Login is still mandatory to modify the Protection
Word, the Control Word, and the Password, but not to write in the EEPROM which is not write inhibited. In order to modify a
write inhibited word, the Protection word has to be modified first. The Read protected area always requires the Login to be
read. If the Write Protection Word is write protected, the write protection configuration is locked.
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EM4150
EM4350
Write Password
When a Write Password command is received, the chip next expects information on the actual valid password. The chip
sends back an ACK pattern if the password is correct. Then the chip expects the new password consisting of 32 bits +
parity bit to be stored in the EEPROM. The chip will respond with an ACK pattern for a correct reception of data upon
reception of the new password, and then will send another acknowledge pattern (ACK) to announce that the data is stored
in the EEPROM.
The Read after Write function has no effect on this command. If the password is wrong or the
transmission is faulty, the chip will : send a NAK pattern; return to the Standard Read Mode; and, the password will remain
the same. (Refer to Write Word for password data structure).
t pp
OUTPUT
WORD n
ACK
LIW
RM
INPUT
t wa
WRITE PW
ACTUAL PW
t wee
ACK
LIW
RM
ACK
LIW
LIW
FWR
NEW PW
TRANSCEIVER RF FIELD "ON"
Fig. 15
Write Word
The Write mode allows modification of the EEPROM contents word by word. To modify address 1 (Protection word) and
address 2 (Control word), it is mandatory to first send a Login command in order to Log in (like in a computer). The new
written values will take effect only after performing a Reset command. It is strongly recommended to check the result of
modifying the contents of these addresses effecting the function of the chip. Address 0 (Password) cannot be modified with
this command but can be changed with the Write Password command.
Addresses 3 to 31 are programmable according to the defined protections. If the Password Check bit is off (bit 16 of control
word) and the word is not write inhibited, the selected word can be freely modified without password. If the Password Check
bit is on and the word is not write inhibited, the selected word can be modified with a previous Login. In any case, if the
word is write inhibited, the protection word has to be changed before programming can occur.
Write to Address
0
1–2
1–2
3 – 31
3 – 31
3 – 31
Check Password bit
(16 bit / Control word)
X
X
X
OFF
ON
X
Write Inhibit
(Protection word)
X
OFF
ON
OFF
OFF
ON
Write Operation
Only with Write Password command
Login always required
Write configuration LOCKED
Freely programmable
Login required
Change protection word first
Address
0 0 A5 A4 A3 A2 A1 A0
Padd
First bit received
Note :
A5 in write mode always "0"
(addresses Laser ROM)
Data
D31 D30 D29 D28 D27 D26 D25 D24 P3 D23 D22 D21 D20 D19 D18 D17 D16 P2 D15 D14
D13 D12 .......................... D02 D01 D00 P0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 "0"
Fig. 16
The Write Word command is followed by the address and data. The address consists of a 9 bit block containing 8 data bits
and 1 even parity bit. Only 6 bits from the data section are used for the word addressing, and the first three bits sent must
be "0". The data consists of 4 times 9 bit blocks, each block consisting of 8 data bits and 1 associated even parity bit and
one additional block consisting of 8 column parity bits and "0" as stop bit (Refer to fig. 7)
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EM4150
EM4350
Write Word (cont.)
After reception of the command, the address, and the data, the EM4150 will check the parity, the write protection status, the
Login status, and also if the available power from the RF field is sufficient. If all the conditions are satisfied, an acknowledge
pattern (ACK) will be issued afterward and the EEPROM writing process will start. At the end of programming, the chip will
send an Acknowledge pattern (ACK). If at least one of the checks fails, the chip will issue a no acknowledge pattern (NAK)
instead of ACK and return to the Standard Read Mode. The Transceiver will keep the RF field permanently "ON" during the
whole writing process time.
The Read After Write function (bit 17 of Control word) controls the mode of operation following a write operation. When
"ON" the latest written word will be read out and output next to the ACK pattern and two Listen Windows (LIW-LIW) even if
the word is read protected. When "OFF", the ACK is followed immediately by a LIW-LIW and FWR. The last written word is
not output.
If a request from the transceiver to return in receive mode (RM) is generated during the LIW, another word can be written in.
Otherwise, the EM4150 will return in the Standard Read Mode.
t wa
t wee
Write 1 word
OUTPUT
WORD n
INPUT
LIW
RM WRITE WORD ADDRESS
ACK
ACK
LIW
ACK
LIW
LIW
FWR
DATA
TRANSCEIVER RF FIELD "ON"
t wa
t wee
Write several words
OUTPUT
WORD n
LIW
RM WRITE WORD ADDRESS
INPUT
ACK
DATA
RM WRITE WORD ADDRESS
DATA
TRANSCEIVER RF FIELD "ON"
t wa
Read After Write function
OUTPUT
WORD n
LIW
RM WRITE WORD ADDRESS
INPUT
t wee
ACK
Note: The Last Written is outpout
even if Read Protected.
ACK
LIW
LIW
Last Written LIW
LIW
FWR
DATA
TRANSCEIVER RF FIELD "ON"
t wa
OUTPUT
INPUT
WORD n
LIW
RM WRITE WORD ADDRESS
NAK
LIW
LIW
FWR
DATA
TRANSCEIVER RF FIELD "ON"
Fig. 17
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EM4150
EM4350
AC/DC Converter and Voltage Limiter
Power On Reset (POR)
When the EM4150 with its attached coil enters an
electromagnetic field, the built in AC/DC converter will
supply the chip. The DC voltage is monitored and a
Reset signal is generated to initialise the logic. The
contents of the Control word and Protection word will be
downloaded to enable the functions (INIT). The Power
On Reset is also provided in order to make sure that the
chip will start issuing correct data. Hysteresis is provided
to avoid improper operation at the limit level.
The AC/DC converter is fully integrated on chip and will
extract the power from the incident RF field. The internal
DC voltage will be clamped to avoid high internal DC
voltage in strong RF fields.
Resonance Capacitor
The Resonance Capacitor is integrated, and its tolerance
is adjusted to ± 2% over the whole production.
Typical Capacitor Variation
versus Temperature
VDD
Vprh
Cr Tolerance [%]
Vprhys
100.3
100.2
t
100.1
Reset
tinit
100.0
99.9
EM4150 Active
99.8
t
99.7
-50
Fig. 18
-30
-10
10
30
50
70
Fig. 19
Lock All / Lock Memory Area
The EM4150 can be converted to a Read Only chip or be
configured to Read/Write and Read Only Areas by
programming the protection word. This configuration can
be locked by write inhibiting the Write Protection Word.
Great care should be taken in doing this operation as
there is no further possibility to change the Write
Protection Word. The Control Word can also be
protected in the same way thus freezing the operation
mode.
90
Temperature [°C]
Special Timings
The Processing Pause Time (tpp), Write Access Time
(twa) and EEPROM Write Time (Twee) are timings
where the EM4150 is executing internal operations.
During these pauses, the RF field will be influenced.
Clock Extractor
RF periods : 32 32 (Opt64)
64
(Opt64)
3200
(Opt64)
16 16 (Opt32)
32
(Opt32)
2624
(Opt32)
t pp
The Clock extractor will generate a system clock with a
frequency corresponding to the frequency of the RF field.
The system clock is used by a sequencer to generate all
internal timings.
Same modulation
as for a normal bit
t wa
t wee
During Twa and Twee, the signal on the coil is
damped due to a higher current consumption.
Fig. 20
Data Extractor
The transceiver generated field will be amplitude
modulated to transmit data to the EM4150. The Data
extractor demodulates the incoming signal to generate
logic levels, and decodes the incoming data.
Modulator
The Data Modulator is driven by the serial data output
from the memory which is Manchester encoded. The
modulator will draw a large current from both coil
terminals, thus amplitude modulating the RF field
according to the memory data.
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EM4150
EM4350
Communication from Transponder to the Transceiver ( READ MODE)
The EM4150 modulates the amplitude of the RF field to transmit data to the transceiver. Data are output serially from the
EEPROM and Manchester encoded.
1 bit 64 periods of RF field (Opt64)
32 periods of RF field (Opt32)
1 bit
1 bit
1 bit
32 periods (Opt64)
16 periods (Opt32)
Data from EEPROM
Coded Data Measured on the COIL
Opt64 is the chip option with a bit period corresponding to 64 periods of the RF field
Opt32 is the chip option with a bit period corresponding to 32 periods of the RF field
Fig. 21
The EM4150 uses different patterns to send status information to the transceiver. Their structure can not be confused with a
bit pattern sequence. These patterns are the Listen Window (LIW) to inform the transceiver that data can be accepted, the
Acknowledge (ACK) indicating proper communication and end of EEPROM write, and the No Acknowledge (NAK) when
something is wrong.
The LIW, due to its special structure, can be used to synchronize the transceiver during a read operation. The LIW is sent
before each word, and is sent twice before FWR.
LIW
ACK
NAK
32 32
128
64
64
(Opt64)
32 32
96
32
96
32
(Opt64)
32 32
96
32
64
32 32
(Opt64)
16 16
64
32
32
(Opt32)
16 16
48
16
48
16
(Opt32)
16 16
48
16
32
16 16
(Opt32)
All numbers represent number of periods of RF field
Opt64 is the chip option with a bit period corresponding to 64 periods of the RF field
Opt32 is the chip option with a bit period corresponding to 32 periods of the RF field
Fig. 22
Communication from the Transceiver to the Transponder (RECEIVE MODE)
The EM4150 can be switched to the Receive Mode ONLY DURING A LISTEN WINDOW. The Transceiver is synchronized
with the incoming data from the transponder and expects a LIW before each word. During the phase where the chip has its
modulator "ON" (64/32 periods of RF [Opt64/Opt32] ), the transceiver has to send a bit "0". A certain phase shift in the read
path of the transceiver can be accepted due to the fact that when entering Receive Mode, the Transceiver becomes the
Master.
At reception of the first "0", the chip immediately stops the LIW sequence and then expects another bit "0" to activate the
receive mode. Once the EM4150 has received the first bit "0", the transceiver is imposing the timing for synchronisation.
The EM4150 turns "ON" its modulator at the beginning of each frame of a bit period. To send a logic "1" bit, the transceiver
continues to send clocks without modulation. After half a bit period, the modulation device of the EM4150 is turned "OFF"
allowing recharge of the internal supply capacitor. To send a logic "0" bit, the transceiver stops sending clocks (100%
modulation) during the first half of a bit period. The transceiver must not turn "OFF" the field after 7/4 clocks of the bit period
(Opt64/Opt32). The field is stopped for the remaining first half of the bit period, and then turned "ON" again for the second
half of the bit period. The 32rd/16th clock (Opt64/Opt32) defines the end of the bit
To ensure synchronisation between the transceiver and the transponder, a logic bit set to "0" has to be transmitted at
regular intervals. The RM pattern consists of two bits set to "0" thus allowing initial synchronisation. In addition, the chosen
data structure contains even parity bits which will not allow more than eight consecutive bits set to logic "1" where no
modulation occurs.
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EM4150
EM4350
Communication from the Transceiver to the Transponder (RECEIVE MODE)
(cont.)
While the transceiver is sending data to the transponder, two different modulations will be observed on both coils. During
the first half of the bit period, the EM4150 is switching "ON" its modulation device causing a modulation of the RF field. This
modulation can also be observed on the transceiver's coil. The transceiver sending a bit "0" will switch "OFF" the field,
causing a 100% modulation being observed on the transponder coil.
Bit
Period
DATA
:
"1"
"0"
"0"
"1"
"0"
"1"
Transceiver
Coil
Transponder
Coil
Periods of RF field (Opt 64):
32
32
32
32
Periods of RF field (Opt 32):
16
16
16
16
*
Modulation induced by the Transceiver
* Recommended
Minimum
: 7/4 periods (Opt64/Opt32)
: 1 period
Modulation induced by the Transponder
Fig. 23
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EM4150
EM4350
Pad Description
Pad
1
2
3
4
5
6
7
8
9
Name
Function
COIL1
VPOS
TEST_IN
VDD
TEST_OUT
TEST
TEST_CLK
VSS
COIL2
Coil Terminal 1
Internal supply
Test input with pull-down
Positive Internal Supply Voltage
Test Output
Test Mode Input with pull-down
Test Clock input with pull-down
Negative Internal Supply Voltage
Coil terminal 2
8
7
9
6
5
4
1
3
2
Packages
CID Package
PCB Package
FRONT VIEW
Y
K
J
TOP VIEW
B
D
Z
MARKING
AREA
A
SYMBOL
A
B
D
e
F
g
J
K
R
MIN
8.2
3.8
5.8
0.38
1.25
0.3
0.42
0.115
0.4
TYP
8.5
4.0
6.0
0.5
1.3
0.4
0.44
0.127
0.5
MAX
8.8
4.2
6.2
0.62
1.35
0.5
0.46
0.139
0.6
X
C2
Dimensions are in mm
R
SYMBOL MIN
TYP
X
8.0
Y
4.0
Z
Dimensions are in mm
e
C2
C1
F
F
C1
g
Fig. 24
MAX
1.0
Fig. 25
Chip Dimensions
Fig. 26
Copyright © 2004, EM Microelectronic-Marin SA
Fig. 27
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EM4150
EM4350
Ordering Information
Die Form
This chart shows general offering; for detailed Part Number to order, please see the table “Standard Versions” below.
EM4150 A6 WS 11
- %%%
Circuit Nb:
EM4150: standard pads
EM4350: mega pads
Customer Version:
%%% = only for custom specific version
Version:
A6 = Manchester, 64 clocks per bit
A5 = Manchester, 32 clocks per bit
Bumping:
" " (blank) = no bumps
E = with Gold Bumps (Note 2)
Die form:
WW = Wafer
WS = Sawn Wafer/Frame
WT = Sticky Tape
WP = Waffle Pack (note 1)
Thickness:
6 = 6 mils (152um)
7 = 7 mils (178um)
11 = 11 mils (280um)
21 = 21 mils (533um)
27 = 27 mils (686um)
Packaged Devices
This chart shows general offering; for detailed Part Number to order, please see the table “Standard Versions” below.
EM4150 A6 CI2LC - %%%
Circuit Nb:
EM4150: standard pads
Customer Version:
%%% = only for custom specific version
Version:
A6 = Manchester, 64 clocks per bit
A5 = Manchester, 32 clocks per bit
Package/Card & Delivery Form:
CI2LB = CID Pack, 2 long pins (2.5mm), in tape
CI2LC = CID Pack, 2 long pins (2.5mm), in bulk
CI2SB = CID Pack, 2 short pins (1.25mm), in tape
CI2SC = CID Pack, 2 short pins (1.25mm), in bulk
CB2RC = PCB Package, 2 pins, in bulk
SO8A = SO-8 Package, in stick (note 1)
Remarks:
•
For ordering please use table of “Standard Version” table below.
•
For specifications of Delivery Form, including gold bumps, tape and bulk, as well as possible other delivery form or
packages, please contact EM Microelectronic-Marin S.A.
•
Note 1: This is a non-standard package. Please contact EM Microelectronic-Marin S.A for availability.
•
Note 2: EM4350 is preferably used with gold bumps. Use of EM4150 with gold bump together with direct technology is
subject to license, please contact EM Sales Office.
Copyright © 2004, EM Microelectronic-Marin SA
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EM4150
EM4350
Standard Versions & Samples:
For samples please order exclusively:
Part Number
Bit coding
Cycle/
bit
EM4150A6CI2LC
Manchester
64
Standard CID package, 2 pins (length 2.5mm) bulk
EM4150A6CB2RC
Manchester
64
Standard PCB Package, 2 pins
Pads
Package
Delivery
Form
bulk
The versions below are considered standards and should be readily available. For other versions or other delivery form,
please contact EM Microelectronic-Marin S.A. Please make sure to give complete part number when ordering, without
spaces between characters.
Part Number
Bit coding
Cycle/
bit
EM4150A5CB2RC
Manchester
32
Standard PCB Package, 2 pins
EM4150A5CI2LC
Manchester
32
Standard CID package, 2 pins (length 2.5mm)
bulk
EM4150A5CI2SC
Manchester
32
Standard CID package, 2 pins (length 1.25mm)
bulk
EM4150A6CB2RC
Manchester
64
Standard PCB Package, 2 pins
bulk
EM4150A6CI2LB
Manchester
64
Standard CID package, 2 pins (length 2.5mm)
tape
EM4150A6CI2LC
Manchester
64
Standard CID package, 2 pins (length 2.5mm)
bulk
EM4150A6CI2SB
Manchester
64
Standard CID package, 2 pins (length 1.25mm)
tape
EM4150A6CI2SC
Manchester
64
Standard CID package, 2 pins (length 1.25mm)
bulk
Pads
Package/Die Form
Delivery Form
/ Bumping
bulk
EM4150A6SO8A
Manchester
64
Standard SO-8 package
stick
EM4150A6WS6
Manchester
64
Standard Sawn wafer, 6 mils
no bumps
EM4150A6WS7
Manchester
64
Standard Sawn wafer, 7 mils
no bumps
EM4150A6WW27
Manchester
64
Standard Unsawn wafer, 27 mils
no bumps
EM4150A6WW7
Manchester
64
Standard Unsawn wafer, 7 mils
no bumps
EM4150XXYYY-%%%
Manchester
32/64
Standard custom
custom
EM4350A6WP11E
Manchester
64
Mega
Die in waffle pack, 11 mils
EM4350A6WS11E
Manchester
64
Mega
Sawn wafer, 11 mils
with gold bumps
with gold bumps
EM4350A6WT11E
Manchester
64
Mega
Die on sticky tape, 11 mils
with gold bumps
EM4350XXYYY-%%%
Manchester
32/64
Mega
custom
custom
Product Support
Check our Web Site under Products/RF Identification section.
Questions can be sent to [email protected]
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an
EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without
notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
© EM Microelectronic-Marin SA, 08/04, Rev. F
Copyright © 2004, EM Microelectronic-Marin SA
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