Maxim DS4412 Dual-channel, i2c adjustable sink/source current dac Datasheet

Rev 1; 10/08
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
The DS4412 contains two I2C adjustable-current DACs
that are each capable of sinking or sourcing current. Each
output has 15 sink and 15 source settings that are programmed by I2C interface. The full-scale range and step
size of each output is determined by an external resistor
that can adjust the output current over a 4:1 range.
The output pins, OUT0 and OUT1, power-up in a highimpedance state.
Applications
Power-Supply Adjustment
Features
♦ Two Current DACs
♦ Full-Scale Current 500µA to 2mA
♦ Full-Scale Range for Each DAC Determined by
External Resistors
♦ 15 Settings Each for Sink and Source Modes
♦ I2C-Compatible Serial Interface
♦ Low Cost
♦ Small Package (8-Pin µSOP)
♦ -40°C to +85°C Temperature Range
♦ 2.7V to 5.5V Operation
Power-Supply Margining
Adjustable Current Sink or Source
Ordering Information
Pin Configuration
TOP VIEW
+
SDA 1
SCL
2
FS1
3
GND
4
DS4412
8
VCC
7
OUT1
6
OUT0
5
FS0
PART
TEMP RANGE
PIN-PACKAGE
DS4412U+
-40°C to +85°C
8 μSOP
DS4412U+T&R
-40°C to +85°C
8 μSOP
+Denotes a lead-free/RoHS-compliant package.
T&R = Tape and reel.
μSOP
Typical Operating Circuit
VCC
VOUT0
VOUT1
4.7kΩ
4.7kΩ
OUT
VCC
SDA
SCL
DC-DC
CONVERTER
OUT0
DS4412
R0A
FB
R1A
FB
R0B
FS0
DC-DC
CONVERTER
OUT1
GND
RFS0
OUT
R1B
FS1
RFS1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS4412
General Description
DS4412
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .....................................Refer to IPC/JEDEC
J-STD-020 Specification
Voltage Range on VCC, SDA, and SCL
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on OUT0, OUT1 Relative to
Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
VCC
(Note 1)
MIN
TYP
MAX
UNITS
2.7
5.5
V
VCC +
0.3
V
0.3 x
VCC
V
MAX
UNITS
500
μA
1
μA
1
μA
Input Logic 1 (SDA, SCL)
VIH
0.7 x
VCC
Input Logic 0 (SDA, SCL)
VIL
-0.3
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
Supply Current
ICC
VCC = 5.5V (Note 2)
Input Leakage (SDA, SCL)
I IL
VCC = 5.5V
Output Leakage (SDA)
IL
Output Current Low (SDA)
I OL
RFS Voltage
VRFS
I/O Capacitance
CI/O
MIN
VOL = 0.4V
3
VOL = 0.6V
6
TYP
mA
0.607
V
10
pF
MAX
UNITS
0.5
3.5
V
V
OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
Output Voltage for Sinking
Output Voltage for Sourcing
Current
Full-Scale Sink Output Current
Full-Scale Source Output Current
SYMBOL
VOUT:SINK
CONDITIONS
VCC > V OUT:SINK (Note 3)
TYP
VOUT:SOURCE
(Note 3)
0
VCC 0.75
IOUT:SINK
(Note 3)
0.5
2.0
mA
IOUT:SOURCE
(Note 3)
-2.0
-0.5
mA
±6
%
Output-Current Full-Scale
Accuracy
I OUT:FS
+25°C, VCC = 4.0V; using 0.1% RFS
resistor (Note 4)
VOUT0 = VOUT1 = 1.2V
Output-Current Temperature
Coefficient
I OUT:TC
(Note 5)
2
MIN
±75
_______________________________________________________________________________________
ppm/°C
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
DS4412
OUTPUT CURRENT CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output-Current Variation due to
Power-Supply Change
DC source
+0.36
DC sink
+0.12
Output-Current Variation due to
Output Voltage Change
DC source, V OUT measured at 1.2V
DC sink, VOUT measured at 1.2V
-0.02
Output Leakage Current at Zero
Current Setting
UNITS
%/V
%/V
+0.12
-1
I ZERO
MAX
+1
μA
Output-Current Differential
Linearity
DNL
(Note 6)
0.5
LSB
Output-Current Integral Linearity
INL
(Note 7)
1
LSB
MAX
UNITS
400
kHz
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
(Note 8)
MIN
0
TYP
SCL Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
µs
Low Period of SCL
tLOW
1.3
µs
High Period of SCL
tHIGH
0.6
µs
Data Hold Time
tDH:DAT
0
Data Setup Time
tSU:DAT
100
0.9
µs
ns
START Setup Time
tSU:STA
0.6
µs
SDA and SCL Rise Time
tR
(Note 9)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 9)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
SDA and SCL Capacitive Loading
CB
0.6
(Note 9)
µs
400
pF
Note 1: All voltages with respect to ground, currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs driven to well-defined logic levels. SDA and
SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current includes ICC + 2.5 x (IRFS0 + IRFS0).
Note 3: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Input resistors RFS must be between 2.25kΩ and 9.0kΩ to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 15.
Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 8: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 9: CB—total capacitance of one bus line in pF.
_______________________________________________________________________________________
3
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
DS4412
Pin Description
NAME
PIN
FUNCTION
SDA
1
I2C Serial Data. Input/output for I2C data.
SCL
2
I2C Serial Clock. Input for I2C clock.
FS1
3
FS0
5
Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current
for each output. FS0 controls OUT0, FS1 controls OUT1.
GND
4
Ground
OUT0
6
OUT1
7
Current Outputs. Sinks or sources the current determined by the register settings and the
resistance connected to FS0 and FS1.
VCC
8
Power Supply
Typical Operating Characteristics
(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
0.3
0.2
0.20
VCC = 3.3V
0.15
VCC = 2.7V
3.7
4.2
4.7
20
40
60
0
80
1
2
3
4
VOLTCO (SINK)
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
-2.3
-2.4
-2.5
2
VOUT (V)
3
4
70
60
+25°C TO +85°C
50
40
30
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT-SOURCE RANGE.
20
10
80
5
DS4412 toc06
+25°C TO -40°C
TEMPERATURE COEFFICIENT (°C/ppm)
DS4412 toc04
-2.2
80
DS4412 toc05
VOUT (V)
-2.1
1
0
TEMPERATURE (°C)
2.2kΩ LOAD ON FS0 AND FS1
0
-20
SUPPLY VOLTAGE (V)
-2.0
IOUT (mA)
2.0
-40
5.2
TEMPERATURE COEFFICIENT (°C/ppm)
3.2
2.2
2.1
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 AND FS1.
0
2.7
2.3
0.10
0.05
4
2.4
0.25
0.1
0
2.2kΩ LOAD ON FS0 AND FS1
IOUT (mA)
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 AND FS1.
2.5
DS4412 toc02
VCC = 5.0V
0.30
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.4
VOLTCO (SOURCE)
0.35
DS4412 toc01
0.5
DS4412 toc03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
70
60
+25°C TO -40°C
50
40
+25°C TO +85°C
30
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT-SOURCE RANGE.
20
10
0
0
0
5
10
SETTING (DEC)
15
0
5
10
SETTING (DEC)
_______________________________________________________________________________________
15
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
DIFFERENTIAL LINEARITY
DS4412 toc07
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT SOURCE AND SINK RANGE
0.7500
1.0
0.6
0.5000
0.4
0.2500
0.2
DNL (LSB)
INL (LSB)
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT SOURCE AND SINK RANGE
0.8
DS4412 toc08
INTEGRAL LINEARITY
1.0000
0.0000
0
-0.2
-0.2500
-0.4
-0.5000
-0.6
-0.7500
-0.8
-1.0000
-1.0
0
5
15
10
0
5
SETTING (DEC)
10
15
SETTING (DEC)
Block Diagram
SDA SCL
VCC
I2C-COMPATIBLE
SERIAL INTERFACE
DS4412
VCC
F8h
F9h
SOURCE OR
SINK MODE
CURRENT
DAC0
GND
OUT0
FS0
RFS0
15 POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC1
FS1
OUT1
RFS1
_______________________________________________________________________________________
5
DS4412
Typical Operating Characteristics (continued)
(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
otherwise noted.)
DS4412
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
Detailed Description
The DS4412 contains two I 2 C adjustable-current
sources that are each capable of sinking and sourcing
current. Each output, OUT0 and OUT1, has 15 sink and
15 source settings that are programmed through the
I2C interface. The full-scale ranges and corresponding
step sizes of the outputs are determined by external
resistors, connected to pins FS0 and FS1, which can
adjust the output currents over a 4:1 range. The formula
to determine the positive and negative full-scale current
ranges for each of the four outputs is given by:
RFS = (VRFS / IFS) x (15 / 1.974)
where V RFS is the R FS voltage (see DC Electrical
Characteristics), and RFS is the external resistor value.
On power-up, the DS4412 outputs zero current. This is
done to prevent it from sinking or sourcing an incorrect
current before the system host controller has had a
chance to modify the device’s setting.
As a source for biasing instrumentation or other circuits, the DS4412 provides a simple and inexpensive
current source with an I2C interface for control. The
adjustable full-scale range allows the application to get
the most out of its 4-bit sink or source resolution.
When used in adjustable power-supply applications
(see Typical Operating Circuit), the DS4412 does not
affect the initial power-up supply voltage because it
defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating
point. Using the external resistor, RFS, to set the output
current range, the DS4412 provides some flexibility for
adjusting the range over which the power supply can
be controlled or margined.
Memory Organization
The DS4412’s current sources are controlled by writing
to the memory addresses in Table 1.
Table 1. Memory Addresses
MEMORY ADDRESS
(HEXADECIMAL)
CURRENT SOURCE
0xF8
OUT0
0xF9
OUT1
The format of each output control register is given by:
MSB
LSB
S
X
X
X
D3
D2
D1
D0
Where:
BIT
NAME
S
Sign Bit
X
DX
FUNCTION
POWER-ON
DEFAULT
Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.
Reserved Reserved.
4-Bit Data Word Controlling
DAC Output. Setting 0000b
Data
outputs zero current
regardless of the state of the
sign bit.
0b
XXX
0000b
Example: RFS0 = 4.8kΩ and register 0xF8h is written to
a value of 0x8Ah. Calculate the output current.
IFS = (0.607V / 4.8kΩ) x (15 / 1.974) = 949.85µA
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position Ah (10 decimal). The magnitude of the output current is equal to:
949.85µA x (10 / 15) = 633.23µA
6
_______________________________________________________________________________________
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
I2C Slave Address
The DS4412’s slave address is 90h.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 1 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
starts are commonly used during read operations to
identify a specific memory address to begin a data
transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for
applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup and hold time requirements (Figure 1).
Data is shifted into the device during the rising edge
of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 1) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a one during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 2). An
ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a
SDA
tBUF
tF
tHD:STA
tLOW
tSP
SCL
tHIGH
tHD:STA
tHD:DAT
STOP
tSU:STA
tR
START
tSU:STO
tSU:DAT
REPEATED
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 1. I2C Timing Diagram
_______________________________________________________________________________________
7
DS4412
I2C Serial Interface Description
DS4412
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
0
0
1
0
0
0
R/W
MSB
SLAVE
ACK
b7
READ/
WRITE
SLAVE
ADDRESS
LSB
b6
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
REGISTER/MEMORY ADDRESS
b5
b4
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS
90h
A) SINGLE BYTE WRITE
-WRITE RESISTOR
F9h TO 00h
90h
B) SINGLE BYTE READ
-READ RESISTOR F8h
F9h
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1
ACK
SLAVE 0 0 0 0 0 0 0 0
ACK
F8h
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE
ACK
ACK
SLAVE
ACK
STOP
90h
REPEATED
START
1 0 0 1 0 0 0 1 SLAVE
ACK
DATA
MASTER
NACK
STOP
Figure 2. I2C Communication Examples
read sequence or as an indication that the device is
not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit-write definition,
and the acknowledgement is read using the bit-read
definition.
Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit read definition above, and the
master transmits an ACK using the bit write definition to receive additional data bytes. The master
must NACK the last byte read to terminated communication so the slave will return control of SDA to the
master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4412’s slave address is 90h.
8
When the R/W bit is 0 (such as in 90h), the master is
indicating it will write data to the slave. If R/W = 1
(91h in this case), the master is indicating it wants to
read from the slave. If an incorrect slave address is
written, the DS4412 assumes the master is communicating with another I2C device and ignores the
communication until the next START condition is
sent.
Memory Address: During an I2C write operation,
the master must transmit a memory address to identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
I2C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and generate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
_______________________________________________________________________________________
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
Where:
IR0B =
Example Calculation
for an Adjustable Power Supply
In this example, the Typical Operating Circuit is used
as a base to create Figure 3, a 2.0V voltage supply with
±20% margin. The adjustable power supply has a
DC-DC converter output voltage, VOUT, of 2.0V and a
DC-DC converter feedback voltage, VFB, of 0.8V. To
determine the relationship of R0A and R0B, we start with
the equation:
VFB =
R 0B
× VOUT
R 0 A + R 0B
Substituting VFB = 0.8V and VOUT = 2.0V, the relationship between R0A and R0B is determined to be:
R0A = 1.5 x R0B
IOUT0 is chosen to be 1mA (midrange source/sink current for the DS4412). Summing the currents into the
feedback node, we have the following
I OUT0 = IR0B − IR0 A
4.7kΩ
IR0 A =
VOUT − VFB
R 0A
To create a 20% margin in the supply voltage, the value
of VOUT is set to 2.4V. With these values in place, R0B is
calculated to be 267Ω, and R0A is calculated to be 400Ω.
The current DAC in this configuration allows the output
voltage to be moved linearly from 1.6V to 2.4V using 15
settings. This corresponds to a resolution of 25.8mV/step.
VCC Decoupling
To achieve the best results when using the DS4412,
decouple the power supply with a 0.01µF or 0.1µF
capacitor. Use a high-quality ceramic surface-mount
capacitor if possible. Surface-mount components minimize lead inductance, which improves performance,
and ceramic capacitors tend to have adequate highfrequency response for decoupling applications.
VOUT = 2.0V
OUT
VCC
SDA
SCL
DC-DC
CONVERTER
DS4412
VFB
R 0B
And
VCC
4.7kΩ
DS4412
Applications Information
IR0A
R0A = 400Ω
FB
OUT0
VFB = 0.8V
IR0B
GND
R0B = 267Ω
FS0
IOUT0
RFS0 = 4.612kΩ
Figure 3. Example Application Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 µSOP
U8+1
21-0036
_______________________________________________________________________________________
9
DS4412
Dual-Channel, I2C Adjustable
Sink/Source Current DAC
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/07
1
10/08
DESCRIPTION
PAGES
CHANGED
Initial release.
—
Added the I/O capacitance (CI/O) parameter to the DC Electrical Characteristics
table.
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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