LINER LTC2461IMSPBF Ultra-tiny, 16-bit iâ²c î î£ adcs with 10ppm/â°c max precision reference Datasheet

LTC2461/LTC2463
Ultra-Tiny, 16-Bit I2C ΔΣ
ADCs with 10ppm/°C Max
Precision Reference
DESCRIPTION
FEATURES
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The LTC®2461/LTC2463 are ultra tiny, 16-Bit analog-todigital converters with an integrated precision reference.
They use a single 2.7V to 5.5V supply and communicate
through an I2C Interface. The LTC2461 is single-ended
with a 0V to 1.25V input range and the LTC2463 is differential with a 1.25V input range. Both ADCs include a
1.25V integrated reference with 2ppm/°C drift performance and 0.1% initial accuracy. The converters are
available in a 12-pin 3mm × 3mm DFN package or an
MSOP-12 package. They include an integrated oscillator
and perform conversions with no latency for multiplexed
applications. The LTC2461/LTC2463 include a proprietary
input sampling scheme that reduces the average input
current several orders of magnitude when compared to
conventional delta sigma converters.
16-Bit Resolution, No Missing Codes
Internal Reference, High Accuracy 10ppm/°C (Max)
Single-Ended (LTC2461) or Differential (LTC2463)
2LSB Offset Error (Typ)
0.01% Gain Error (Typ)
60 Conversions Per Second
Single Conversion Settling Time for Multiplexed
Applications
1.5mA Supply Current
200nA Sleep Current
Internal Oscillator—No External Components
Required
2-Wire I2C Interface with Two Addresses Plus One
Global Address for Synchronization
Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP
Packages
Following a single conversion, the LTC2461/LTC2463
automatically power down the converter and can also be
configured to power down the reference. When both the
ADC and reference are powered down, the supply current
is reduced to 200nA.
APPLICATIONS
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System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Data Acquisition
Embedded ADC Upgrades
The LTC2461/LTC2463 can sample at 60 conversions per
second and, due to the very large oversampling ratio,
have extremely relaxed antialiasing requirements. Both
include continuous internal offset and fullscale calibration
algorithms which are transparent to the user, ensuring accuracy over time and the operating temperature range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
VREF vs Temperature
1.2520
0.1μF
0.1μF
0.1μF
10k
REFOUT
SCL
LTC2463
IN–
10k
0.1μF
R
SDA
REF–
10μF
COMP VCC
IN+
10k
0.1μF
A0
I 2C
INTERFACE
GND
REFERENCE OUTPUT VOLTAGE (V)
2.7V TO 5.5V
1.2515
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
24613 TA01a
1.2480
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
24613 TA01b
24613f
1
LTC2461/LTC2463
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(VIN+, VIN –, VIN, VREF –,
VCOMP, VREFOUT) ...........................–0.3V to (VCC + 0.3V)
Digital Voltage
(VSDA, VSCL, VA0) ..........................–0.3V to (VCC + 0.3V)
Storage Temperature Range .................. –65°C to 150°C
Operating Temperature Range
LTC2461C/LTC2463C ............................... 0°C to 70°C
LTC2461I/LTC2463I .............................–40°C to 85°C
PIN CONFIGURATION
LTC2463
LTC2463
TOP VIEW
REFOUT
1
12 VCC
COMP
2
11 GND
A0
GND
4
SCL
5
8 REF–
SDA
6
7 GND
10
1
2
3
4
5
6
REFOUT
COMP
A0
GND
SCL
SDA
IN–
3
13
TOP VIEW
9 IN+
12
11
10
9
8
7
VCC
GND
IN–
IN+
REF–
GND
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 135°C/W
DD PACKAGE
12-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13)
LTC2461
LTC2461
TOP VIEW
REFOUT
1
12 VCC
COMP
2
11 GND
10 GND
A0
3
GND
4
SCL
5
8 REF–
SDA
6
7 GND
13
TOP VIEW
REFOUT
COMP
A0
GND
SCL
SDA
9 IN
1
2
3
4
5
6
12
11
10
9
8
7
VCC
GND
GND
IN
REF–
GND
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 135°C/W
DD PACKAGE
12-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2461CDD#PBF
LTC2461CDD#TRPBF
LFGF
12-Lead Plastic (3mm × 3mm) DFN
0°C to 70°C
LTC2461IDD#PBF
LTC2461IDD#TRPBF
LFGF
12-Lead Plastic (3mm × 3mm) DFN
–40°C to 85°C
LTC2461CMS#PBF
LTC2461CMS#TRPBF
2461
12-Lead Plastic MSOP
0°C to 70°C
LTC2461IMS#PBF
LTC2461IMS#TRPBF
2461
12-Lead Plastic MSOP
–40°C to 85°C
LTC2463CDD#PBF
LTC2463CDD#TRPBF
LFGG
12-Lead Plastic (3mm × 3mm) DFN
0°C to 70°C
LTC2463IDD#PBF
LTC2463IDD#TRPBF
LFGG
12-Lead Plastic (3mm × 3mm) DFN
–40°C to 85°C
LTC2463CMS#PBF
LTC2463CMS#TRPBF
2463
12-Lead Plastic MSOP
0°C to 70°C
LTC2463IMS#PBF
LTC2463IMS#TRPBF
2463
12-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
24613f
2
LTC2461/LTC2463
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
(Note 3)
l
Integral Nonlinearity
(Note 4)
l
1
8
LSB
Offset Error
LTC2461, 30Hz, LTC2463
LTC2461, 60Hz
l
2
5
15
LSB
LSB
16
Offset Error Drift
Bits
0.02
LSB/°C
Gain Error
Includes Contributions of ADC and Internal Reference
l
±0.01
±0.25
% of FS
Gain Error Drift
Includes Contributions of ADC and Internal Reference
C-Grade
I-Grade
l
±2
±5
±10
ppm/°C
ppm/°C
Transition Noise
2.2
μVRMS
Power Supply Rejection DC
80
dB
ANALOG INPUTS
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
VIN
Positive Input Voltage Range
LTC2463
l
VIN–
Negative Input Voltage Range
LTC2463
l
VIN
Input Voltage Range
LTC2461
l
VOR+, VUR+
VOR–, VUR–
Overrange/Underrange Voltage, IN+
VIN
– = 0.625V (See Figure 3)
8
LSB
Overrange/Underrange Voltage, IN–
VIN+ = 0.625V (See Figure 3)
8
LSB
CIN
IN+, IN–, IN Sampling Capacitance
+
IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2463)
IN DC Leakage Current (LTC2461)
MIN
TYP
MAX
UNITS
0
VREF
V
0
VREF
V
0
VREF
V
0.35
VIN = GND or VCC (Note 8)
VIN = GND or VCC (Note 8)
pF
l
l
–10
–10
1
1
1.247
1.25
1.253
±2
±5
±10
ICONV
Input Sampling Current (Note 5)
VREF
REFOUT Output Voltage
l
REFOUT Voltage Temperature Coefficient (Note 9)
C-Grade
I-Grade
l
10
10
nA
nA
50
Reference Line Regulation
2.7V ≤ VCC ≤ 5.5V
Reference Short Circuit Current
VCC = 5.5, Forcing REFOUT to GND
l
l
nA
V
ppm/°C
ppm/°C
–90
dB
35
mA
COMP Pin Short Circuit Current
VCC = 5.5, Forcing REFOUT to GND
Reference Load Regulation
2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing
3.5
200
mV/mA
μA
Reference Output Noise Density
CCOMP= 0.1μF, CREFOUT = 0.1μF, At f = 1kHz
30
nV/√Hz
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC
Supply Voltage
l
ICC
Supply Current
Conversion
Nap
Sleep
l
l
l
TYP
2.7
MAX
5.5
1.5
800
0.2
2.5
1500
2
UNITS
V
mA
μA
μA
24613f
3
LTC2461/LTC2463
I2C INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
l
MIN
VIL
Low Level Input Voltage
l
II
Digital Input Current
l
–10
VHYS
Hysteresis of Schmidt Trigger Inputs
(Note 3)
l
0.05VCC
VOL
Low Level Output Voltage (SDA)
I = 3mA
l
0.4
V
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
1
μA
CI
Capacitance for Each I/O Pin
l
CB
Capacitance Load for Each Bus Line
l
VIH(A0)
High Level Input Voltage for Address Pin
l
VIL(A0)
Low Level Input Voltage for Address Pin
l
TYP
MAX
UNITS
0.7VCC
V
0.3VCC
V
10
μA
V
10
pF
400
pF
0.95VCC
V
0.05VCC
V
I2C TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tCONV
Conversion Time
l
13
16.6
23
ms
fSCL
SCL Clock Frequency
l
0
tHD(SDA,STA)
Hold Time (Repeated) START Condition
l
0.6
400
kHz
μs
tLOW
LOW Period of the SCL Pin
l
1.3
μs
tHIGH
HIGH Period of the SCL Pin
l
0.6
μs
tSU(STA)
Set-Up Time for a Repeated START Condition
l
0.6
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time for SDA, SCL Signals
(Note 6)
l
20 + 0.1CB
300
(Note 6)
l
20 + 0.1CB
300
μs
μs
0.9
ns
ns
tf
Fall Time for SDA, SCL Signals
tSU(STO)
Set-Up Time for STOP Condition
l
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
μs
tOF
Output Fall Time VIHMIN to VILMAX
l
20 + 0.1CB
tSP
Input Spike Suppression
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
Note 3: Guaranteed by design, not subject to test.
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Bus Load CB = 10pF to
400pF (Note 6)
l
ns
250
ns
50
ns
Note 5: Input sampling current is the average input current drawn from
the input sampling network while the LTC2461/LTC2463 are converting.
Note 6: CB = capacitance of one bus line in pF.
Note 7: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 8: A positive current is flowing into the DUT pin.
Note 9: Voltage temperature coefficient is calculated by dividing the
maximum change in output voltage by the specified temperature range.
24613f
4
LTC2461/LTC2463
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (VCC = 5.5V)
Integral Nonlinearity (VCC = 2.7V)
3
TA = –45°C, 25°C, 90°C
TA = –45°C, 25°C, 90°C
2
1
1
1
0
INL (LSB)
2
0
–1
–1
–2
–2
–2
0.25
0.75
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
–3
–1.25
1.25
0.25
0.75
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
24613 G01
Offset Error vs Temperature
ADC Gain Error vs Temperature
Transition Noise vs Temperature
9
TRANSITION NOISE RMS (μV)
ADC GAIN ERROR (LSB)
20
VCC = 4.1V
1
VCC = 2.7V
0
10
VCC = 5.5V
VCC = 5.5V
2
–1
–2
15
10
VCC = 4.1V
5
–3
VCC = 2.7V
–4
–30
50
–10 10
30
TEMPERATURE (°C)
70
0
–50
90
–25
0
25
50
TEMPERATURE (°C)
Conversion Mode Power Supply
Current vs Temperature
75
1.9
VCC = 4.1V
1.5
VCC = 2.7V
SLEEP CURRENT (nA)
VCC = 5.5V
1.6
VCC = 5.5V
250
200
150
VCC = 4.1V
100
50
1.1
–30
50
–10 10
30
TEMPERATURE (°C)
70
90
24613 G07
VCC = 2.7V
3
2
VCC = 5.5V
–30
50
–10 10
30
TEMPERATURE (°C)
0
–50
VCC = 2.7V
–30
50
–10 10
30
TEMPERATURE (°C)
70
90
24613 G06
VREF vs Temperature
1.2
1.0
–50
4
1.2508
300
1.3
5
0
–50
100
350
1.4
6
Sleep Mode Power Supply
Current vs Temperature
2.0
1.7
7
24613 G05
24613 G04
1.8
8
1
REFERENCE OUTPUT VOLTAGE (V)
–5
–50
5 25 45 65 85 105 125
TEMPERATURE (°C)
24613 G03
25
3
OFFSET ERROR (LSB)
–3
–55 –35 –15
1.25
24613 G02
5
4
VCC = 5.5V, 4.1V, 2.7V
0
–1
–3
–1.25
CONVERSION CURRENT (mA)
INL vs Temperature
3
2
INL (LSB)
INL (LSB)
3
(TA = 25°C, unless otherwise noted)
70
90
24613 G08
VCC = 5V
1.2507
1.2506
1.2505
1.2504
1.2503
1.2502
–50
–30
50
–10 10
30
TEMPERATURE (°C)
70
90
24613 G09
24613f
5
LTC2461/LTC2463
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Rejection
vs Frequency at VCC
Conversion Time vs Temperature
TA = 25°C
VCC = 4.1V
CONVERSION TIME (ms)
REJECTION (dB)
–20
–40
–60
–80
–100
–120
VREF vs VCC
21
1.24892
20
1.24891
VCC = 5V, 4.1V, 3V
18
17
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
24613 G10
1.24889
1.24888
1.24887
16
1.24886
15
1
TA = 25°C
1.24890
19
VREF (V)
0
(TA = 25°C, unless otherwise noted)
14
–50
1.24885
–25
25
50
0
TEMPERATURE (°C)
75
100
24613 G11
1.24884
2.0
2.5
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
24613 G12
24613f
6
LTC2461/LTC2463
PIN FUNCTIONS
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,
this voltage sets the fullscale input range of the ADC. For
noise and reference stability connect to a 0.1μF capacitor
tied to GND. This capacitor value must be less than or
equal to the capacitor tied to the reference compensation
pin (COMP). REFOUT cannot be overdriven by an external
reference. For applications that require an input range
greater than 0V to 1.25V, please refer to the LTC2451/
LTC2453.
COMP (Pin 2): Internal Reference Compensation Pin. For
low noise and reference stability, tie a 0.1μF capacitor to
GND.
A0 (Pin 3): Chip Address Control Pin. The A0 pin can be
tied to GND or VCC. If A0 is tied to GND, the LTC2461/
LTC2463 I2C address is 0010100. If A0 is tied to VCC, the
LTC2461/LTC2463 I2C address is 1010100.
GND (Pins 4, 7, 11): Ground. Connect directly to the
ground plane through a low impedance connection.
I2C
Interface. The
SCL (Pin 5): Serial Clock Input of the
LTC2461/LTC2463 can only act as a slave and the SCL pin
only accepts external serial clock. Data is shifted into the
SDA pin on the rising edges of SCL and output through
the SDA pin on the falling edges of SCL.
SDA (Pin 6): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin.
The pin is high impedance unless the LTC2461/LTC2463
is in the data output mode. While the LTC2461/LTC2463
is in the data output mode, SDA is an open drain pull
down (which requires an external 1.7k pull-up resistor
to VCC).
REF– (Pin 8): Negative Reference Input to the ADC. The
voltage on this pin sets the zero input to the ADC. This
pin should tie directly to ground or the ground sense of
the input sensor.
IN+ (LTC2463), IN (LTC2461) (Pin 9): Positive input voltage for the LTC2463 differential device. ADC input for the
LTC2461 single-ended device.
IN– (LTC2463), GND (LTC2461) (Pin 10): Negative input
voltage for the LTC2463 differential device. GND for the
LTC2461 single-ended device.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10μF capacitor in parallel with a low-series-inductance
0.1μF capacitor located as close to pin 12 as possible.
Exposed Pad (Pin 13 – DFN Package): Ground. Connect
directly to the ground plane through a low impedance
connection.
24613f
7
LTC2461/LTC2463
BLOCK DIAGRAM
1
9
IN+
(IN)
IN–
(GND)
COMP
INTERNAL
REFERENCE
$3 A/D
CONVERTER
12
VCC
A0
I2C
INTERFACE
SCL
SDA
DECIMATING
SINC FILTER
–
10
2
REFOUT
3
5
6
$3 A/D
CONVERTER
INTERNAL
OSCILLATOR
8
REF–
4, 7, 11, 13 (DD PACKAGE)
GND
24613 BD
( ) PARENTHESIS INDICATE LTC2461
Figure 1. Functional Block Diagram
APPLICATIONS INFORMATION
CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
The LTC2461/LTC2463 are low power, delta sigma, analog to digital converters with a simple I2C interface (see
Figure 1). The LTC2463 has a fully differential input while
the LTC2461 is single-ended. Both are pin and software
compatible. Their operation is composed of three distinct
states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT
(see Figure 2). The operation begins with the CONVERT
state. Once the conversion is finished, the converter automatically powers down (NAP) or, under user control, both
the converter and reference are powered down (SLEEP).
The conversion result is held in a static register while the
device is in this state. The cycle concludes with the DATA
INPUT/OUTPUT state. Once all 16-bits are read the device
begins a new conversion.
The CONVERT state duration is determined by the LTC2461/
LTC2463 conversion time (nominally 16.6 milliseconds).
Once started, this operation can not be aborted except by a
low power supply condition (VCC < 2.1V) which generates
an internal power-on reset signal.
After the completion of a conversion, the LTC2461/LTC2463
enters the SLEEP/NAP state and remains there until a valid
CONVERT
SLEEP/NAP
NO
READ/WRITE
ACKNOWLEDGE
YES
DATA INPUT/OUTPUT
NO
STOP
OR
READ 16 BITS
YES
24613 F02
Figure 2. LTC2461/LTC2463 State Transition Diagram
read/write is acknowledged. Following this condition, the
ADC transitions into the DATA INPUT/OUTPUT state.
While in the SLEEP/NAP state, the LTC2461/LTC2463’s
converters are powered down. This reduces the supply
24613f
8
LTC2461/LTC2463
APPLICATIONS INFORMATION
current by approximately 50%. While in the Nap state,
the reference remains powered up. To power down the
reference in addition to the converter, the user can select
the SLEEP mode during the DATA INPUT/OUTPUT state.
Once the next conversion is complete, SLEEP state is
entered and power is reduced to 200nA. The reference
is powered up once a valid read/write is acknowledged.
The reference startup time is 12ms (if the reference and
compensation capacitor values are both 0.1μF).
Power-Up Sequence
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
The LTC2461/LTC2463 perform offset calibrations every
conversion cycle. This calibration is transparent to the
user and has no effect upon the cyclic operation described
previously. The advantage of continuous calibration is
stability of the ADC performance with respect to time and
temperature.
The LTC2461/LTC2463 include a proprietary input sampling
scheme that reduces the average input current by several
orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks
to interface directly to the LTC2461/LTC2463. Since the
average input sampling current is 50nA, an external RC
lowpass filter using 1kΩ and 0.1μF results in <1LSB
additional error. Additionally, there is negligible leakage
current between IN+ and IN–.
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2461/LTC2463
start a conversion cycle and follow the succession of states
shown in Figure 2. The reference startup time following a
POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conversion following power-up will be invalid since the reference
voltage has not completely settled. The first conversion
following power up can be discarded using the data abort
command or simply read and ignored. The following conversions are accurate to the device specifications.
Ignoring offset and full-scale errors, the LTC2461 will
theoretically output an “all zero” digital result when the
input is at ground (a zero scale input) and an “all one”
digital result when the input is at VREF (VREFOUT = 1.25V).
In an underrange condition, for all input voltages below
zero scale, the converter will generate the output code 0. In
an overrange condition, for all input voltages greater than
VREF, the converter will generate the output code 65535.
For applications that require an input range greater than
0V to 1.25V, please refer to the LTC2451.
Ease of Use
Input Voltage Range (LTC2463)
The LTC2461/LTC2463 data output has no latency, filter
settling delay or redundant results associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog input voltages requires no
special actions.
As mentioned in the Output Data Format section, the output
code is given as 32768 • (VIN+ – VIN–)/VREF + 32768. For
(VIN+ – VIN–) ≥ VREF, the output code is clamped at 65535
(all ones). For (VIN+ – VIN–) ≤ –VREF, the output code is
clamped at 0 (all zeroes).
Input Voltage Range (LTC2461)
The LTC2463 includes a proprietary architecture that
can, typically, digitize each input up to 8 LSBs above
24613f
9
LTC2461/LTC2463
APPLICATIONS INFORMATION
VREF and below GND, if the differential input is within
±VREF. As an example (Figure 3), if the user desires to
measure a signal slightly below ground, the user could
set VIN– = GND. If VIN+ = GND, the output code would be
approximately 32768. If VIN+ = GND – 8LSB = –0.305mV,
the output code would be approximately 32760. For applications that require an input range greater than ±1.25V,
please refer to the LTC2453.
20
16
12
OUTPUT CODE
8
4
0
–4
SIGNALS
BELOW
GND
–8
–12
–16
–20
–0.001 –0.005
0.005
0
VIN+/VREF+
0.001
0.0015
24613 F03
Figure 3. Output Code vs VIN+ with VIN– = 0 (LTC2463)
I2C INTERFACE
The LTC2461/LTC2463 communicate through an I2C interface. The I2C interface is a 2-wire open-drain interface
supporting multiple devices and masters on a single bus.
The connected devices can only pull the data line (SDA)
LOW and can never drive it HIGH. SDA must be externally
connected to the supply through a pull-up resistor. When
the data line is free, it is HIGH. Data on the I2C bus can be
transferred at rates up to 100kbits/s in the Standard-Mode
and up to 400kbits/s in the Fast-Mode.
Upon entering the DATA INPUT/OUTPUT state, SDA outputs
the sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDA output pin under the control of the SCL input pin.
There is no latency in generating this data and the result
corresponds to the last completed conversion. A new bit
of data appears at the SDA pin following each falling edge
detected at the SCL input pin and appears from MSB to LSB.
The user can reliably latch this data on every rising edge
of the external serial clock signal driving the SCL pin.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or
1010100 (if A0 is tied to VCC).
The LTC2461/LTC2463 can only be addressed as a slave.
It can only transmit the last conversion result. The serial
clock line, SCL, is always an input to the LTC2461/LTC2463
and the serial data line SDA is bidirectional. Figure 4 shows
the definition of the I2C timing.
SDA
tf
tLOW
tSU(DAT)
tr
tf
tHD(SDA)
tSP
tr
tBUF
SCL
tHD(STA)
S
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
Sr
P
S
24613 F04
Figure 4. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
24613f
10
LTC2461/LTC2463
APPLICATIONS INFORMATION
The START and STOP Conditions
Output Data Format
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2461/
LTC2463’s address (0010100 or 1010100, depending on the
state of the pin A0) the ADC is selected. When the device is
addressed during the conversion state, it does not accept
the request and issues a NAK by leaving the SDA line HIGH.
If the conversion is complete, the LTC2461/LTC2463 issue
an ACK by pulling the SDA line LOW.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Following the ACK, the LTC2461/LTC2463 can output data.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 5a).
The DATA INPUT/OUTPUT state is concluded once all 16
data bits have been read or after a STOP condition.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
1
7
8
9
The LTC2463 (differential input) output code is given by
32768 • (VIN+ – VIN–)/VREF + 32768. The first bit output
by the LTC2463, D15, is the MSB, which is 1 for VIN+ ≥
VIN– and 0 for VIN+ < VIN–. This bit is followed by successively less significant bits (D14, D13, …) until the LSB is
output by the LTC2463, see Table 1.
1
2
3
8
D15
D14
D13
D8
9
1
2
D7
D6
3
8
9
SCL
SDA
7-BIT
ADDRESS
R
MSB
START BY
MASTER
SLEEP
ACK BY
LTC2461/LTC2463
D5
D0
LSB
ACK BY
MASTER
DATA OUTPUT
NACK BY
MASTER
CONVERSION
24613 F05a
Figure 5a. Read Sequence Timing Diagram
24613f
11
LTC2461/LTC2463
APPLICATIONS INFORMATION
The LTC2461 (single-ended input) output code is a direct
binary encoded result, see Table 1.
The speed bit (SPD) is only used by the LTC2461. In the
default mode, SPD = 0, the output rate is 60Hz and continuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration
is performed and the output rate is reduced to 30Hz. The
LTC2463 data output rate is always 60Hz and background
offset calibration is performed (SPD = don’t care).
Data Input Format
After a START condition, the master sends a 7-bit address followed by a read/write request (R/W) bit. The
R/W bit is 0 for a write. The data input word is 4 bits long
and consists of two enable bits (EN1 and EN2) and two
programming bits (SPD and SLP), see Figure 5b. EN1 is
applied to the first rising edge of SCL after a valid write
address is acknowledged. Programming is enabled by
setting EN1 = 1 and EN2 = 0.
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
Table 1. LTC2461/LTC2463 Output Data Format
SINGLE ENDED INPUT VIN
(LTC2461)
DIFFERENTIAL INPUT VOLTAGE
VIN+ – VIN– (LTC2463)
D15
(MSB)
D14
D13
D12...D2
D1
D0
(LSB)
CORRESPONDING
DECIMAL VALUE
≥VREF
≥VREF
1
1
1
1
1
1
65535
VREF – 1LSB
VREF – 1LSB
1
1
1
1
1
0
65534
0.75 • VREF
0.5 • VREF
1
1
0
0
0
0
49152
0.75 • VREF – 1LSB
0.5 • VREF – 1LSB
1
0
1
1
1
1
49151
0.5 • VREF
0
1
0
0
0
0
0
32768
0.5 • VREF – 1LSB
–1LSB
0
1
1
1
1
1
32767
0.25 • VREF
–0.5 • VREF
0
1
0
0
0
0
16384
0.25 • VREF – 1LSB
–0.5 • VREF – 1LSB
0
0
1
1
1
1
16383
0
≤ –VREF
0
0
0
0
0
0
0
1
2
…
7
8
9
1
2
3
4
EN1
EN2
SPD
SLP
5
6
7
8
9
SCL
7-BIT ADDRESS
SDA
W
ACK BY
LTC2461/LTC2463
START BY
MASTER
SLEEP
ACK BY
LTC2461/LTC2463
DATA INPUT
24613 F03
Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463
24613f
12
LTC2461/LTC2463
APPLICATIONS INFORMATION
the next conversion is complete. It will remain powered
down until a valid address is acknowledged. The reference
startup time is approximately 12ms. In order to ensure a
stable reference for the following conversions, either the
data input/output time should be delayed 12ms after an
address acknowledge or the first conversion following a
reference start up should be discarded.
end of a read operation, a new conversion automatically
begins. At the conclusion of the conversion cycle, the next
result may be read using the method described above. If
the conversion cycle is not complete and a valid address
selects the device, the LTC2461/LTC2463 generate a NAK
signal indicating the conversion cycle is in progress. See
Figure 7a for an example state diagram.
OPERATION SEQUENCE
Discarding a Conversion Result and Initiating a New
Conversion
Continuous Read
It is possible to start a new conversion without reading
the old result, as shown in Figure 7b. Following a valid
7-bit address, a read request (R/W) bit, and a valid ACK,
a STOP command will start a new conversion.
Conversions from the LTC2461/LTC2463 can be continuously read, see Figure 6. The R/W is 1 for a read. At the
S
CONVERSION
7-BIT ADDRESS
(0010100 OR 1010100)
R
ACK
READ
P
DATA OUTPUT
SLEEP
S
7-BIT ADDRESS
(0010100 OR 1010100)
CONVERSION
READ
R ACK
P
DATA OUTPUT
SLEEP
CONVERSION
24613 F06
Figure 6. Consecutive Reading
I2C START
7-BIT ADDRESS:
0010100 OR 1010100
R/W
BIT LOW
WRITE INPUT
CONFIGURATION
(FIGURE 5b)
ACK
I2C STOP
CONVERT
CONVERSION
FINISHED
WRITE INPUT
CONFIGURATION
(FIGURE 5b)
FOR CYCLE N
I2C (REPEAT) START
R/W
BIT LOW
7-BIT ADDRESS:
0010100 OR 1010100
I2C START
CONVERSION
FINISHED
7-BIT ADDRESS:
0010100 OR 1010100
R/W
BIT HIGH
ACK
READ DATA FROM
CYCLE N-1
NAK
I2C STOP
CONVERT
24613 F07b
ACK
Figure 7a. I2C State Diagram
S
CONVERSION
7-BIT ADDRESS
(0010100 OR 1010100)
SLEEP
R
ACK READ (OPTIONAL)
DATA OUTPUT
P
CONVERSION
24613 F07a
Figure 7b. Start a New Conversion without Reading Old Conversion Result
24613f
13
LTC2461/LTC2463
APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY
The LTC2461/LTC2463 are designed to minimize the conversion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability
of this part, some simple precautions are desirable.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable.
The VCC pin should have two distinct connections: the
first to the decoupling capacitors described above, and
the second to the ground return for the power supply
voltage source.
Digital Signal Levels
REFOUT and COMP
Due to the nature of CMOS logic, it is advisable to keep
input digital signals near GND or VCC. Voltages in the range
of 0.5V to VCC – 0.5V may result in additional current
leakage from the part. Undershoot and overshoot should
also be minimized, particularly while the chip is converting. Excessive noise on the digital lines could degrade the
ADC performance.
The on-chip 1.25V precision reference is internally tied
to the LTC2461/LTC2463 converter’s reference input and
its output to the REFOUT pin. A 0.1μF capacitor should
be placed on the REFOUT pin. It is possible to reduce
this capacitor, but the transition noise increases. A 0.1μF
capacitor should also be placed on the COMP pin. This
pin is tied to an internal point in the reference and is used
for stability. In order for the reference to remain stable the
capacitor placed on the COMP pin must be greater than or
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2461/LTC2463
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless,
the very high accuracy of this converter is best preserved by careful low and high frequency power supply
decoupling.
A 0.1μF, high quality, ceramic capacitor in parallel with
a 10μF low ESR ceramic capacitor should be connected
between the VCC and GND pins, as close as possible to
the package. The 0.1μF capacitor should be placed closest
to the ADC package. It is also desirable to avoid any via
in the circuit path, starting from the converter VCC pin,
passing through these two decoupling capacitors, and
returning to the converter GND pin. The area encompassed
by this circuit path, as well as the path length, should be
minimized.
As shown in Figure 8, REF– is used as the negative reference voltage input to the ADC. This pin can be tied directly
to ground or Kelvined to sensor ground. In the case where
REF– is used as a sense input, it should be bypassed to
ground with a 0.1μF ceramic capacitor in parallel with a
10μF low ESR ceramic capacitor.
INTERNAL
REFERENCE
VCC
ILEAK
RSW
15k
(TYP)
REFOUT
ILEAK
VCC
ILEAK
RSW
15k
(TYP)
IN+
ILEAK
VCC
ILEAK
CEQ
0.35pF
(TYP)
RSW
15k
(TYP)
IN–
ILEAK
VCC
ILEAK
REF –
RSW
15k
(TYP)
24613 F08
ILEAK
Figure 8. LTC2461/LTC2463 Analog Input/Reference
Equivalent Circuit
24613f
14
LTC2461/LTC2463
APPLICATIONS INFORMATION
equal to the capacitor tied to the REFOUT pin. The REFOUT
pin should not be overridden by an external voltage. If
a reference voltage greater than 1.25V is required, the
LTC2451/LTC2453 should be used.
The internal reference has a corresponding start up
time depending on the size of the capacitors tied to the
REFOUT and COMP pins. This start up time is typically
12ms when 0.1μF capacitors are used. At initial power up,
the first conversion result can be aborted or ignored. At
the completion of this first conversion, the reference has
settled and all subsequent conversions are valid.
If the reference is put to sleep (program SLP = 1) the reference is powered down after the next conversion. This last
conversion result is valid. On a valid address acknowledge,
the reference is powered back up. In order to ensure the
reference output has settled before the next conversion,
the power up time can be extended by delaying the data
read 12ms. Once all 16 bits are read from the device, the
next conversion automatically begins. In the default operation, the reference remains powered up at the conclusion
of the conversion cycle.
Driving VIN+ and VIN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 9. The input signal VSIG is
connected to the ADC input pins (IN+ and IN–) through an
equivalent source resistance RS. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors CIN are also connected to the ADC input
pins. This capacitor is placed in parallel with the input
parasitic capacitance CPAR. This parasitic capacitance
includes elements from the printed circuit board (PCB)
and the associated input pin of the ADC. Depending on the
PCB layout, CPAR has typical values between 2pF and 15pF.
In addition, the equivalent circuit of Figure 9 includes the
converter equivalent internal resistor RSW and sampling
capacitor CEQ.
IN
(LTC2461)
RS
VSIG+
+
–
IN+
(LTC2463)
CIN
VCC
ILEAK
ILEAK
CEQ
0.35pF
(TYP)
CPAR
VCC
RS
VSIG–
+
–
IN–
(LTC2463)
CIN
CPAR
ILEAK
ILEAK
RSW
15k
(TYP)
ICONV
RSW
15k
(TYP)
CEQ
0.35pF
(TYP)
ICONV
24613 F09
Figure 9. LTC2461/LTC2463 Input Drive Equivalent Circuit
There are some immediate trade-offs in RS and CIN without
needing a full circuit analysis. Increasing RS and CIN can
give the following benefits:
1) Due to the LTC2461/LTC2463’s input sampling algorithm, the input current drawn by IN+, IN– or IN over
a conversion cycle is typically 50nA. A high RS • CIN
attenuates the high frequency components of the input
current, and RS values up to 1k result in <1LSB error.
2) The bandwidth from VSIG is reduced at the input pins
(IN+, IN– or IN). This bandwidth reduction isolates the
ADC from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenuated before they go back to the signal source.
4) A large CIN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing RS protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large RS • CIN should be for a given
application. Increasing RS beyond a given point increases
the voltage drop across RS due to the input current,
24613f
15
LTC2461/LTC2463
APPLICATIONS INFORMATION
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the RS • CIN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement CIN as
a high-quality 0.1μF ceramic capacitor and to set RS ≤ 1k.
This capacitor should be located as close as possible to
the actual IN+, IN– or IN package pin. Furthermore, the
area encompassed by this circuit path, as well as the path
length, should be minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split RS and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
Figure 10 shows the measured LTC2463 INL vs Input
Voltage as a function of RS value with an input capacitor
CIN = 0.1μF.
In some cases, RS can be increased above these guidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit τ = RS • CIN, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≈ 1/(2πRSCIN).
Finally, if the recommended choice for CIN is unacceptable
for the user’s specific application, an alternate strategy is to
eliminate CIN and minimize CPAR and RS. In practical terms,
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so
on. The resultant INL vs VIN is shown in Figure 11. The
measurements of Figure 11 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum
width input trace of about 1 inch length.
Signal Bandwidth, Transition Noise and Noise
Equivalent Input Bandwidth
The LTC2461/LTC2463 include a sinc1 type digital filter
with the first notch located at f0 = 60Hz. As such, the
3dB input signal bandwidth is 26.54Hz. The calculated
LTC2461/LTC2463 input signal attenuation vs frequency
over a wide frequency range is shown in Figure 12. The
calculated LTC2461/LTC2463 input signal attenuation vs
frequency at low frequencies is shown in Figure 13. The
converter noise level is about 2.2μVRMS and can be modeled by a white noise source connected at the input of a
noise-free converter.
On a related note, the LTC2463 uses two separate A/D
converters to digitize the positive and negative inputs.
Each of these A/D converters has 2.2μVRMS transition
noise. If one of the input voltages is within this small
transition noise band, then the output will fluctuate one
bit, regardless of the value of the other input voltage. If
both of the input voltages are within their transition noise
bands, the output can fluctuate 2 bits.
For a simple system noise analysis, the VIN drive circuit can
be modeled as a single-pole equivalent circuit characterized by a pole location fi and a noise spectral density ni.
If the converter has an unlimited bandwidth, or at least a
bandwidth substantially larger than fi, then the total noise
contribution of the external drive circuit would be:
Vn = ni π / 2 • fi
Then, the total system noise level can be estimated as
the square root of the sum of (Vn2) and the square of the
LTC2461/LTC2463 noise floor (~2.2μV2).
24613f
16
LTC2461/LTC2463
APPLICATIONS INFORMATION
3
3
CIN = 0.1μF
VCC = 5V
TA = 25°C
2
CIN = 0
VCC = 5V
TA = 25°C
2
RS = 10k
RS = 10k
1
RS = 1k
INL (LSB)
INL (LSB)
1
0
RS = 0k
RS = 0k
0
RS = 1k
–1
–1
–2
–2
–3
–1.25
0.25
0.75
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
–3
–1.25
1.25
24613 F10
INPUT SIGNAL ATTENUATION (dB)
0
VCC = 5V
TA = 25°C
–20
–40
–60
–80
1.25
24613 F11
Figure 11. Measured INL vs Input Voltage (CIN = 0)
0
INPUT SIGNAL ATTENUATIOIN (dB)
Figure 10. Measured INL vs Input Voltage (CIN = 0.1μF)
0.25
0.75
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
VCC = 5V
TA = 25°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
–100
0
2.5
5.0
7.5
1.00
1.25
1.50
INPUT SIGNAL FREQUENCY (MHz)
24613 F12
Figure 12. LTC2463 Input Signal Attentuation vs Frequency
–50
0
60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (Hz)
24613 F13
Figure 13. LTC2463 Input Signal Attenuation
vs Frequency (Low Frequencies)
24613f
17
LTC2461/LTC2463
PACKAGE DESCRIPTION
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
2.38 ±0.05
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
7
0.40 ± 0.10
12
2.38 ±0.10
1.65 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
6
0.200 REF
1
0.23 ± 0.05
0.45 BSC
0.75 ±0.05
2.25 REF
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
24613f
18
LTC2461/LTC2463
PACKAGE DESCRIPTION
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 p 0.038
(.0165 p .0015)
TYP
12 11 10 9 8 7
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0o – 6o TYP
0.406 p 0.076
(.016 p .003)
REF
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
0.86
(.034)
REF
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 p 0.0508
(.004 p .002)
MSOP (MS12) 1107 REV Ø
24613f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2461/LTC2463
TYPICAL APPLICATION
10μF
VCC
0.1μF
VCC
0.1μF
VCC
1
1k
9
IN+
IN–
1k
0.1μF
0.1μF
1μF
VCC
μC
12
5k
REFOUT VCC
IN+
VCC
SCL
5
LTC2463
6
SDA
IN–
3
10
A0
COMP REF– GND
0.1μF
2
8
7, 11, 4
0.1μF
5k
4
SCK/SCL
7
MOSI/SDA
5
MISO/SDO
GND
8
24613 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1860/LTC1861
12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L
12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC1864/LTC1865
16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L
16-bit, 3V, 1-/2-Channel 150ksps SAR ADC
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC2360
12-Bit, 100ksps SAR ADC
3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages
LTC2440
24-Bit No Latency ΔΣ™ ADC
200nVRMS Noise, 4kHz Output Rate, 15ppm INL
LTC2480
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA, Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
Temp. Sensor, SPI
LTC2481
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA, Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
Temp. Sensor, I2C
LTC2482
16-Bit, Differential Input, No Latency ΔΣ ADC, SPI
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2483
16-Bit, Differential Input, No Latency ΔΣ ADC, I2C
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2484
24-Bit, Differential Input, No Latency ΔΣ ADC, SPI with
Temp. Sensor
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2485
24-Bit, Differential Input, No Latency ΔΣ ADC, I2C with
Temp. Sensor
Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC6241
Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp
550nVP-P Noise, 125μV Offset Max
LTC2450
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V
Input Range
2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,
30Hz Output Rate
LTC2450-1
Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V
Input Range
2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,
60Hz Output Rate
LTC2451
Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C, 0V to 5.5V
Input Range
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Package, Programmable 30Hz/60Hz Output Rates
LTC2452
Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI,
±5.5V Input Range
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Package
LTC2453
Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C,
±5.5V Input Range
2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Package
LTC2460
16-Bit, ΔΣ SPI ADC with 10ppm Max Reference
Single-Ended, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages
LTC2462
16-Bit, ΔΣ SPI ADC with 10ppm Max Reference
Differential Input, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages
No Latency ΔΣ is a trademark of Linear Technology Corporation.
24613f
20 Linear Technology Corporation
LT 0609 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
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