MOTOROLA MTW32N20E

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SEMICONDUCTOR TECHNICAL DATA
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Motorola Preferred Device
TMOS POWER FET
32 AMPERES
200 VOLTS
RDS(on) = 0.075 OHM
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Isolated Mounting Hole

D
G
CASE 340K–01, Style 1
TO–247AE
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
200
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
200
Vdc
Gate–Source Voltage — Continuous
VGS
± 20
Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
32
19
128
Adc
Total Power Dissipation
Derate above 25°C
PD
180
1.44
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vpk, IL = 32 Apk, L = 1.58 mH, RG = 25 Ω )
EAS
810
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.7
40
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Sil Pad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MTW32N20E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
200
—
—
247
—
—
Vdc
mV/°C
—
—
—
—
250
1000
—
—
100
nAdc
2.0
—
—
8.0
4.0
—
Vdc
mV/°C
—
0.064
0.075
Ohm
—
—
—
—
3.0
2.7
gFS
12
—
—
mhos
Ciss
—
3600
5000
pF
Coss
—
130
250
Crss
—
690
1000
td(on)
—
25
50
tr
—
120
240
td(off)
—
75
150
tf
—
91
182
QT
—
85
120
Q1
—
12
—
Q2
—
40
—
Q3
—
30
—
—
—
1.1
0.9
2.0
—
trr
—
280
—
ta
—
195
—
tb
—
85
—
QRR
—
2.94
—
µC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
5.0
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
13
—
nH
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 V, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 200 Vdc, VGS = 0)
(VDS = 200 Vdc, VGS = 0, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
µAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 32 Adc)
(ID = 16 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vdc VGS = 0,
0
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS* ✝
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 100 Vdc,
Adc,
Vd ID = 32 Ad
VGS = 10 Vdc
Vdc,
RG = 6.2 Ω))
Fall Time
Gate Charge
Vd , ID = 32 Adc,
Ad ,
( DS = 160 Vdc,
(V
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
(IS = 32 Adc, VGS = 0)
(IS = 16 Adc, VGS = 0, TJ = 125°C)
Reverse Recovery Time
((IS = 32 Adc,
Ad , VGS = 0,
0,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
✝ Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTW32N20E
YPICAL ELECTRICAL CHARACTERISTICS
100
TJ = – 55°C
9V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
50
VGS = 10 V
TJ = 25°C
80
8V
60
7V
40
6V
20
100°C
VDS ≥ 10 V
40
25°C
30
20
10
5V
2
0
4
6
8
2
4
6
8
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.14
TJ = 100°C
0.12
0.1
0.08
25°C
0.06
– 55°C
0.04
0.02
8
16
24
32
40
48
56
64
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
VGS = 10 V
0
0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0.16
0
0
10
10
0.1
TJ = 25°C
0.09
0.08
VGS = 10 V
0.07
15 V
0.06
0.05
0
8
16
24
32
40
48
56
64
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
10000
VGS = 0 V
VGS = 10 V
ID = 16 A
2
I DSS, LEAKAGE (mA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
1.5
1
2000
TJ = 125°C
1000
200
100
100°C
20
0.5
–50
–25
0
25
50
75
100
125
150
10
25°C
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
200
3
MTW32N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at a
voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–
state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by L di/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
10000
VDS = 0
VGS = 0
TJ = 25°C
C, CAPACITANCE (pF)
8000
Crss
6000
4000
Ciss
2000
Coss
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
200
16
TJ = 25°C
ID = 32 A
VDS = 160 V
VDS
180
160
140
12
120
QT
8
100
80
Q2
Q1
VGS
60
40
4
0
20
Q3
0
10
20
30
40
50
60
70
QT, TOTAL CHARGE (nC)
80
90
0
100
1000
td(off)
TJ = 25°C
ID = 32 A
VDD = 100 V
VGS = 10 V
200
t, TIME (ns)
20
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTW32N20E
100
tr
tf
td(on)
20
10
2
1
1
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
2
10
20
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
TJ = 25°C
VGS = 0 V
I S , SOURCE CURRENT (AMPS)
30
20
10
0
0
0.2
0.4
0.6
0.8
1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive
pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in
AN569, “Transient Thermal Resistance–General Data and Its
Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10µs. In addition the total power averaged
over a complete switching cycle must not exceed (TJ(MAX) –
TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used in
switching circuits with unclamped inductive loads. For reliable
Motorola TMOS Power MOSFET Transistor Device Data
operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTW32N20E
VGS = 20 V
SINGLE PULSE
TC = 25°C
200
100
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
10 µs
.1
20
10
1
10
2
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.2
0.1
1
2
10
100 200
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
750
600
450
300
150
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
1
0.2
0.1
0.02
0.002
0.001
0.01
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
0.05
P(pk)
0.02
0.01
ID = 32 A
0.01
SINGLE PULSE
t1
t2
DUTY CYCLE, D = t1/t2
0.02
0.1
0.2
1
2
t, TIME (ms)
10
20
RθJC(t) = r(t) RθJC
RθJC = 0.7°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
100
200
1000
Figure 13. Thermal Response
6
Motorola TMOS Power MOSFET Transistor Device Data
MTW32N20E
PACKAGE DIMENSIONS
0.25 (0.010)
M
–T–
–Q–
T B M
E
–B–
C
4
L
U
A
R
1
K
2
3
–Y–
P
V
H
F
D
0.25 (0.010)
M
Y Q
J
G
S
CASE 340K–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
DIM
A
B
C
D
E
F
G
H
J
K
L
P
Q
R
U
V
STYLE 1:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
19.7
20.3
15.3
15.9
4.7
5.3
1.0
1.4
1.27 REF
2.0
2.4
5.5 BSC
2.2
2.6
0.4
0.8
14.2
14.8
5.5 NOM
3.7
4.3
3.55
3.65
5.0 NOM
5.5 BSC
3.0
3.4
INCHES
MIN
MAX
0.776
0.799
0.602
0.626
0.185
0.209
0.039
0.055
0.050 REF
0.079
0.094
0.216 BSC
0.087
0.102
0.016
0.031
0.559
0.583
0.217 NOM
0.146
0.169
0.140
0.144
0.197 NOM
0.217 BSC
0.118
0.134
GATE
DRAIN
SOURCE
DRAIN
7
MTW32N20E
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8
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*MTW32N20E/D*
Motorola TMOS Power MOSFET TransistorMTW32N20E/D
Device Data