ON MC100EP445FAR2 3.3v/5v ecl 8-bit serial/parallel converter Datasheet

MC10EP445, MC100EP445
3.3V/5VECL 8−Bit
Serial/Parallel Converter
The MC10/100EP445 is an integrated 8–bit differential serial to
parallel data converter with asynchronous data synchronization. The
device has two modes of operation. CKSEL HIGH mode is designed
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode
is designed to operate at twice the internal clock data rate of up to
5.0 Gb/s. The conversion sequence was chosen to convert the first
serial bit to Q0, the second bit to Q1, etc. Two selectable differential
serial inputs, which are selected by SINSEL, provide this device with
loop-back testing capability. The MC10/100EP445 has a SYNC pin
which, when held high for at least two consecutive clock cycles, will
swallow one bit of data shifting the start of the conversion data from
Dn to Dn+1. Each additional shift requires an additional pulse to be
applied to the SYNC pin.
Control pins are provided to reset and disable internal clock
circuitry. Additionally, VBB pin is provided for single-ended input
condition.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
32
1
XXX
A
WL
YY
WW
300 ps Propagation Delay
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
Differential Clock and Serial Inputs
MCXXX
EP445
AWLYYWW
= 10 OR 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
VBB Output for Single-Ended Input Applications
Asynchronous Data Synchronization (SYNC)
Asynchronous Master Reset (RESET)
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
Open Input Default State
ORDERING INFORMATION
Device
•
• CLK ENABLE Immune to Runt Pulse Generation
 Semiconductor Components Industries, LLC, 2002
November, 2002 - Rev. 7
1
Package
Shipping
MC10EP445FA
LQFP-32
250 Units/Tray
MC10EP445FAR2
LQFP-32
2000/Tape & Reel
MC100EP445FA
LQFP-32
250 Units/Tray
MC100EP445FAR2
LQFP-32
2000/Tape & Reel
Publication Order Number:
MC10EP445/D
VCC
Q2
Q1
VCC
Q0
PCLK
PCLK
VCC
MC10EP445, MC100EP445
PIN DESCRIPTION
24
23
22
21
20
19
18
17
PIN
FUNCTION
SINSEL
25
16
VEE
SINA*, SINA*
ECL Differential Serial Data Input A
SINB
26
15
Q3
SINB*, SINB*
ECL Differential Serial Data Input B
SINSEL*
ECL Serial Input Selector Pin
SINB
27
VEE
28
VBB0
29
MC10EP445
MC100EP445
14
Q4
Q0-Q7
ECL Parallel Data Outputs
13
VCC
CLK*, CLK*
ECL Differential Clock Inputs
12
VCC
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC*
ECL Conversion Synchronizing Input
CKSEL*
ECL Clock Input Selector Pin
CKEN*
ECL Clock Enable Pin
RESET*
ECL Reset Pin
VBB0, VBB1
Output Reference Voltage
VCC
Positive Supply
VEE
Negative Supply
SINA
30
11
Q5
SINA
31
10
Q6
VCC
32
9
Q7
7
8
VCC
CKSEL
6
VBB1
5
CLK
4
CLK
3
CKEN
2
SYNC
RESET
1
* Pins will default logic LOW or differential logic LOW
when left open.
Warning: All VCC and VEE pins must be externally
connected to Power Supply to guarantee proper
operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
TRUTH TABLE
FUNCTION
High
PIN
SINSEL
CKSEL
Low
Select SINB Input
Select SINA Input
Q: PCLK = 8:1
CLK: Q = 1:1
Q: PCLK = 8:1
CLK: Q = 1:2
CLK
CLK
Q
Q
CKEN
Synchronously Disable Internal Clock Circuitry
Synchronously Enable Internal
Clock Circuitry
RESET
Asynchronous Master Reset
Synchronous Enable
SYNC
Asynchronously Applied to Swallow a Data Bit
Normal Conversion Process
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2
MC10EP445, MC100EP445
SINA
VEE
SINA
SINB
1:2
DEMUX
SINB
1:2
DEMUX
1:2
DEMUX
SINSEL
1:2
DEMUX
CKEN
T
C
Q4
Q2
Q6
Q
1:2
DEMUX
R
T
C
Q0
Q
R
1:2
DEMUX
1:2
DEMUX
SYNC
Q1
Q5
Q3
Q7
Control
Logic
DIV2
CLK
PCLK
DIV2
PCLK
CLK
CKSEL
RESET
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
75 k
Internal Input Pull-up Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
Value
> 2 kV
> 200 V
> 2 kV
Level 2
Oxygen Index: 28 to 34
Transistor Count
UL 94 V-0 @ 0.125 in
993 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
MC10EP445, MC100EP445
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
95
119
143
98
122
146
100
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single-Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single-Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1790
1990
1855
2055
1915
2115
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1890
2.0
150
0.5
1955
150
0.5
0.5
2015
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
4. All loading with 50 to VCC - 2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP445, MC100EP445
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 7)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 8)
3865
3990
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 8)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single-Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single-Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3490
3690
3555
3755
3615
3815
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 9)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
3590
2.0
3655
150
3715
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
8. All loading with 50 to VCC-2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 11)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 12)
-1 135
-1010
-885
-1070
-945
-820
-1010
-885
-760
mV
VOL
Output LOW Voltage (Note 12)
-1935
-1810
-1685
-1870
-1745
-1620
-1810
-1685
-1560
mV
VIH
Input HIGH Voltage (Single-Ended)
-1210
-885
-1 145
-820
-1085
-760
mV
VIL
Input LOW Voltage (Single-Ended)
-1935
-1610
-1870
-1545
-1810
-1485
mV
VBB
Output Voltage Reference
-1510
-1310
-1445
-1245
-1385
-1 185
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
-1410
VEE+2.0
0.0
VEE+2.0
150
0.5
-1345
0.0
VEE+2.0
150
0.5
-1285
0.5
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with VCC.
11. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
12. All loading with 50 to VCC-2.0 volts.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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5
MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
95
119
143
98
122
146
100
125
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 15)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 15)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single-Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 16)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
1875
2.0
1875
150
0.5
1875
150
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.
15. All loading with 50 to VCC-2.0 volts.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 18)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 19)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 19)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single-Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single-Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
3575
2.0
150
0.5
3575
150
0.5
0.5
3575
A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.
18. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
19. All loading with 50 to VCC-2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP445, MC100EP445
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current (Note 22)
95
119
143
98
122
146
100
125
150
mA
VOH
Output HIGH Voltage (Note 23)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 23)
-1945
-1820
-1695
-1945
-1820
-1695
-1945
-1820
-1695
mV
VIH
Input HIGH Voltage (Single-Ended)
-1225
-880
-1225
-880
-1225
-880
mV
VIL
Input LOW Voltage (Single-Ended)
-1945
-1625
-1945
-1625
-1945
-1625
mV
VBB
Output Voltage Reference
-1525
-1325
-1525
-1325
-1525
-1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 24)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
-1425
VEE + 2.0
0.0
-1425
VEE + 2.0
150
0.0
-1425
VEE + 2.0
150
0.5
0.5
A
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21. Input and output parameters vary 1:1 with VCC.
22. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC-V EE operation at 3.3 V.
23. All loading with 50 to VCC - 2.0 volts.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
-40 °C
Symbol
Min
Typ
CKSEL = LOW
CKSEL = HIGH
2.0
2.8
2.5
3.3
CLK to Q
CLK TO PCLK
1230
1000
1450
1240
Characteristic
25°C
Max
Min
Typ
2.0
2.8
2.5
3.3
1300
1050
1530
1310
85°C
Max
Min
Typ
1.7
2.8
2.2
3.3
1400
1140
1650
1420
Max
Unit
fmax
Maximum Input CLK Frequency
(See Figure 12. Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
ts
Setup Time
SINA, B+ TO CLK+ (Figure 4)
CKEN+ TO CLK- (Figure 5)
-300
100
-400
50
-300
100
-400
50
-300
100
-400
50
ps
th
Hold Time
CLK+ TO SINA, B- (Figure 4)
CLK- TO CKEN (Figure 5)
650
45
550
-35
675
45
575
-35
725
45
625
-35
ps
tRR/tRR2
Reset Recovery (Figure 3)
350
180
350
180
350
180
ps
tPW
Minimum Pulse Width
tJITTER
Cycle-to-Cycle Jitter
(See Figure 12. Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
(Note 26)
tr
tf
Output Rise/Fall Times
(20% - 80%)
RESET
400
PCLK
Q
1660
1490
1760
1580
400
0.2
<1
150
800
1200
100
180
250
7
1900
1710
400
0.2
<1
150
800
1200
100
200
300
25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC - 2.0 V.
26. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
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GHz
ps
ps
0.2
<1
ps
150
800
1200
mV
125
230
325
ps
MC10EP445, MC100EP445
Reset
tRR
CLK
CLK
Figure 3. Reset Recovery
CLK
Data Setup Time
+
ts
Data Hold Time
+
th
Figure 4. Data Setup and Hold Time
CLK
CKEN Setup Time
+
ts
CKEN Hold Time -
+
th
Figure 5. CKEN Setup and Hold Time
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MC10EP445, MC100EP445
APPLICATION INFORMATION
The two selectable serial data paths can be used for
loop-back testing as well as the bit error testing.
Upon power-up, the internal flip-flops will attain a
random state. To synchronize multiple flip–flops in the
device, the Reset (pin 1) must be asserted. The reset pin will
disable the internal clock signal irrespective of the CKEN
state (CKEN disables the internal clock circuitry). The
device will grab the first stream of data after the falling edge
of RESET, followed by the falling edge of CLK, on
second rising edge of CLK in either CKSEL modes. (See
Figure 6)
The MC10/100EP445 is an integrated 1:8 serial to parallel
converter with two modes of operation selected by
CKSEL (Pin 7). CKSEL HIGH mode only latches data on
the rising edge of the input CLK and CKSEL LOW mode
latches data on both the rising and falling edge of the input
CLK. CKSEL LOW is the open default state. Either of the
two differential input serial data path provided for this
device, SINA and SINB, can be chosen with the SINSEL pin
(pin 25). SINA is the default input path when SINSEL pin
is left floating. Because of internal pull-downs on the input
pins, all input pins will default to logic low when left open.
RESET
(Asynchronous Reset)
RESET
(Synchronous ENABLE)
CLK
RESET
PCLK
Figure 6. Reset Timing Diagram
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MC10EP445, MC100EP445
For CKSEL LOW operation, the data is latched on both
the rising edge and the falling edge of the clock and the time
from when the serial data is latched to when the data is seen
on the parallel output is 6 clock cycles (see Figure 7).
Number of Clock Cycles from Data Latch to Q
1
2
3
4
5
6
CLK
SINA
D0
D1 D2 D3
D4 D5
D6
D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
RESET
CKEN
CKSEL
PCLK
Q0
D0
D8
D16
Q1
D1
D9
D17
Q2
D2
D10
D18
Q3
D3
D11
D19
Q4
D4
D12
D20
Q5
D5
D13
D21
Q6
D6
D14
D22
Q7
D7
D15
D23
Figure 7. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW
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10
MC10EP445, MC100EP445
Similarly, for CKSEL HIGH operation, the data is latched
only on the rising edge of the clock and the time from when
the serial data is latched to when the data is seen on the
parallel output is 12 clock cycles (see Figure 8).
Number of Clock Cycles from Data Latch to Q
2
3
4
5
6
7
8
9
10
1
11
12
CLK
SINA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
RESET
CKEN
CKSEL
PCLK
Q0
D0
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH
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11
MC10EP445, MC100EP445
clock cycles shifts the start bit for conversion from Qn to
Qn- 1. The bit is swallowed following the two clock cycle
pulse width of SYNC on the next triggering edge of
clock (either on the rising or the falling edge of the clock).
Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 9)
To allow the user to synchronize the output byte data
correctly, the start bit for conversion can be moved using the
SYNC input pin (pin 2). Asynchronously asserting the
SYNC pin will force the internal clock to swallow a clock
pulse, effectively shifting a bit from the Qn to the Qn- 1 output
as shown in Figure 9 and Figure 10. For CKSEL LOW, a
single pulse applied asynchronously for two consecutive
2 Clock Cycles for SYNC
1
2
Next Triggering Edge of Clock
Bit D8 is Swallowed
CLK
SINA
D0
D1 D2 D3
D4 D5 D6
D7 D8
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
CKSEL
PCLK
SYNC
Q0
D0
D9
D17
Q1
D1
D10
D18
Q2
D2
D11
D19
Q3
D3
D12
D20
Q4
D4
D13
D21
Q5
D5
D14
D22
Q6
D6
D15
D23
Q7
D7
D16
D24
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW
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12
MC10EP445, MC100EP445
triggering edge of clock (on the rising edge of the clock
only). Each additional shift requires an additional pulse to be
applied to the SYNC pin. (See Figure 10)
For CKSEL HIGH, a single pulse applied asynchronously
for three consecutive clock cycles shifts the start bit for
conversion from Qn to Qn- 1. The bit is swallowed following
the three clock cycle pulse width of SYNC on the next
3 Clock Cycles for Sync
1
2
3
Next Triggering Edge of Clock
Bit D8 is Swallowed
CLK
SINA
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
PCLK
Q0
D0
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH
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13
MC10EP445, MC100EP445
edge of CLK will suspend all activities. The first data bit will
clock on the rising edge, since the falling edge of CKEN
followed by the falling edge of the incoming clock triggers
the enabling of the internal process. (See Figure 11)
The synchronous CKEN (pin 3) applied with at least one
clock cycle pulse length will disable the internal clock
signal. The synchronous CKEN will suspend all of the
device activities and prevent runt pulses from being
generated. The rising edge of CKEN followed by the falling
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
PCLK
CKSEL
Figure 11. Timing Diagram with CKEN with CKSEL HIGH
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also rebias
AC coupled inputs. When used, decouple VBB and VCC via
a 0.01 F capacitor, which will limit the current sourcing or
sinking to 0.5mA. When not used, VBB should be left open.
Also, both outputs of the differential pair must be terminated
(50 to VTT = VCC – 2 V) even if only one output is used.
The differential PCLK output (pins 22 and 23) is a word
framer and can help the user to synchronize the parallel data
outputs. During CKSEL LOW operation, the PCLK will
provide a divide by 4-clock frequency, which frames the
serial data in period of PCLK output. Likewise during
CKSEL HIGH operation, the PCLK will provide a divide by
8-clock frequency.
The VBB pin, an internally generated voltage supply, is
available to this device only. For single–ended input
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14
MC10EP445, MC100EP445
VOUTpp (mV)
CKSEL HIGH
10
900
9
800
8
700
7
CKSEL LOW
600
6
500
5
400
300
200
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
4
3
2
(JITTER)
100
0
JITTEROUT ps (RMS)
1000
1
0
500
1000
1500
2000
2500
3000
3500
INPUT CLK FREQUENCY (MHz)
Figure 12. Fmax/Jitter
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
-
ECLinPS Circuit Performance at Non-Standard VIH Levels
AN1405
-
ECL Clock Distribution Techniques
AN1406
-
Designing with PECL (ECL at +5.0 V)
AN1504
-
Metastability and the ECLinPS Family
AN1568
-
Interfacing Between LVDS and ECL
AN1650
-
Using Wire-OR Ties in ECLinPS Designs
AN1672
-
The ECL Translator Guide
AND8001
-
Odd Number Counters Design
AND8002
-
Marking and Date Codes
AND8009
-
ECLinPS Plus Spice I/O Model Kit
AND8020
-
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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15
MC10EP445, MC100EP445
PACKAGE DIMENSIONS
LQFP
FA SUFFIX
32-LEAD PLASTIC PACKAGE
CASE 873A-02
ISSUE A
A
BASE
METAL
1
ÉÉ
ÉÉ
ÉÉ
B
V
DETAIL Y
V1
17
8
J
D
AE
P
AE
9
SECTION AE-AE
4X
-Z9
F
M
N
-U-
-T-
B1
-T-, -U-, -Z-
AC T−U Z
0.20 (0.008) AB T−U Z
25
0.20 (0.008)
32
4X
A1
DETAIL Y
0.20 (0.008) AC T−U Z
S1
S
DETAIL AD
G
-ABSEATING
PLANE
-AC0.10 (0.004) AC
8X
M
R
W
K
Q
X
DETAIL AD
GAUGE PLANE
H
0.250 (0.010)
C E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
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16
MC10EP445/D
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