PHILIPS HEF4022BD 4-stage divide-by-8 johnson counter Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4022B
MSI
4-stage divide-by-8 Johnson
counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
counter and the other clock input may be used as a clock
enable input. When cascading counters, the O4-7 output,
which is LOW while the counter is in states, 4, 5, 6 and 7,
can be used to drive the CP0 input of the next counter.
DESCRIPTION
The HEF4022B is a 4-stage divide-by-8 Johnson counter
with eight spike-free decoded active HIGH outputs (O0 to
O7), an active LOW output from the most significant
flip-flop (O4-7), active HIGH and active LOW clock inputs
(CP0, CP1) and an overriding asynchronous master reset
input (MR).
A HIGH on MR resets the counter to zero
(O0 = O4-7 = HIGH; O1 to O7 = LOW) independent of the
clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an
internal circuit, following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table). Either CP0 or CP1 may be used as clock input to the
Fig.1 Functional diagram.
HEF4022BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4022BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4022BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
See Family Specifications
PINNING
CPO
clock input (LOW to HIGH; edge-triggered)
CP1
clock input (HIGH to LOW; edge-triggered)
MR
master reset input
O0 to O7
decoded outputs
O4-7
carry output (active LOW)
January 1995
2
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Philips Semiconductors
4-stage divide-by-8 Johnson counter
January 1995
3
Product specification
HEF4022B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
Notes
FUNCTION TABLE
MR
CP0
CP1
H
X
X
L
H
L
O0 = O4-7 = H; O1 to O7 = L
Counter advances
L
Counter advances
L
L
X
No change
L
X
H
No change
L
H
L
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
OPERATION
No change
L
No change
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
195
390
ns
168 ns + (0,55 ns/pF) CL
75
145
ns
64 ns + (0,23 ns/pF) CL
50
100
ns
42 ns + (0,16 ns/pF) CL
Propagation delays
CP0, CP1 → On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
245
485
ns
218 ns + (0,55 ns/pF) CL
95
195
ns
84 ns + (0,23 ns/pF) CL
60
125
ns
52 ns + (0,16 ns/pF) CL
tPLH
15
CP0, CP1 → O4-7
5
HIGH to LOW
10
245
485
ns
218 ns + (0,55 ns/pF) CL
90
185
ns
79 ns + (0,23 ns/pF) CL
60
120
ns
52 ns + (0,16 ns/pF) CL
tPHL
15
5
LOW to HIGH
10
190
380
ns
163 ns + (0,55 ns/pF) CL
75
145
ns
64 ns + (0,23 ns/pF) CL
50
105
ns
42 ns + (0,16 ns/pF) CL
tPLH
15
MR → O1 to O7
HIGH to LOW
5
10
130
260
ns
103 ns + (0,55 ns/pF) CL
55
105
ns
44 ns + (0,23 ns/pF) CL
40
75
ns
32 ns + (0,16 ns/pF) CL
tPHL
15
MR → O0
LOW to HIGH
MR → O4-7
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
130
260
ns
103 ns + (0,55 ns/pF) CL
55
105
ns
44 ns + (0,23 ns/pF) CL
15
40
75
ns
32 ns + (0,16 ns/pF) CL
5
110
220
ns
83 ns + (0,55 ns/pF) CL
5
10
tPLH
45
90
ns
34 ns + (0,23 ns/pF) CL
15
35
70
ns
27 ns + (0,16 ns/pF) CL
5
60
120
ns
10 ns + (1,0 ns/pF) CL
10
tPLH
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
10
10
tTHL
tTLH
15
January 1995
4
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Hold times
CP0 → CP1
CP1 → CP0
SYMBOL
5
10
thold
MIN.
TYP.
MAX.
140
70
ns
50
25
ns
15
30
15
ns
5
170
85
ns
60
30
ns
15
40
20
ns
Minimum clock
5
75
35
ns
pulse width
10
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
10
thold
tWCP
30
15
ns
15
20
10
ns
5
70
35
ns
10
tWMRH
30
15
ns
15
20
10
ns
5
30
10
ns
10
tRMR
15
5
ns
15
10
5
ns
5
3
6
MHz
8
16
MHz
12
24
MHz
10
fmax
15
VDD
V
Dynamic power
dissipation per
package (P)
see also waveforms
Figs 4 and 5
TYPICAL FORMULA FOR P (µW)
5
475 fi + ∑ (fo CL) × VDD 2
10
2400 fi + ∑ (fo CL) × VDD 2
fi = input freq. (MHz)
15
6700 fi + ∑ (fo CL) × VDD
fo = output freq. (MHz)
2
where
CL = total load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
Fig.4
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0. Hold times are shown as positive values,
but may be specified as negative values.
Conditions: CP1 = LOW while CP0 is triggered on a LOW to HIGH transition.
tWCP and tRMR also apply when CP0 = HIGH and CP1 is triggered on
a HIGH to LOW transition.
Fig.5 Waveforms showing recovery time for MR; minimum CP0 and MR pulse widths.
January 1995
6
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
Fig.6 Timing diagram.
January 1995
7
Philips Semiconductors
Product specification
HEF4022B
MSI
4-stage divide-by-8 Johnson counter
APPLICATION INFORMATION
Some of the features of the HEF4022B are:
• High speed
• Spike-free decoded outputs
• Carry output for cascading
Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Fig.7 Counter expansion.
January 1995
8
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