IDT IDT71V256SA12Y Low power 3.3v cmos fast sram 256k (32k x 8-bit) Datasheet

LOW POWER
3.3V CMOS FAST SRAM
256K (32K x 8-BIT)
IDT71V256SA
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• Ideal for high-performance processor secondary cache
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Fast access times:
— Commercial: 10/12/15/20ns
— Industrial: 15ns
• Low standby current (maximum):
— 2mA full standby
• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
— 28-pin 300 mil plastic DIP (Commercial only)
— 28-pin TSOP Type I
• Produced with advanced high-performance CMOS
technology
• Inputs and outputs are LVTTL-compatible
• Single 3.3V(±0.3V) power supply
The IDT71V256SA is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology.
The IDT71V256SA has outstanding low power characteristics while at the same time maintaining very high performance. Address access times of as fast as10 ns are ideal for
3.3V secondary cache in 3.3V desktop designs.
When power management logic puts the IDT71V256SA in
standby mode, its very low power characteristics contribute to
extended battery life. By taking CS HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as CS remains HIGH. Furthermore, under
full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SA is packaged in 28-pin 300 mil SOJ, 28pin 300 mil plastic DIP, and 28-pin 300 mil TSOP Type I
packaging.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
GND
A14
I/O0
INPUT
DATA
CIRCUIT
I/O CONTROL
I/O7
CS
OE
WE
CONTROL
CIRCUIT
3101 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3101/04
1
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
Symbol
Rating
Value
Unit
–0.5 to +4.6
V
1
28
VCC
2
27
WE
VCC
3
26
Supply Voltage
Relative to GND
4
25
5
24
VTERM(2)
23
A13
A8
A9
A11
Terminal Voltage
Relative to GND
22
OE
TBIAS
Temperature Under Bias
–55 to +125
°C
21
A10
20
TSTG
Storage Temperature
CS
6
SO28-5
P28-2
7
8
9
10
19
11
18
12
17
13
16
14
15
DIP/SOJ
TOP VIEW
I/O7
I/O6
I/O5
I/O4
I/O3
OE
22
21
A 10
A 11
A9
A8
A 13
23
20
CS
24
19
25
18
26
17
WE
27
V CC
A 14
A 12
A7
A6
A5
A4
A3
28
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A0
A1
A2
16
1
15
14
2
13
3
12
4
11
5
10
6
9
7
8
V
–55 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
NOTES:
3101 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
3101 drw 02
SO28-8
–0.5 to VCC+0.5
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
Parameter(1)
Symbol
3101 drw 11
TSOP
TOP VIEW
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max. Unit
VIN = 3dV
6
pF
VOUT = 3dV
7
pF
NOTE:
3101 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Name
Description
A0–A14
I/O0–I/O7
CS
Addresses
Data Input/Output
Chip Select
WE
OE
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
GND
VCC
Write Enable
Commercial
0°C to +70°C
0V
3.3V ± 0.3V
Output Enable
Ground
Industrial
-40°C to +85°C
0V
3.3V ± 0.3V
GND
VCC
Power
3101 tbl 05
3101 tbl 01
RECOMMENDED DC OPERATING
CONDITIONS
TRUTH TABLE(1)
WE
CS
OE
I/O
X
H
X
High-Z
Standby (ISB)
X
VHC
X
High-Z
Standby (ISB1)
H
L
H
High-Z
Output Disable
H
L
L
L
L
X
DOUT
DIN
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
Function
Symbol
Read
Write
3101 tbl 02
Parameter
Min. Typ.
Max. Unit
VCC
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage - Inputs
2.0
—
5.0
V
VIH
Input High Voltage - I/O
2.0
—
Vcc+0.3
V
VIL
Input Low Voltage
–0.3(1)
—
0.8
V
NOTE:
3101 tbl 06
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.
2
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol
71V256SA10(3) 71V256SA12(3) 71V256SA15 71V256SA20(3) Unit
Parameter
ICC
Dynamic Operating Current CS ≤ VIL, Outputs
Open, VCC = Max., f = fMAX(2)
100
90
85
85
mA
ISB
Standby Power Supply Current (TTL Level)
(2)
CS = VIH, VCC = Max., Outputs Open, f = fMAX
20
20
20
20
mA
ISB1
Full Standby Power Supply Current (CMOS Level)
(2)
CS ≥ VHC , VCC = Max., Outputs Open, f = 0
,
VIN ≤ VLC or VIN ≥ VHC
2
2
2
2
mA
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.
3. Commercial temperature range only.
3101 tbl 07
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V± 0.3V
IDT71V256SA
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
|ILI|
Input Leakage Current
VCC = Max., VIN = GND to VCC
—
—
2
µA
|ILO|
Output Leakage Current
VCC = Max., CS = VIH, VOUT = GND to VCC
—
—
2
µA
VOL
Output Low Voltage
IOL = 8mA, VCC = Min.
—
—
0.4
V
VOH
Output High Voltage
IOH = –4mA, VCC = Min.
2.4
—
—
V
3101 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
3ns
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
3101 tbl 09
3.3V
3.3V
320Ω
320Ω
DATA OUT
DATA OUT
350Ω
350Ω
30pF*
3101 drw 04
5pF*
3101 drw 05
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
Figure 1. AC Test Load
*Includes scope and jig capacitances
3
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 0.3V)
71V256SA10(2)
Symbol
Parameter
71V256SA12(2)
71V256SA15
71V256SA20(2)
Max.
Min.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
10
—
—
10
12
—
—
12
15
—
—
15
20
—
—
20
ns
ns
tACS
—
10
—
12
—
15
—
20
ns
ns
Chip Select Access Time
(1)
Chip Select to Output in Low-Z
5
—
5
—
5
—
5
—
tCHZ(1)
Chip Select to Output in High-Z
0
8
0
8
0
9
0
10
ns
tOE
Output Enable to Output Valid
—
6
—
6
—
7
—
8
ns
tOLZ(1)
tOHZ(1)
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
3
2
—
6
3
2
—
6
0
0
—
7
0
0
—
8
ns
ns
tOH
Output Hold from Address Change
tCLZ
3
—
3
—
3
—
3
—
ns
Write Cycle
tWC
Write Cycle Time
tAW
Address Valid to End-of-Write
tCW
Chip Select to End-of-Write
10
9
9
—
—
—
12
9
9
—
—
—
15
10
10
—
—
—
20
15
15
—
—
—
ns
ns
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
9
—
9
—
10
—
15
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
tDW
tDH
tOW(1)
tWHZ(1)
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Write Enable to Output in High-Z
6
0
4
1
—
—
—
8
6
0
4
1
—
—
—
8
7
0
4
1
—
—
—
9
8
0
4
1
—
—
—
10
ns
ns
ns
ns
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
2. Commercial temperature range only.
3101 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC
ADDRESS
t AA
t OH
OE
t OE
t OLZ
(2)
t OHZ
(2)
t CHZ
(2)
CS
t ACS
t CLZ
DATAOUT
(2)
DATA VALID
3101 drw 06
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
4
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
t RC
ADDRESS
t AA
t OH
DATAOUT
t OH
PREVIOUS DATA VALID
DATA VALID
3101 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
t ACS
t CLZ
t CHZ
(5)
(5)
DATA VALID
DATAOUT
3101 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 5, 7)
t WC
ADDRESS
t OHZ
(6)
OE
t AW
CS
t WP
t AS
(7)
t WR
WE
t WHZ
DATAOUT
(6)
t OW (6)
(4)
(4)
t DW
DATAIN
t DH
DATA VALID
3101 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP.
5
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 4)
t WC
ADDRESS
t AW
CS
tAS
t CW
(5)
tWR
WE
t DW
t DH
DATA VALID
DATAIN
3101 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP.
ORDERING INFORMATION - COMMERCIAL
IDT71V256
SA
Power
XX
X
X
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Y
TP
PZ
300 mil SOJ (SO28-5)
300 mil Plastic DIP (P28-2)
TSOP Type I (SO28-8)
10
12
15
20
Speed in nanoseconds
I
Industrial (-40°C to +85°C)
Y
PZ
300 mil SOJ (SO28-5)
TSOP Type I (SO28-8)
15
Speed in nanoseconds
3101 drw 11
ORDERING INFORMATION - INDUSTRIAL
IDT71V256
SA
Power
XX
X
X
Speed
Package
Process/
Temperature
Range
3101 drw 12
6
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