AD ADL5201ACPZ-R7 Wide dynamic range, high speed Datasheet

FEATURES
−11.5 dB to +20 dB gain range
0.5 dB ± 0.1 dB step size
150 Ω differential input and output
7.5 dB noise figure at maximum gain
OIP3 > 50 dBm at 200 MHz
−3 dB upper frequency bandwidth of 700 MHz
Multiple control interface options
Parallel 6-bit control interface (with latch)
Serial peripheral interface (SPI) (with fast attack)
Gain up/down mode
Wide input dynamic range
Low power mode option
Power-down control
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP package
FUNCTIONAL BLOCK DIAGRAM
SPI WITH FA,
PARALLEL WITH LATCH,
UP/DOWN INTERFACE
MODE0,
MODE1
VIN+
VPOS GND PWUP
LOGIC
150Ω
0dB TO 31.5dB
+20dB
150Ω
VOUT–
VIN–
PM
VOUT+
ADL5201
09388-001
Data Sheet
Wide Dynamic Range, High Speed,
Digitally Controlled VGA
ADL5201
Figure 1.
APPLICATIONS
Differential ADC drivers
High IF sampling receivers
High output power IF amplification
Instrumentation
GENERAL DESCRIPTION
The ADL5201 is a digitally controlled, variable gain, wide bandwidth amplifier that provides precise gain control, high IP3, and
low noise figure. The excellent distortion performance and high
signal bandwidth make the ADL5201 an excellent gain control
device for a variety of receiver applications. The ADL5201 also
incorporates a low power mode option that lowers the supply
current.
The ADL5201 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the ADL5201
is typically 80 mA in low power mode. When configured in high
performance mode for more demanding applications, the quiescent
current is 110 mA. When powered down, the ADL5201 consumes
less than 7 mA and offers excellent input-to-output isolation.
The gain setting is preserved during power-down.
For wide input dynamic range applications, the ADL5201 provides
a broad 31.5 dB gain range with 0.5 dB resolution. The gain is
adjustable through multiple gain control interface options: parallel,
serial peripheral interface, and up/down.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5201 provides precise gain adjustment capabilities with
good distortion performance and low phase error. The ADL5201
amplifier comes in a compact, thermally enhanced, 24-lead,
4 mm × 4 mm LFCSP package and operates over the temperature
range of −40°C to +85°C.
Incorporating proprietary distortion cancellation techniques,
the ADL5201 achieves an output IP3 of greater than 47 dBm at
frequencies approaching 200 MHz for most gain settings.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADL5201
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description......................................................................... 17
Applications....................................................................................... 1
Basic Structure ............................................................................ 17
Functional Block Diagram .............................................................. 1
Input System ............................................................................... 17
General Description ......................................................................... 1
Output Amplifier........................................................................ 17
Revision History ............................................................................... 2
Gain Control ............................................................................... 17
Specifications..................................................................................... 3
Applications Information .............................................................. 18
Absolute Maximum Ratings............................................................ 5
Basic Connections...................................................................... 18
ESD Caution.................................................................................. 5
ADC Driving............................................................................... 18
Pin Configuration and Function Descriptions............................. 6
Layout Considerations............................................................... 20
Typical Performance Characteristics ............................................. 7
Evaluation Board ............................................................................ 21
Characterization and Test Circuits............................................... 14
Evaluation Board Control Software......................................... 21
Theory of Operation ...................................................................... 15
Schematics and Artwork ........................................................... 22
Digital Interface Overview ........................................................ 15
Evaluation Board Configuration Options............................... 24
Parallel Digital Interface ............................................................ 15
Outline Dimensions ....................................................................... 26
Serial Peripheral Interface (SPI) ............................................... 15
Ordering Guide .......................................................................... 26
Up/Down Interface .................................................................... 15
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADL5201
SPECIFICATIONS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Return Loss (S11)
Output Return Loss (S22)
INPUT STAGE
Maximum Input Swing (Differential)
Differential Input Resistance
Common-Mode Input Voltage
CMRR
GAIN
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain Flatness
Gain Temperature Sensitivity
Gain Step Response
Gain Conformance Error
Phase Conformance Error
OUTPUT STAGE
Output Voltage Swing
Differential Output Resistance
NOISE/HARMONIC PERFORMANCE
46 MHz
Second Harmonic
Third Harmonic
Output IP3 (OIP3)
70 MHz
Second Harmonic
Third Harmonic
Output IP3 (OIP3)
140 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3 (OIP3)
Output 1 dB Compression Point (OIP1dB)
300 MHz
Second Harmonic
Third Harmonic
Output IP3 (OIP3)
Test Conditions/Comments
VOUT < 2 V p-p (5.2 dBm)
Min
Typ
Max
Unit
700
5.5
−18.73
−18.8
MHz
V/ns
dB
dB
10.8
150
1.5
51.44
V p-p
Ω
V
dB
30 MHz < fC < 200 MHz
Gain code = 000000
For VIN = 0.2 V, gain code = 111111 to 000000
Over 10 dB gain range
Over 10 dB gain range
20
−11.5
0.5
0.285
0.0089
15
±0.03
1.0
dB
dB
dB
dB
dB/°C
ns
dB
Degrees
VOUT+ and VOUT− pins
At P1dB, gain code = 000000
Differential
10
150
V p-p
Ω
−86
−104
50
dBc
dBc
dBm
−91
−103
51
dBc
dBc
dBm
7.5
−89
−97
51
19.8
dB
dBc
dBc
dBm
dBm
−85
−90
50
dBc
dBc
dBm
100 MHz
100 MHz
VIN+ and VIN− pins
Gain code = 111111
Gain code = 000000
Gain code = 000000
Gain code = 111111
Gain code = 000000, high performance mode
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p composite
Gain code = 000000, high performance mode
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p composite
Gain code = 000000, high performance mode
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p composite
Gain code = 000000, high performance mode
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p composite
Rev. 0 | Page 3 of 28
ADL5201
Data Sheet
Parameter
POWER-UP INTERFACE
Power-Up Threshold
Test Conditions/Comments
PWUP pin
Minimum voltage to enable the device
Maximum voltage to enable the device
PWUP Input Bias Current
GAIN CONTROL INTERFACE
VIH
VIL
Maximum Input Bias Current
SPI TIMING
fSCLK
tDH
tDS
tPW
POWER INTERFACE
Supply Voltage
Quiescent Current
Min
Typ
Max
Unit
3.3
V
V
μA
1.4
1
Minimum/maximum voltage for a logic high
Maximum voltage for a logic low
1.4
3.3
0.8
LATCH, SCLK, SDIO, data pins
1/tSCLK
Data hold time
Data setup time
SCLK high pulse width
1
μA
20
5
5
5
MHz
ns
ns
ns
4.5
5.5
High performance mode
85°C
Low power mode
85°C
PWUP low
Power-Down Current
V
110
120
80
95
7
V
mA
mA
mA
mA
mA
TIMING DIAGRAMS
tPW
tSCLK
SCLK
tDH
tDS
CS
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
D4
D3
Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS
tDS
tPW
UPDN_DAT
UPDN_CLK
UP
DN
tDS
RESET
tDH
Figure 3. Up/Down Mode Timing Diagram
LATCH
A5 TO A0
tDH
Figure 4. Parallel Mode Timing Diagram
Rev. 0 | Page 4 of 28
09388-104
DNC
09388-003
SDIO
D2
D1
D0
09388-002
tDS tDH
Data Sheet
ADL5201
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS
PWUP, A0 to A5, MODE0, MODE1, PM, LATCH
Input Voltage, VIN+ and VIN−
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (at Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
3.6 V
+3.6 V to −1.2 V
676.5 mW
37.16°C/W
2.29°C/W
140°C
–40°C to +85°C
–65°C to +150°C
240°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
ADL5201
Data Sheet
19 PWUP
21 VPOS
20 PM
22 VPOS
23 VPOS
24 VPOS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
18 VPOS
VIN+ 2
17 VOUT–
VIN– 3
ADL5201
16 VOUT+
GND 4
TOP VIEW
(Not to Scale)
15 VOUT–
MODE1 5
14 VOUT+
MODE0 6
NOTES
1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
A LOW IMPEDANCE GROUND PAD.
09388-004
UPDN_DAT/A0 12
9
GS1/CS/A3
UPDN_CLK/A1 11
8
GS0/FA/A2 10
7
SDIO/A5
SCLK/A4
13 LATCH
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 4, EP
2
3
5
6
7
Mnemonic
GND
VIN+
VIN−
MODE1
MODE0
SDIO/A5
8
SCLK/A4
9
GS1/CS/A3
10
GS0/FA/A2
11
UPDN_CLK/A1
12
UPDN_DAT/A0
13
LATCH
14, 16
15, 17
18, 21,
22, 23, 24
19
20
VOUT+
VOUT−
VPOS
PWUP
PM
Description
Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.
Positive Input.
Negative Input.
MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.
LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.
Serial Data Input/Output (SDIO). When CS is pulled low, SDIO is used for reading and writing to the SPI port.
Bit 5 for Parallel Gain Control Interface (A5).
Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Parallel Gain Control Interface (A4).
MSB for Gain Step Size Control in Up/Down Mode (GS1).
SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface.
Bit 3 for Parallel Gain Control Interface (A3).
LSB for Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack (FA). In serial mode, a logic high (1.4 V ≤ FA ≤ 3.3 V) attenuates according to the FA setting in the SPI
word. Bit 2 for Parallel Gain Control Interface (A2).
Clock Interface for Up/Down Function (UPDN_CLK).
Bit 1 for Parallel Gain Control Interface (A1).
Data Pin for Up/Down Function (UPDN_DAT).
Bit 0 for Parallel Gain Control Interface (A0).
A logic low (0 V ≤ LATCH ≤ 0.8 V) allows gain changes. A logic high (1.4 V ≤ LATCH ≤ 3.3 V) disallows gain
changes.
Positive Output.
Negative Output.
Positive Power Supply.
Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part.
Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V)
enables low power mode.
Rev. 0 | Page 6 of 28
Data Sheet
ADL5201
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 200 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.
25
25
46MHz
140MHz
300MHz
20
14dB
13dB
10dB
9dB
12dB
11dB
6dB
5dB
8dB
7dB
15
15
10
GAIN (dB)
10
GAIN (dB)
16dB
15dB
18dB
17dB
20dB
19dB
20
5
0
5
0
–5
–5
–10
–10
–15
20
30
40
50
60
70
GAIN CODE
–20
10
40
35
35
NOISE FIGURE (dB)
40
30
25
20
15
15
20
25
PROGRAMMED GAIN (dB)
–6dB
–7dB
–8dB
–9dB
–10dB
–11dB
1000
Figure 7. Noise Figure vs. Programmed Gain at 140 MHz
TA = +25°C
TA = +85°C
MIN GAIN (–11.5dB)
MID GAIN (+5dB)
15
5
10
TA = –40°C
20
5
5
–4dB
–5dB
100
25
10
0
–2dB
–3dB
30
10
0
09388-006
NOISE FIGURE (dB)
45
–5
0dB
–1dB
Figure 9. Gain vs. Frequency Response (Every 1 dB Step)
45
–10
2dB
1dB
FREQUENCY (MHz)
Figure 6. Gain vs. Gain Code at 46 MHz, 140 MHz, and 300 MHz
0
–15
4dB
3dB
09388-008
10
MAX GAIN (+20dB)
0
100
200
300
400
500
600
FREQUENCY (MHz)
09388-009
0
09388-005
–15
Figure 10. Noise Figure vs. Frequency at Max, Mid, and Min Gain Outputs
25
20
18
20
16
OP1dB (dBm)
15
10
5
TA = –40°C
TA = +25°C
TA = +85°C
12
10
8
6
INPUT
MAX RATINGS
BOUNDARY
4
0
–15
–10
–5
0
5
10
15
20
PROGRAMMED GAIN (dB)
Figure 8. OP1dB vs. Programmed Gain at 140 MHz
25
0
0
50
100
150
200
250
FREQUENCY (MHz)
300
350
400
09388-010
2
09388-007
OP1dB (dBm)
14
Figure 11. OP1dB vs. Frequency at Maximum Gain, Three Temperatures
Rev. 0 | Page 7 of 28
ADL5201
60
Data Sheet
60
–11.5dB
0dB
+10dB
+20dB
55
–11.5dB
0dB
+10dB
+20dB
55
50
OIP3 (dBm)
OIP3 (dBm)
50
45
45
40
INPUT
MAX RATINGS
BOUNDARY
35
40
30
35
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
Figure 12. Output Third-Order Intercept vs. Frequency
at Four Gain Codes
60
20
–4
1
2
3
4
5
6
TA = –40°C
TA = +25°C
TA = +85°C
55
45
45
40
40
35
35
50
100
150
200
250
300
350
400
–60
46MHz
140MHz
300MHz
–80
–80
IMD3 (dBc)
–70
–90
–100
–110
–110
0
5
10
15
20
PROGRAMMED GAIN (dB)
25
–120
09388-013
–5
–1
0
1
2
3
4
5
6
TA = –40°C
TA = +25°C
TA = +85°C
–90
–100
–10
–2
POUT (dBm)
–70
–120
–15
–3
Figure 16. Output Third-Order Intercept vs. Power, Frequency = 140 MHz,
Three Temperatures
Figure 13. Output Third-Order Intercept vs. Frequency,
Three Temperatures at 2 V p-p Composite
–60
30
–4
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
Figure 14. Two-Tone Output IMD3 vs. Programmed Gain
at 46 MHz, 140 MHz, and 300 MHz
Figure 17. Two-Tone Output IMD3 vs. Frequency,
Three Temperatures
Rev. 0 | Page 8 of 28
400
09388-016
0
09388-015
OIP3 (dBm)
50
09388-012
OIP3 (dBm)
0
60
FREQUENCY (MHz)
IMD3 (dBc)
–1
Figure 15. Output Third-Order Intercept vs. Power at Four Gain Codes,
Frequency = 140 MHz at 2 V p-p Composite
50
30
–2
POUT (dBm)
TA = –40°C
TA = +25°C
TA = +85°C
55
–3
09388-014
0
09388-011
30
25
Data Sheet
–90
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
–150
0
50
100
150
200
250
–120
350
300
FREQUENCY (MHz)
–80
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140
–6
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140
50
100
150
200
250
–120
350
300
09388-018
0
HARMONIC DISTORTION HD2 (dBc)
–60
–80
HARMONIC DISTORTION HD3 (dBc)
–50
–80
FREQUENCY (MHz)
–2
–1
0
1
2
3
4
5
6
–120
–60
TA = –40°C
TA = +25°C
TA = +85°C
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
–120
POUT (dBm)
Figure 22. Harmonic Distortion vs. Power, Frequency = 140 MHz,
Three Temperatures
Figure 19. Harmonic Distortion vs. Frequency, Three Temperatures
25
20
18
20
16
14
15
OP1dB (dBm)
OP1dB (dBm)
10
5
TA = –40°C
TA = +25°C
TA = +85°C
12
10
8
6
INPUT
MAX RATINGS
BOUNDARY
4
0
–15
–10
–5
0
5
10
PROGRAMMED GAIN (dB)
15
20
25
0
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 20. OP1dB vs. Programmed Gain at 140 MHz, Low Power Mode
300
350
400
09388-022
2
09388-019
HARMONIC DISTORTION HD2 (dBc)
–70
–3
POUT (dBm)
–40
TA = –40°C
TA = +25°C
TA = +85°C
–4
Figure 21. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency = 140 MHz
Figure 18. Harmonic Distortion vs. Frequency at Four Gain Codes
–60
–5
HARMONIC DISTORTION HD3 (dBc)
–50
–50
HARMONIC DISTORTION HD3 (dBc)
–80
–70
09388-021
–40
–40
–11.5dB
0dB
+10dB
+20dB
09388-020
–30
HARMONIC DISTORTION HD2 (dBc)
–70
–60
HARMONIC DISTORTION HD3 (dBc)
–60
HARMONIC DISTORTION HD2 (dBc)
–20
–11.5dB
0dB
+10dB
+20dB
09388-017
–50
ADL5201
Figure 23. OP1dB vs. Frequency at Maximum Gain, Three Temperatures,
Low Power Mode
Rev. 0 | Page 9 of 28
ADL5201
Data Sheet
60
60
–11.5dB
0dB
+10dB
+20dB
55
–11.5dB
0dB
+10dB
+20dB
55
50
45
OIP3 (dBm)
OIP3 (dBm)
50
45
40
35
40
INPUT
MAX RATINGS
BOUNDARY
30
35
0
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
Figure 24. Output Third-Order Intercept vs. Frequency
at Four Gain Codes, Low Power Mode at 2 V p-p Composite
60
20
–4
09388-023
55
1
2
3
4
5
6
TA = –40°C
TA = +25°C
TA = +85°C
50
45
40
40
35
35
0
50
100
150
200
250
300
350
400
30
–4
–70
–1
0
1
2
3
4
5
6
Figure 28. Output Third-Order Intercept vs. Power,
Three Temperatures, Low Power Mode at 2 V p-p Composite
–60
46MHz
140MHz
300MHz
TA = –40°C
TA = +25°C
TA = +85°C
–70
–80
IMD3 (dBc)
–80
–90
–90
–100
–110
–110
–10
–5
0
5
10
15
20
PROGRAMMED GAIN (dB)
25
09388-025
–100
–120
–15
–2
POUT (dBm)
Figure 25. Output Third-Order Intercept vs. Frequency,
Three Temperatures, Low Power Mode
–60
–3
09388-027
OIP3 (dBm)
45
09388-024
OIP3 (dBm)
0
60
FREQUENCY (MHz)
IMD3 (dBc)
–1
Figure 27. Output Third-Order Intercept vs. Power at Four Gain Codes,
Frequency = 140 MHz, Low Power Mode
50
30
–2
POUT (dBm)
TA = –40°C
TA = +25°C
TA = +85°C
55
–3
–120
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
Figure 29. Two-Tone Output IMD3 vs. Frequency,
Three Temperatures, Low Power Mode
Figure 26. Two-Tone Output IMD3 vs. Programmed Gain
at 46 MHz, 140 MHz, and 300 MHz; Low Power Mode
Rev. 0 | Page 10 of 28
400
09388-028
30
09388-026
25
Data Sheet
–90
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
–150
0
50
100
150
200
250
300
–120
350
FREQUENCY (MHz)
–80
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140
–6
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
0
50
100
150
200
250
300
–120
350
FREQUENCY (MHz)
HARMONIC DISTORTION HD2 (dBc)
–50
–90
HARMONIC DISTORTION HD3 (dBc)
–80
09388-030
–40
–150
–70
–30
–70
–80
–2
–1
0
1
2
3
4
5
6
–120
–50
TA = –40°C
TA = +25°C
TA = +85°C
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130
–6
Figure 31. Harmonic Distortion vs. Frequency, Three Temperatures,
Low Power Mode
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
–110
POUT (dBm)
Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz,
Three Temperatures, Low Power Mode
VOLTAGE
CH4 1mV/DIV
CH1 200mV/DIV
CH1 200mV/DIV
TIME (10ns/DIV)
TIME (10ns/DIV)
Figure 32. Enable Time Domain Response
Figure 35. Disable Time Domain Response
Rev. 0 | Page 11 of 28
09388-034
CH4 1V/DIV
09388-031
VOLTAGE
HARMONIC DISTORTION HD2 (dBc)
–60
–3
Figure 33. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency = 140 MHz, Low Power Mode
–20
TA = –40°C
TA = +25°C
TA = +85°C
–4
POUT (dBm)
Figure 30. Harmonic Distortion vs. Frequency at Four Gain Codes,
Low Power Mode
–50
–5
HARMONIC DISTORTION HD3 (dBc)
–50
–50
HARMONIC DISTORTION HD3 (dBc)
–80
–70
09388-033
–40
–40
–11.5dB
0dB
+10dB
+20dB
09388-032
–30
HARMONIC DISTORTION HD2 (dBc)
–70
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
–60
–60
–20
–11.5dB
0dB
+10dB
+20dB
09388-029
–50
ADL5201
ADL5201
Data Sheet
CH2 500mV/DIV
0pF
VOLTAGE
TIME (10ns/DIV)
TIME (1ns/DIV)
100
–30
50
–40
0
–50
–50
–60
–100
300
250
–20
200
–30
150
–40
100
–50
50
–60
0
–70
–50
–80
–150
–90
–200
1000
100
–100
10
09388-036
–80
10
0
–10
FREQUENCY (MHz)
–100
MAGNITUDE MAX GAIN
MAGNITUDE MIN GAIN
PHASE MAX GAIN
PHASE MIN GAIN
–150
100
–200
1000
09388-039
–20
S22 MAGNITUDE (dB)
150
S11 PHASE (Degrees)
–10
FREQUENCY (MHz)
Figure 40. S22 Magnitude and Phase vs. Frequency
Figure 37. S11 Magnitude and Phase vs. Frequency
1.0
0
0.8
–10
REVERSE ISOLATION (dB)
0.6
0.4
0.2
0
–0.2
–0.4
–20
–30
–40
–50
–0.6
–1.0
–15
–10
–5
0
5
10
15
20
PROGRAMMED GAIN (dB)
25
Figure 38. Gain Step Error, Frequency = 140 MHz
–70
10
100
FREQUENCY (MHz)
Figure 41. Reverse Isolation vs. Frequency
Rev. 0 | Page 12 of 28
1000
09388-041
–60
–0.8
09388-037
GAIN ERROR (dB)
S11 MAGNITUDE (dB)
200
S22 PHASE (Degrees)
Figure 39. Large Signal Pulse Response, 0 pF and 5.6 pF, 2 V p-p Composite
0
MAGNITUDE MAX GAIN
MAGNITUDE MIN GAIN
PHASE MAX GAIN
PHASE MIN GAIN
09388-038
200mV/DIV
Figure 36. Gain Step Time Domain Response
–70
INPUT
09388-035
VOLTAGE
CH3 50mV/DIV
5.6pF DIFFERENTIAL
Data Sheet
1.0
ADL5201
0
MIN
MID
MAX
–10
REVERSE ISOLATION (dB)
GROUP DELAY (ns)
0.8
0.6
0.4
0.2
–20
–30
–40
1000
FREQUENCY (MHz)
–60
10
COMMON-MODE REJECTION RATIO, CMRR (dB)
3.0
350MHz
300MHz
250MHz
200MHz
150MHz
100MHz
50MHz
2.5
2.0
1.5
1.0
0.5
0
0
10
20
30
40
50
GAIN CODE
60
70
09388-043
PHASE VARIATION (Degrees)
3.5
1000
Figure 44. Disable-State Reverse Isolation vs. Frequency
Figure 42. Group Delay vs. Frequency at Max, Mid, and Min Gain Outputs
4.0
100
FREQUENCY (MHz)
Figure 43. Phase Variation vs. Gain Code
60
50
40
30
20
10
0
10
100
1000
FREQUENCY (MHz)
Figure 45. Common-Mode Rejection Ratio vs. Frequency
Rev. 0 | Page 13 of 28
09388-045
100
09388-042
0
10
09388-044
–50
ADL5201
Data Sheet
CHARACTERIZATION AND TEST CIRCUITS
+5V
L1
1µH
50Ω
AC
C3
0.1µF
ADL5201
50Ω TRACES
50Ω
L2
1µH
0.1µF
C2
50Ω
50Ω TRACES
AC
50Ω
0.1µF
C4
6
09388-046
C1
0.1µF
A0 TO A5
Figure 46. Test Circuit for S-Parameters on Dedicated 50 Ω Differential-to-Differential Board
+5V
AC
C2
0.1µF
6
C3
0.1µF
R1
62Ω
R4
25Ω
ETC1-1-13
PAD LOSS = 11dB
C4
0.1µF
R2
62Ω
T2
50Ω
R3
25Ω
A0 TO A5
Figure 47. Test Circuit for Distortion, Gain, and Noise
09388-048
50Ω
ADL5201
T1
L2
1µH
09388-047
TC3-1T
L1
1µH
C1
0.1µF
Figure 48. Differential-to-Differential Characterization Board
Rev. 0 | Page 14 of 28
Data Sheet
ADL5201
THEORY OF OPERATION
DIGITAL INTERFACE OVERVIEW
The ADL5201 DVGA has three digital gain control options:
parallel control interface, serial peripheral interface, and gain
up/down interface. The desired gain control option is selected via
two control pins, MODE0 and MODE1 (see Table 4 for the
truth table for the mode control pins). The gain code is in 6-bit
binary format. A voltage from 1.4 V to 3.3 V is required for a
logic high.
Two pins are common to all gain control options: PM and PWUP.
PM allows the user to choose operation in low power mode or
high performance mode. PWUP is the power-up pin. Physical
pins are shared among the three interfaces, resulting in as many
as three different functions per digital pin (see Table 3).
Table 4. Digital Control Interface Selection Truth Table
MODE1
0
0
1
1
MODE0
0
1
0
1
Interface
Parallel control
Serial peripheral (SPI)
Up/down
Up/down
To write to the SPI register, CS must be pulled low and 16 clock
pulses must be applied to SCLK. To read the SPI register value,
the R/W bit must be set high, CS must be pulled low, and the
part must be clocked. After the register is read out during the
next 16 clock cycles, the SPI is automatically placed in write mode.
Fast Attack
The fast attack feature, accessible via the SPI, allows the gain to
be reduced from its present gain setting by a predetermined step
size. Four different attenuation step sizes are available. The
truth table for fast attack is shown in Table 5.
Table 5. SPI 2-Bit Attenuation Step Size Truth Table
FA1
0
0
1
1
FA0
0
1
0
1
Step Size (dB)
2
4
8
16
SPI fast attack mode is controlled by the FA pin. A logic high
on the FA pin results in an attenuation that is selected by
Bits[FA1:FA0] in the SPI register.
PARALLEL DIGITAL INTERFACE
UP/DOWN INTERFACE
The parallel digital interface uses six binary bits (Bits[A5:A0])
and a latch pin (LATCH). The Latch pin controls whether the
input data latch is transparent or latched. In transparent mode,
the gain changes as the input gain control bits change. In latched
mode, gain is determined by the latched gain setting and does
not change with the input gain control bits.
The GS1 and GS0 pins control the up/down gain step function.
Gain is increased by a clock pulse on the UPDN_CLK pin
(rising and falling edges) when the UPDN_DAT pin is high.
Gain is decreased by a clock pulse on the UPDN_CLK pin
when the UPDN_DAT pin is low.
UPDN_CLK
The SPI uses three pins: SDIO, SCLK, and CS. The SPI data
register consists of two bytes: six gain control bits, two attenuation step size address bits, one read/write bit, and seven don’t
care bits. SDIO is the serial data input and output pin. The
SCLK pin is the serial clock, and CS is the channel select pin.
D1
D2
D3
D4
D5
FA0
FA1 R/W DNC DNC DNC DNC DNC DNC DNC
DO NOT CARE
(7 BITS)
GAIN CONTROL
Figure 49. 16-Bit SPI Register
DN
RESET
Figure 50. Up/Down Timing
Reset is detected by a rising edge latching data having one polarity,
with the falling edge latching the opposite polarity. Reset results
in a minimum binary gain code of 111111.
Table 6. Gain Step Size Control Truth Table
READ/WRITE
FAST ATTACK ATTENUATION
STEP SIZE ADDRESS
09388-050
D0
UP
The truth table for the gain step function is shown in Table 6.
The step size is selectable using the GS1 and GS0 pins. The gain
is limited by the top and bottom of the control range.
MSB LSB MSB
DATA
UPDN_DAT
09388-049
SERIAL PERIPHERAL INTERFACE (SPI)
GS1
0
0
1
1
Rev. 0 | Page 15 of 28
GS0
0
1
0
1
Step Size (dB)
0.5
1
2
4
ADL5201
Data Sheet
Truth Table
LOGIC TIMING
To write to the ADL5201, refer to the timing shown in Figure 51.
The write mode uses a 16-bit serial word on the SDIO pin. The
R/W bit of the word must be low to write Bits[D5:D0], which are
the binary weighted codes for the attenuation level (0 = minimum
attenuation, 63 = maximum attenuation). The FA0 and FA1 bits
control the fast attack step size. The DNC bits are nonfunctional,
do not care bits.
Table 7. Gain Code vs. Voltage Gain Lookup Table
6-Bit Binary
Gain Code
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Voltage
Gain (dB)
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
6-Bit Binary
Gain Code
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Voltage
Gain (dB)
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
−5
−5.5
−6
−6.5
−7
−7.5
−8
−8.5
−9
−9.5
−10
−10.5
−11
−11.5
Reading the ADL5201 SPI register requires the following two steps:
1.
2.
Set the R/W bit high using a 16-bit word and the timing
shown in Figure 51. All other bits are ignored when the
R/W bit is high.
The SDIO is used as an output during the next sequence.
The written pattern is serially clocked out on SDIO using
16 clocks and the timing shown in Figure 51. The R/W bit
automatically returns low to the write state following the
read sequence.
tPW
tSCLK
SCLK
tDH
tDS
CS
SDIO
DNC
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
Figure 51. SPI Interface Read/Write Mode Timing Diagram
Rev. 0 | Page 16 of 28
D4
D3
D2
D1
D0
09388-151
tDS tDH
Data Sheet
ADL5201
CIRCUIT DESCRIPTION
The dc current to the outputs of each amplifier is supplied through
two external chokes. The inductance of the chokes and the
resistance of the load, in parallel with the output resistance of
the device, add a low frequency pole to the response. The parasitic capacitance of the chokes adds to the output capacitance of the
part. This total capacitance, in parallel with the load and output
resistance, sets the high frequency pole of the device. Generally,
the larger the inductance of the choke, the higher its parasitic
capacitance. Therefore, this trade-off must be considered when
the value and type of the choke are selected. For an operation
frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 μH
chokes with an SRF of 160 MHz or higher are recommended
(such as the 0805LS-102XJBB from Coilcraft). If higher value
chokes are used, a 4 MHz zero, due to the internal ac-coupled
feedback, causes an increase in S21 of up to 6 dB at frequencies
below 4 MHz.
BASIC STRUCTURE
The ADL5201 is a differential variable gain amplifier (VGA)
consisting of a 150 Ω digitally controlled passive attenuator
followed by a highly linear transconductance amplifier with
feedback.
ADL5201
gm
AMP
ATTENUATOR
VIN–
VOUT+
VOUT–
LOGIC
REF
DIGITAL INPUTS
PARALLEL, SPI,
FAST ATTACK
UP/DOWN
09388-051
VIN+
Figure 52. Simplified Schematic
INPUT SYSTEM
The dc voltage level at the input of the amplifier is set by an
independent internal voltage reference circuit to approximately
1.6 V. The reference is not accessible and cannot be adjusted.
The amplifier can be powered down by pulling the PWUP pin
low. In power-down mode, the total current is reduced to 7 mA
(typical). The dc level at the input remains at approximately
1.6 V, regardless of the state of the PWUP pin.
OUTPUT AMPLIFIER
Gain of the output amplifier is set to be 22 dB when driving
a 150 Ω load. The input and output resistance of this amplifier
is set to 150 Ω in matched condition. If the load or the source
resistance is not equal to 150 Ω, the following equations can be
used to determine the resulting gain and input/output resistances.
Voltage Gain = AV = 0.09 × (2000)//RL
RIN = (2000 + RL)/(1 + 0.09 × RL)
S21 (Gain) = 2 × RIN/(RIN + RS) × AV
ROUT = (2000 + RS)/(1 + 0.09 × RS)
Note that the at maximum attenuation setting, RS, as seen by
the output amplifier, is the output resistance of the attenuator,
which is 150 Ω. However, at the minimum attenuation setting,
RS is the source resistance that is connected to the input of the part.
The supply current of the amplifier consists of about 35 mA
through the VPOS pin and 50 mA through the two chokes
combined. The latter increases with temperature at
approximately 2.5 mA per 10°C. The total choke current increases
to 75 mA for high performance mode. The amplifier has two
output pins for each polarity, and they are oriented in an
alternating fashion. When designing the board, care should be
taken to minimize the parasitic capacitance due to the routing
that connects the corresponding outputs together. To minimize
the parasitic capacitance, a good practice is to avoid any ground
or power plane under this routing region and under the chokes.
GAIN CONTROL
The gain can be adjusted using the parallel control interface, the
serial peripheral interface, or the gain up/down interface. In
general, the gain step size is 0.5 dB, but larger sizes can be
programmed using the various interfaces, as described in the
Digital Interface Overview section. The amplifier has a maximum
gain of +20 dB (Code 0) to −11.5 dB (Code 63).
The noise figure of the amplifier is approximately 7.5 dB at the
maximum gain setting, and it increases as the gain is reduced.
The increase in noise figure is equal to the reduction in gain.
The linearity of the part, measured at the output, is first-order
independent of the gain setting. From −4 dB to +20 dB gain,
the OIP3 is approximately 50 dBm into a 150 Ω load at 200 MHz
(0 dBm per tone). At gain settings below −4 dB, the OIP3 drops
to approximately 40 dBm.
Rev. 0 | Page 17 of 28
ADL5201
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
To enable the ADL5201, the PWUP pin must be pulled high
(1.4 V ≤ PWUP ≤ 3.3 V). Taking PWUP low puts the ADL5201
in sleep mode, reducing current consumption to approximately
7 mA at ambient temperature.
Figure 53 shows the basic connections for operating the ADL5201.
A voltage between 4.5 V and 5.5 V should be applied to the
VPOS pins. Each supply pin should be decoupled with at least
one low inductance, surface-mount ceramic capacitor of 0.1 μF,
placed as close as possible to the device.
ADC DRIVING
The outputs of the ADL5201 must be pulled up to the positive
supply with 1 μH RF chokes. The differential outputs are biased
to the positive supply and require ac coupling capacitors, preferably
0.1 μF. Similarly, the input pins are at bias voltages of about 1.6 V
above ground and should be ac-coupled, as well. The ac coupling
capacitors and the RF chokes are the principle limitations for
operation at low frequencies.
The ADL5201 is a highly linear, variable gain amplifier that
is optimized for ADC interfacing. The output IMDs and noise
floor remain constant throughout the 31.5 dB gain range. This
is a valuable feature in a variable gain receiver, where it is
desirable to maintain a constant instantaneous dynamic range
as the receiver range is modified. The output noise is 15 nV/√Hz,
which is compatible with 14- or 16-bit ADCs. The two-tone
IMDs are usually greater than −100 dB for −1 dBm into 150 Ω
or 2 V p-p output. The 150 Ω output impedance makes the task
of designing a filter for the high input impedance ADCs more
straightforward.
The digital pins (mode control pins, associated SPI and parallel
gain control pins, PM, and PWUP) operate on a voltage of 3.3 V.
0.1µF
0.1µF
0.1µF
+VPOS
0.1µF
0.1µF
RS
2
BALANCED
AC
SOURCE
RS
2
24
23
22
21
20
19
VPOS
VPOS
VPOS
PM
PWUP
3.3V
VPOS
3.3V
10µF
1µH
1 GND
VPOS 18
2 VIN+
VOUT– 17
0.1µF
0.1µF
0.1µF
3 VIN–
VOUT+ 16
ADL5201
4 GND
VOUT– 15
5 MODE1
VOUT+ 14
RL
1µH
BALANCED
LOAD
0.1µF
GS1/CS/A3
GS0/FA/A2
UPDN_CLK/A1
UPDN_DAT/A0
7
8
9
10
11
12
6 MODE0
LATCH 13
GAIN CONTROL INTERFACE
Figure 53. Basic Connections
Rev. 0 | Page 18 of 28
09388-052
SCLK/A4
MODE0
SDIO/A5
GAIN MODE INTERFACE
Data Sheet
ADL5201
5V
5V
1:3
1µH
0.1µF
VREF
0.1µF
75Ω
ADL5201
50Ω
47nH
75Ω
AC
AD9467
14pF
33Ω
VREF
47nH
0.1µF
0.1µF
33Ω
1µH
09388-053
DIGITAL
INTERFACE
5V
Figure 54. Wideband ADC Interfacing Example Featuring the ADL5201 and the AD9467
–15
–30
–45
–60
–75
–1
–105
–2
–120
–3
–135
–4
–150
–5
5
0
15
30
45
2 +
60
6
75
90
4
105
120
FREQUENCY (MHz)
–6
09388-055
3
–90
Figure 56. Measured Single-Tone Performance of the Circuit Shown
in Figure 54 for a 100 MHz Input Signal
–7
–8
The two-tone 100 MHz IMDs of two 1 V p-p signals have
an SFDR of greater than 91 dBc, as shown in Figure 57.
–9
–10
–11
FUND1 = –6.682dBFS
FUND2 = –7.096dBFS
2f1 – f2 = –93.2dBFS
2f2 – f1 = –92.58dBc
NOISE FLOOR = –115.3dBFS
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
Figure 55. Measured Frequency Response of the Wideband
ADC Interface Shown in Figure 54
Figure 54 uses a 1:3 impedance transformer to provide the
150 Ω input impedance of the ADL5201 with a matched input.
The outputs of the ADL5201 are biased through the two 1 μH
inductors, and the two 0.1 μF capacitors on the outputs decouple
the 5 V inductor voltage from the input common-mode voltage
of the AD9467. The two 75 Ω resistors provide the 150 Ω load to
the ADL5201, whose gain is load dependent. The 47 nH inductors and 14 pF capacitor constitute the (100 MHz − 1 dB) low-pass
filter. The two 33 Ω isolation resistors suppress any switching
currents from the ADC input sample-and-hold circuitry. The
circuit depicted in Figure 54 provides variable gain, isolation,
filtering, and source matching for the AD9467. By using this
circuit with the ADL5201 in a gain of 20 dB (maximum gain),
an SNR of 68 dB and an SFDR performance of 88 dBc are
achieved at 100 MHz, as shown in Figure 56.
–15
–30
AMPLITUDE (dBFS)
0
09388-054
0
–12
Rev. 0 | Page 19 of 28
–45
–60
–75
2f1 + f2
–90
2f2 – f1
+
2f2 + f1 f1 + f2
f2 – f1
–105
2f1 – f2
–120
–135
–150
0
15
30
45
60
75
90
105
FREQUENCY (MHz)
Figure 57. Measured Two-Tone Performance of the
Circuit Shown in Figure 54 for a 100 MHz Input Signal
120
09388-056
INSERTION LOSS (dB)
0
SNR = 68dB
SFDR = 88dBc
NOISE FLOOR = –114dBFS
FUND = –1.05dBFS
SECOND = –94.7dBc
THIRD = –88.75dBc
0
AMPLITUDE (dBFS)
Figure 54 shows the ADL5201 driving a two-pole, 100 MHz, lowpass filter into the AD9467. The AD9467 is a 16-bit, 200 MSPS
to 250 MSPS ADC with a buffered wideband input that presents
a 530 Ω differential input impedance and requires a 2 V or 2.5 V
input swing to reach full scale. For optimum performance, the
ADL5201 should be driven differentially, using an impedance
transformer or input balun.
ADL5201
Data Sheet
An alternative narrow-band approach is presented in Figure 58.
By designing a narrow band-pass antialiasing filter between the
ADL5201 and the target ADC, the output noise of the ADL5201
outside the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves by several decibels (dB) when a reasonable order
antialiasing filter is included. In this example, a low loss 1:3
input transformer is used to match the 150 Ω balanced input
of the ADL5201 to a 50 Ω unbalanced source, resulting in
minimum insertion loss at the input.
the target center frequency. In addition, the L6 inductor shorts
the ADC inputs at dc, which introduces a zero into the transfer
function. The ac coupling capacitors and the bias chokes introduce
additional zeros into the transfer function. The final overall frequency response takes on a band-pass characteristic, helping to
reject noise outside of the intended Nyquist zone. Table 8 provides
initial suggestions for prototyping purposes. Some empirical
optimization may be needed to help compensate for actual PCB
parasitics.
Figure 58 shows the ADL5201 optimized for driving some of
the popular unbuffered Analog Devices ADCs: the AD9246,
AD9640, and AD6655. Table 8 includes antialiasing filter
component recommendations for popular IF sampling center
frequencies. Inductor L5 works in parallel with the on-chip
ADC input capacitance and a portion of the capacitance
presented by C4 to form a resonant tank circuit. The resonant tank
helps to ensure that the ADC input looks like a real resistance at
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
To minimize the parasitic capacitance, a good practice is to avoid
any ground or power planes under this routing region and under
the chokes.
LAYOUT CONSIDERATIONS
5V
5V
1:3
1µH
1nF
1nF
L1
ADL5201
50Ω
C2
L3
L5
C4
CML
75Ω
75Ω
AC
1nF
1nF
L1
L3
L6
AD9246
AD9640
AD6655
L5
1µH
09388-057
DIGITAL
INTERFACE
5V
Figure 58. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications
Table 8. Interface Filter Recommendations for Various IF Sampling Center Frequencies
Center Frequency
(MHz)
96
140
170
211
1 dB Bandwidth
(MHz)
27
31
25
40
L1 (nH)
68
47
39
30
C2 (pF)
15
11
10
7
Rev. 0 | Page 20 of 28
L3 (nH)
220
150
120
100
C4 (pF)
15
11
10
7.5
L5 (nH)
68
47
47
30
L6 (nH)
150
82
51
43
Data Sheet
ADL5201
EVALUATION BOARD
EVALUATION BOARD CONTROL SOFTWARE
The ADL5201 evaluation board is configured with a USB-friendly
interface to program the gain of the ADL5201. The software
graphical user interface (see Figure 59) lets users select a particular
gain mode and gain level to write to the device. The GUI also
allows users to read back data from the SDIO pin, showing the
currently programmed gain setting. The software setup files can be
downloaded from the ADL5201 product page at www.analog.com.
09388-058
The ADL5201 evaluation board is available with software to
program the variable gain control. It is a 4-layer board with a split
ground plane for analog and digital sections. Special care is
taken to place the power decoupling capacitors close to the
device pins. The board is designed for easy single-ended
(through a Mini-Circuits TC3-1T+ RF transformer) or
differential configuration for each channel.
Figure 59. Evaluation Board Control Software
Rev. 0 | Page 21 of 28
Figure 60. Evaluation Board Schematic
Rev. 0 | Page 22 of 28
1
2
3
MODE0
AGND
2 3 4 5
1
2
3
R1 3.3V
1kΩ
AGND
AGND
1 T2
0.1µF
C1
TCM3-1T+
3
2
AGND
PWUP
AGND
3.3V
1kΩ
R6
PA6
PM
1kΩ
1
2
3
3.3V
PB1
R11
TBD0402
0
R13
R10
TBD0402
0
AGND
R8
MOLEX22-03-2031
1
2
3
R7 3.3V
1kΩ
PA5
AGND
MOLEX22-03-2031
1
2
3
LATCH
1kΩ
3.3V
1kΩ
R2
REMOVE PLANE UNDER TRACES
R4
TBD0402
R5
4
6
AGND
JOHNSON142-0701-851
PWRUP
1
R3
0Ω
MOLEX22-03-2031
MOLEX22-03-2031
MODE1
AGND
2 3 4 5
J1 1
AGND
2 3 4 5
INB1
R12
R9
TBD0402
AGND
AGND
0.1µF
3.3V
1 YEL
AGND
1kΩ
R14 3.3V
AGND
C2
10µF
C4
0.1µF
AGND
DNI
1kΩ
R17
PA0
AGND
AGND
1
2
3
VOUT_POS 14
16
VOUT_POS
VOUT_NEG 15
17
VOUT_NEG
UPDN_DAT_A0 12
UPDN_CLK_A1 11
10
GS0_FA_A2
9
GS1_CS_N_A3
SCLK_A4 8
SDIO_A5 7
U1
C5
0.1µF
VPOS
R18
C6
1kΩ
TBD0402
DNI
AGND
SIDO/A5
PA7
13 LATCH
19 PWUP
20 PM
2
VIN_POS
3 VIN_NEG
5 MODE1
6 MODE0
C3
0.1µF
R16
TBD0402
1kΩ
R15
PWUP
PM
VPOS
RED
VPOS
LATCH
MODE0
MODE1
75Ω TRACES
NP
AGND
1 BLK
C17
VPOS_ID 21
VPOS_IG 22
18
23
24
1 GND
4 GND_ZAP
PAD PAD
1
A5
GS1/CS/A3
AGND
DNI
MOLEX22-03-2031
R21
TBD0402
GSO/FA/A2
UPDN_CLK/A1
UPDN_DAT/A0
C10
1kΩ
R22
0.1µF
C11
0.1µF
AGND
C8
TBD0402
DNI
3.3V
1µH
C9
0.1µF
C7
0
0.1µF
R24
L2
VXB
1 RED
0
L1
1µH
VXA
1 RED
R51
AGND
R20 0Ω
SCLK/A4
R19 0Ω
VPOS
PA1
R23
1kΩ
AGND
1
2
3
MOLEX22-03-2031
AGND
R29
TBD0402
A4
TBD0402
TBD0402
R30
TBD0402
AGND
C12
0.1µF
TBD0402
3
4
TCM3-1T+
R28
TBD0402
6
0Ω
2
T1 1
AGND
R27
TBD0402
R25
0Ω
R26
AGND
VPOS
AGND
R33
DNI
AGND
R32
DNI
AGND
R31
DNI
AGND
DNI
VPOS
R36
R43
1kΩ
AGND
C16
TBD0402
DNI
3.3V
AGND
1kΩ
R38
C15
TBD0402
DNI
AGND
3.3V
1kΩ
1kΩ
C14
TBD0402
DNI
3.3V
AGND
C13
TBD0402
DNI
3.3V
R34
PA2
R46
1kΩ
PA3
R42
1kΩ
PA4
R37
1kΩ
PB0
R35
1kΩ
AGND
AGND
AGND
AGND
5 4 3 2
AGND
AGND
A3
1
2
3
MOLEX22-03-2031
A2
1
2
3
MOLEX22-03-2031
A1
1
2
3
MOLEX22-03-2031
A0
1
AGND
2
3
MOLEX22-03-2031
TBD0402
0Ω
R47
50Ω TRACES
5 4 3 2
OUTB–
ADL5201
Data Sheet
SCHEMATICS AND ARTWORK
09388-059
ADL5201
09388-060
Data Sheet
Figure 62. Top Layer
09388-062
09388-061
Figure 61. Logic Schematic
Figure 63. Bottom Layer
Rev. 0 | Page 23 of 28
ADL5201
Data Sheet
EVALUATION BOARD CONFIGURATION OPTIONS
Configuration Options for the Main Section
Table 9. Bill of Materials for Main Section
Components
C2 to C5, C7, C9, C17
U1
INB−
T2
J1
C1
R3, R4, R9 to R13
T1
C10 to C12
L1, L2
R19, R20, R24 to R28,
R47, R48, R51
OUTB+, OUTB−
PWUP, PWRUP
A0 to A5
LATCH
PM
MODE0, MODE1
R1, R2, R5 to R8,
R14 to R18, R21 to R23,
R30 to R38, R42, R43, R46
C6, C8, C13 to C16
Function
Power supply decoupling. Nominal supply decoupling consists of
a 0.1 μF capacitor to ground.
Device under test.
Input interface. INB− is the RF input. T2 is a 3:1 impedance ratio balun
used to transform a single ended 50 Ω signal into a 150 Ω balanced
differential signal. The input can be configured for a differential by
removing R3 and installing a 0 Ω jumper at R4.
C1 provides dc blocking. R12 and R13 are placeholders and can be
replaced with blocking capacitors when driving the ADL5201 from
a fully differential source.
R3 grounds one side of the differential drive interface for single-ended
applications. R9, R10, and R11 are provided for generic placement of
matching components.
Output interface. T1 is a 3:1 impedance ratio balun used to transform
a 150 Ω balanced differential signal to a 50 Ω singled-end signal.
C10 and C11 are dc blocks.
L1 and L2 provide dc bias to the open-collector output.
R24 to R28 are provided for the generic placement of matching
components. R47 grounds one side of the differential output interface
for single-ended applications.
Power-up interface. The ADL5201 is powered up by applying a logic
high (1.4 V ≤ PWUPA/B ≤ 3.3 V) to PWUP from an external source or by
installing a shunt between Pin 1 and Pin 2 of the 3-pin header, PWUP.
Gain control interface. All of the gain control functions are fully
controlled via the USB microcontroller using the supplied software.
Three-pin headers allow for manual operation of the gain control, if
desired.
R1, R2, R5 to R8, R14, R15, R17, R18, R22, R23, R34 to R38, R42, R43, and
R46 isolate the digital control pins from the microcontroller and
provide current limiting.
The R16, R21, and R30 to R33 resistors and the C6, C8, and C13 to C16
capacitors allow for the generic placement of filter components.
Rev. 0 | Page 24 of 28
Default Conditions
C2 = 10 μF (Size C7343)
C3 to C5, C7, C9, C17 = 0.1 μF (Size 0603)
Installed
T2 = TC3-1T+ (Mini-Circuits)
C1 = 0.1 μF (Size 0402)
R3, R12, R13 = 0 Ω (Size 0402)
R4, R9 to R11 = open
INB− (SMA connector) installed
J1 (SMA connector) installed
T1 = TC3-1T+ (Mini-Circuits)
C10 to C12 = 0.1 μF (Size 0402)
R19, R20, R24 to R26, R47, R51 = 0 Ω
(Size 0402)
R27, R28, R48 = open
L1, L2 = 1 μH (Size 0805)
OUTB+ (SMA connector) installed
OUTB− (SMA connector) installed
PWUP (3-pin header) installed
PWRUP (SMA connector) installed
A0 to A5 (3-pin header) installed
LATCH (3-pin header) installed
MODE0 (3-pin header) installed
MODE1 (3-pin header) installed
PM (3-pin header) installed
R1, R2, R5 to R8, R14, R15, R17, R18,
R22, R23, R34 to R38, R42, R43, R46 =
1 kΩ (Size 0402)
R16, R21, R30 to R33 = open
C6, C8, C13 to C16 = open
Data Sheet
ADL5201
Configuration Options for the USB Section
Table 10. Bill of Materials for USB Section
Components
C31, C62
C49
C28 to C30, C53 to C55, C57 to C61
C47, C50
C52, C56
D6
J16
R39, R49, R50
R41
R40
R44, R45
R58
U6
U7
U5
Y2
Default Conditions
22 pF (Size 0603)
1000 pF (Size 0603)
0.1 μF (Size 0402)
1 μF (Size 0402)
10 pF (Size 0402)
Green LED (Panasonic LNJ308G8TRA)
USB SMT connector (Hirose Electric UX60A-MB-5ST 240-0003-4)
2 kΩ (Size 0603)
78.7 kΩ (Size 0603)
140 kΩ (Size 0603)
100 kΩ (Size 0603)
0 Ω (Size 0603)
USB microcontroller (Cypress CY7C68013A-56LFXC)
64 kbit EEPROM (Microchip 24LC64-I/SN)
Low dropout regulator (Analog Devices ADP3334ACPZ)
24 MHz crystal oscillator (AEL Crystals X24M000000S244)
Rev. 0 | Page 25 of 28
ADL5201
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
6
7
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
112108-A
0.20 REF
Figure 64. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5201ACPZ-R7
ADL5201-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
24 Lead LFCSP_WQ, 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Package Option
CP-24-7
Data Sheet
ADL5201
NOTES
Rev. 0 | Page 27 of 28
ADL5201
Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09388-0-10/11(0)
Rev. 0 | Page 28 of 28
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