Austin AS8SLC512K32Q-12L/883C 512k x 32 sram sram memory array mcm Datasheet

SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
512K x 32 SRAM
PIN ASSIGNMENT
(Top View)
SRAM Memory Array MCM
NC
A0
A1
A2
A3
A4
A5
CE\3
GND
CE\4
WE\1
A6
A7
A8
A9
A10
Vcc
68 Lead CQFP (Q & Q1)
FEATURES
Fast access times: 10, 12, 15, 17 and 20ns
Fast OE\ access times: 6ns
Ultra-low operating power < 1W worst case
Single +3.3V ±0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Easy memory expansion with CE\ and OE\ options
Automatic CE\ power down
High-performance, low-power consumption, CMOS
OPTIONS
•
•
•
•
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
10
59
11
12
58
57
13
14
56
55
15
54
16
53
17
52
18
51
19
50
20
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
MARKINGS
Timing
10ns
12ns
15ns
17ns
20ns
66 Lead PGA (P)
-10
-12
-15
-17
-20
Package
Ceramic Quad Flatpack
Q
Ceramic Quad Flatpak(.054min SO) Q1
Pin Grid Array
P
Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
2V data retention/low power
L
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
Vcc
A11
A12
A13
A14
A15
A16
CE\1
OE
CE\2
A17
WE\2
WE\3
WE\4
A18
NC
NC
•
•
•
•
•
•
•
•
•
CS
No. 702
CS
\
No.904
CS
CS
M4
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8SLC512K32 is a 3.3V
16 Megabit CMOS SRAM Module organized as 512Kx32 bits. The
AS8SLC512K32 achieves very high speed access, low power
consumption and high reliability by employing advanced CMOS
memory technology.
This military temperature grade product is ideally suited for
commercial, industrial, and military applications when asynchronous high
speed switching and low ACTIVE opening power & ultra Fast Asynchronous Access is mandated.
M3
M2
M1
For more products and information
please visit our web site at
www.austinsemiconductor.com
BLOCK DIAGRAM
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
This is a stress rating only and functional operation on the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow. See the Application Information section at the end of this datasheet for
more information.
Voltage of Vcc Supply Relative to Vss...........-0.5V to +4.6V
Storage Temperature.....................................-65°C to +150°C
Short Circuit Output Current(per I/O)............................20mA
Voltage on Any Pin Relative to Vss............-.5V to Vcc+4.6V
Maximum Junction Temperature**.............................+150°C
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < 125oC and -40oC to +85oC; Vcc = 3.3V ±0.3V)
DESCRIPTION
Input High (logic 1) Voltage
CONDITIONS
SYMBOL
VIH
MIN
2.2
VCC+0.3
V
1
VIL
-0.3
0.8
V
1
ILI1
-10
10
µA
ILI2
-10
10
µA
Output(s) Disabled
0V<VOUT<VCC
ILO
-10
10
µA
Output High Voltage
IOH=-4.0mA
VOH
2.4
Output Low Voltage
IOL=8.0mA
VOL
Input Low (logic 1) Voltage
Input Leakage CurrentADD,OE
0V<VIN<VCC
Input Leakage CurrentWE,CE
Output Leakage CurrentI/O
DESCRIPTION
CONDITIONS
SYMBOL
MAX
UNITS NOTES
0.5
-10
-12
MAX
-15
-17
-20
350
320
280
260
240
280
240
200
180
160
---
---
---
---
---
120
80
80
80
80
---
---
---
---
---
80
40
40
40
40
100
80
80
80
80
80
60
60
60
60
80
60
60
60
60
50
36
36
36
36
V
1
V
1
UNITS NOTES
CS\<VIL; VCC = MAX
High Speed
f = MAX = 1/ tRC (MIN)
Power Supply
Outputs
Open, OE\ = VIH
Current: Operating
ICC1
Low Power (L)
Low Speed
Power Supply
Current: Operating
Low Speed
Power Supply
Current: Operating
CS\<VIL; VCC = MAX
f = 10 MHz, OE\ = VIH
ICC2
Low Power (L)
CS\<VIL; VCC = MAX
f = 1 MHz, OE\ = VIH
ICC3
Low Power (L)
mA
2, 3,13
mA
2
mA
2
mA
3, 13
CS\>VIH; VCC = MAX
Power Supply
Current: Standby
f = MAX = 1/ tRC (MIN)
Outputs Open, OE\=VIH
ISBT1
Low Power (L)
CMOS Standby
VIN = VCC - 0.2V, or VSS
+0.2V
VCC=Max; f = 0Hz
Low Power (L)
AS8SLC512K32
Rev. 2.5 5/09
ISBT2
mA
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
AS8SLC512K32
CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)*
SYMBOL
CADD
COE
CWE, CCS
CIO
PARAMETER
A0 - A18 Capacitance
OE\ Capacitance
WE\ and CS\ Capacitance
I/O 0- I/O 31 Capacitance
MAX
40
40
12
15
UNITS
pF
pF
pF
pF
NOTE:
*This parameter is sampled.
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels...........................................VSS to 3V
Input rise and fall times...........................................1ns/V
Input timing reference levels...............................1.5V
Output reference levels........................................1.5V
Output load..........................................See Figure 1, 2
3.3V
RL = 50Ω
ZO = 50Ω
319Ω
VL = 1.5V
Q
30 pF
Q
5 pF
333Ω
FIGURE 1
AS8SLC512K32
Rev. 2.5 5/09
FIGURE 2
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTE 5) (-55oC<TA < 125oC and -40oC to +85oC; VCC = 3.3V ±0.3V)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip select access time
Output hold from address change
Chip select to output in Low-Z
Chip select to output in High-Z
Output enable access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip select to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width, CS\ controlled
WRITE pulse width, WE\ controlled
Data setup time
Data hold time
Write disable to output in Low-z
Write enable to output in High-Z
AS8SLC512K32
Rev. 2.5 5/09
SYMBOL
t
RC
AA
t
ACS
t
OH
t
LZCS
t
HZCS
t
AOE
t
LZOE
t
HZOE
-10
MIN MAX
10
t
t
WC
CW
t
AW
t
AS
t
AH
t
WP1
t
WP2
t
DS
t
DH
t
LZWE
t
HZWE
t
-12
MIN MAX
12
15
10
10
1
1
0
0
12
12
2
2
5
5
6
6
0
0
0
0
6
12
8
8
0
0
10
10
6
1
2
5
-17
MIN MAX
17
15
15
2
2
5
10
7
7
0
0
9
9
5
1
2
5
-15
MIN MAX
20
17
17
2
2
7
7
20
20
2
2
7.5
7.5
0
7
15
10
10
0
0
12
12
7
1
2
6
-20
UNITS NOTES
MIN MAX
0
0
7.5
17
11
11
0
0
14
14
7.5
1
2
6.5
8
8
8
20
12
12
0
0
15
15
8
1
2
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,6,7
4,6,7
4,6
4,6
4,6,7
4,6,7
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
LOW POWER CHARACTERISTICS (L Version Only)
CONDITIONS
DESCRIPTION
VCC for Retention Data
Data Retention Current
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
CS\ = Vcc + 0.2V
SYMBOL
VDR
MIN
2
MAX
UNITS
V
VCC = 2V
ICCDR
24
mA
VCC = 3V
ICCDR
32
mA
Chip Deselect to Data
Retention Time
NOTES
tCDR
0
ns
4
tR
20
ms
4, 11
Operation Recovery Time
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
t
t
CDR
CS\ 1-4
123456789012345678
12345
123456789012345678
12345
12345678
12345
123456789012345678
12345678
12345
12345678
123456789012345678
12345
12345678
123456789012345678
12345
12345678
123456789012345678
12345
12345678
123456789012345678
12345
12345678
123456789012345678
12345
123456789012345678
VDR
R
123456789012345678
12345
123456789012345678
12345
12345678
123456789012345678
12345678
12345
123456789012345678
12345678
12345
123456789012345678
12345678
12345
123456789012345678
12345678
12345
12345678
12345
123456789012345678
123456789012345678
12345678
12345
123456789012345678
12345
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. ICC is for full 32 bit mode.
1
t RC(MIN) HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
READ CYCLE NO. 1
tRC
ADDRESS
tAA
tOH
DATA I/O
PREVIOUS DATA VALID
12345
1234567
12345
12345
1234567
12345
12
12
12345
12345
1234567
12
12
12345
1234567
12
12345
12
12345
1234567
12345
12
12
NEW DATA VALID
READ CYCLE NO. 2
tRC
ADDRESS
12345
1234
123456789
1234
12345
123456789
12345
1234
123456789
CS\ 12345
1234
123456789
12345
1234
123456789
tAA
12345678
1234567
123456
12345678
1234567
123456
1234567
123456
12345678
12345678
1234567
123456
1234567
123456
12345678
t
tLZCS ACS
t
12345
1234
1234567890123
1234
12345
1234567890123
1234
1234567890123
OE\12345
1234567890123
12345
1234
DATA I/O
AS8SLC512K32
Rev. 2.5 5/09
HZCS
12345678901
1234567
123456
12345678901
1234567
123456
12345678901
1234567
123456
12345678901
1234567
123456
tAOE 123456
1234
12
12345
11
tLZOE
123456
1234
12
12345
123456
1234
12
12345
11
123456
1234
12
12345
HIGH IMPEDANCE
tHZOE
DATA VALID
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1
(Chip Select Controlled)
tWC
ADDRESS
tAS
123456
123456
123456
123456
123456
123456789
123456789
WE\ 123456789
123456789
CS\
tAW
tAH
tCW
1234567890123
1234567
123456
1234567890123
1234567
123456
1234567
123456
1234567890123
1234567890123
1234567
123456
tWP21
tDS
DATA I/O
tDH
DATA VALID
WRITE CYCLE NO. 2
(Write Enable Controlled)
tWC
ADDRESS
1234
12345
123456789
1234
12345
123456789
12345
1234
123456789
1234
123456789
CS\ 12345
1234
12345
123456789
tAS
WE\
t AW
tAH 1234567
1234567890123
123456
1234567890123
1234567
123456
1234567
123456
1234567890123
1234567890123
1234567
123456
1234567890123
1234567
123456
tCW
t WP1 1
12345
12345
12345
12345
tHZWE
12345678901234
1
11234
1
12345678901234
11234
1
11234
DATA I/O 12345678901234
tDS
tLZWE
tDH
DATA VALID
1234
1234
123
1234
1234
123
1234
1234
123
NOTES
1. All voltages referenced to VSS (GND).
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #702 (Package Designator Q)
4 x D2
4 x D1
D
DETAIL A
R
b
1o - 7o
B
L1
e
SEE DETAIL A
A1
A
A2
E
SYMBOL
A
A1
A2
B
b
D
D1
D2
E
e
R
L1
SMD SPECIFICATIONS
MIN
MAX
0.123
0.196
0.118
0.186
0.000
0.020
0.010 REF
0.013
0.017
0.800 BSC
0.870
0.890
0.980
1.000
0.936
0.956
0.050 BSC
0.005
--0.035
0.045
*All measurements are in inches.
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P)
4xD
D1
A
D2
Pin 56
A1
Pin 1
φb1
(identified by
0.060 square pad)
E1
e
φb
Pin 66
e
Pin 11
L
SMD SPECIFICATIONS
SYMBOL
A
A1
φb
φb1
D
D1/E1
D2
e
L
MIN
0.144
0.025
0.016
0.045
1.065
MAX
0.181
0.035
0.020
0.055
1.085
1.000 TYP
0.600 TYP
0.100 TYP
0.145
0.155
*All measurements are in inches.
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc.
AS8SLC512K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator Q1)
Case Outline A
SYMBOL
A
A1
b
B
c
D/E
D1/E1
D2/E2
e
L
R
SMD SPECIFICATIONS
MIN
MAX
--0.196
0.054
--0.013
0.017
0.010 TYP
0.009
0.012
0.980
1.000
0.870
0.890
0.800 BSC
0.050 BSC
0.035
0.045
0.010 TYP
*All measurements are in inches.
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
SRAM
AS8SLC512K32
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS8SLC512K32Q-17L/XT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
Q
Q
Q
Q
Q
Speed
ns
-10
-12
-15
-17
-20
Options Process
L
L
L
L
L
/*
/*
/*
/*
/*
EXAMPLE: AS8SLC512K32P-12/IT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
P
P
P
P
P
Speed
ns
-10
-12
-15
-17
-20
Options Process
L
L
L
L
L
/*
/*
/*
/*
/*
EXAMPLE: AS8SLC512K32Q1-12/XT
Device Number
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
AS8SLC512K32
Package
Type
Q1
Q1
Q1
Q1
Q1
Speed
ns
-10
-12
-15
-17
-20
Options Process
L
L
L
L
L
/*
/*
/*
/*
/*
*AVAILABLE PROCESSES
XT = Extended Temperature Rang
IT = Industrial Temperature Range
883C = Military Processing
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
OPTION DEFINITIONS
L = 2V data retention/low power
AS8SLC512K32
Rev. 2.5 5/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
SRAM
Austin Semiconductor, Inc.
AS8SLC512K32
DOCUMENT TITLE
512K x 32 SRAM SRAM Memory Array MCM
REVISION HISTORY
Rev #
2.5
AS8SLC512K32
Rev. 2.5 5/09
History
Updated Q & Q1 Package Specs
Page 8 & 10
Release Date
May 2009
Status
Release
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
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