Sharp LH28F160BG-TL 16 m-bit (1 mb x 16) smart 3 flash memory Datasheet

LH28F160BG-TL/BGH-TL
LH28F160BG-TL/BGH-TL
16 M-bit (1 MB x 16) Smart 3
Flash Memories
DESCRIPTION
Y
R
A
L
FEATURES
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM-compatible write interface
• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Thirty-one 32 k-word main blocks
– Top or bottom boot location
• Enhanced cycling capability
– 100 000 block erase cycles
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Packages
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend/Reverse bend
– 60-ball CSP (FBGA060/048-P-0811)
IN
IM
The LH28F160BG-TL/BGH-TL flash memories with
Smart 3 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F160BG-TL/
BGH-TL can operate at VCC and VPP = 2.7 V.
Their low voltage operation capability realizes
longer battery life and suits for cellular phone
application. Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F160BG-TL/BGH-TL offer two levels of
protection : absolute protection with VPP at GND,
selective hardware boot block locking. These
alternatives give designers ultimate control of their
code security needs.
• Smart 3 technology
– 2.7 to 3.6 V VCC
– 2.7 to 3.6 V or 12 V VPP
• High performance read access time
LH28F160BG-TL10/BGH-TL10
– 100 ns (2.7 to 3.6 V)
LH28F160BG-TL12/BGH-TL12
– 120 ns (2.7 to 3.6 V)
P
R
E
∗ ETOX is a trademark of Intel Corporation.
COMPARISON TABLE
VERSIONS
LH28F160BG-TL
LH28F160BGH-TL
LH28F160BV-TL∗
LH28F160BVH-TL∗
BIT CONFIGURATION
1 MB x 16
OPERATING TEMPERATURE
0 to +70°C
1 MB x 16
–25 to +85°C
2 MB x 8/1 MB x 16
2 MB x 8/1 MB x 16
0 to +70°C
–40 to +85°C
∗ Refer to the datasheet of LH28F160BV-TL/BVH-TL.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F160BG-TL/BGH-TL
PIN CONNECTIONS
48-PIN TSOP (Type I)
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
Y
47
3
R
48
2
A
1
28
21
27
22
26
23
25
24
IN
A15
A14
A13
A12
A11
A10
A9
A8
NC
RY/BY#
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
TOP VIEW
(TSOP048-P-1220)
NOTE :
IM
Reverse bend available on request.
60-BALL CSP
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A14
A13
A15
A16
GND
NC
NC
NC
NC
A11
A10
A12
DQ15
DQ14
DQ7
C
A8
NC
A9
DQ6
DQ5
DQ13
D
WE#
RP#
RY/BY#
DQ12
VCC
DQ4
E
WP#
VPP
A19
DQ10
DQ11
DQ3
F
A17
A18
A7
DQ1
DQ2
DQ9
G
A5
A6
A4
OE#
DQ8
DQ0
A2
A3
A1
A0
GND
CE#
NC
NC
NC
L
A NC
P
R
E
B
H NC
NC
NC
(FBGA060/048-P-0811)
-2-
LH28F160BG-TL/BGH-TL
BLOCK ORGANIZATION
Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.
This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.
Y
Boot Blocks : The two boot blocks are intended to
replace a dedicated boot PROM in a microprocessor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the VPP, RP# and
WP# pins.
A
R
Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 16 M-bit
device contains thirty-one 32 k words (32 768
words) blocks.
IN
BLOCK DIAGRAM
DQ0-DQ15
ADDRESS
COUNTER
IM
CE#
WE#
OE#
RP#
WP#
COMMAND
USER
INTERFACE
DATA
MAIN BLOCKS
-3-
MAIN BLOCK 30
31
32 k-WORD
MAIN BLOCK 29
MAIN BLOCK 1
RY/BY#
WRITE
Y GATING
MAIN BLOCK 0
X
VCC
COMPARATOR
Y
DECODER
DECODER
DATA
REGISTER
REGISTER
STATUS
BOOT BLOCK 0
BOOT BLOCK 1
PARAMETER BLOCK 0
PARAMETER BLOCK 1
PARAMETER BLOCK 2
PARAMETER BLOCK 3
PARAMETER BLOCK 4
PARAMETER BLOCK 5
ADDRESS
LATCH
I/O
LOGIC
REGISTER
L
E
R
INPUT
BUFFER
P
A0-A19
INPUT
BUFFER
IDENTIFIER
MULTIPLEXER
OUTPUT
OUTPUT
BUFFER
STATE
PROGRAM/ERASE
MACHINE
VOLTAGE SWITCH
VPP
VCC
GND
LH28F160BG-TL/BGH-TL
PIN DESCRIPTION
SYMBOL
TYPE
A0-A19
INPUT
CE#
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
INPUT/
data during memory array, status register and identifier code read cycles. Data pins float
OUTPUT
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
INPUT
CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
Y
DQ0-DQ15
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
levels.
RP#
INPUT
OE#
INPUT
WE#
INPUT
WP#
INPUT
R
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. Block erase or word write with VIH <
A
RP# < VHH produce spurious results and should not be attempted.
IN
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot
blocks cannot be erased and programmed.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
RY/BY#
OUTPUT
IM
performing an internal operation (block erase or word write). RY/BY#-high-impedance
indicates that the WSM is ready for new commands, block erase is suspended, and
word write is inactive, word write is suspended, or the device is in deep power-down
SUPPLY
writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase and
word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce
spurious results and should not be attempted.
E
VPP
L
mode.
BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
SUPPLY
P
GND
SUPPLY
R
VCC
NC
DEVICE POWER SUPPLY : 2.7 to 3.6 V. Do not float any power pins. With VCC ≤
VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid
VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
and should not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
-4-
LH28F160BG-TL/BGH-TL
1 INTRODUCTION
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.
1.1
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (3.0 V
VCC and VPP), independent of other blocks. Each
block can be independently erased 100 000 times.
Block erase suspend mode allows system software
to suspend block erase to read data from, or write
data to any other block.
Y
This datasheet contains LH28F160BG-TL/BGH-TL
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160BG-TL/
BGH-TL flash memories documentation also
includes ordering information which is referenced in
Section 7.
New Features
R
Key enhancements of LH28F160BG-TL/BGH-TL
Smart 3 flash memories are :
A
• 2.7 V VCC and VPP Write/Erase Operation
• Enhanced Suspend Capabilities
• Boot Block Architecture
1.2
L
IM
• VPPLK has been lowered to 1.5 V to support
2.7 V block erase and word write operations.
Designs that switch VPP off during read
operations should make sure that the VPP
voltage transitions to GND.
• To take advantage of Smart 3 technology, allow
VPP connection to 2.7 V or 12 V.
Writing memory data is performed in word
increments of the device’s 32 k-word blocks
typically within 55 µs, 4 k-word blocks typically
within 60 µs (3.0 V VCC and VPP). Word write
suspend mode enables the system to read data
from, or write data to any other flash memory array
location.
IN
Note following important differences :
Product Overview
P
R
E
The LH28F160BG-TL/BGH-TL are high-performance
16 M-bit Smart 3 flash memories organized as
1 024 k-word of 16 bits. The 1 024 k-word of data
is arranged in two 4 k-word boot blocks, six 4 kword parameter blocks and thirty-one 32 k-word
main blocks which are individually erasable insystem. The memory map is shown in Fig. 1.
VPP at 2.7 V eliminates the need for a separate 12 V
converter, while VPP = 12 V maximizes block erase
and word write performance. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP ≤ VPPLK.
-5-
The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
LH28F160BG-TL/BGH-TL
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-High-impedance indicates that the WSM is
ready for a new command, block erase is
suspended (and word write is inactive), word write
is suspended, or the device is in deep power-down
mode.
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 3 mA at
2.7 V VCC.
Y
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
P
R
E
L
IM
IN
A
R
The access time is 100 ns or 120 ns (tAVQV) at the
VCC supply voltage range of 2.7 to 3.6 V over the
temperature range, 0 to +70°C (LH28F160BG-TL)/
–25 to +85°C (LH28F160BGH-TL).
-6-
LH28F160BG-TL/BGH-TL
Top Boot
Bottom Boot
P
IM
L
E
NOTES :
BLOCK CONFIGURATION
Top Boot
Bottom Boot
VERSIONS
LH28F160BG-TTL
LH28F160BGH-TTL
LH28F160BG-BTL
LH28F160BGH-BTL
Fig. 1 Memory Map
-7-
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0
R
Y
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Boot Block
4 k-Word Boot Block
A
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
D7FFF
D0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
IN
0
1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
4 k-Word Boot Block
4 k-Word Boot Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
4 k-Word Parameter Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
32 k-Word Main Block
R
FFFFF
FF000
FEFFF
FE000
FDFFF
FD000
FCFFF
FC000
FBFFF
FB000
FAFFF
FA000
F9FFF
F9000
F8FFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
LH28F160BG-TL/BGH-TL
2 PRINCIPLES OF OPERATION
software to suspend a word write to read data from
any other flash memory array location.
The LH28F160BG-TL/BGH-TL Smart 3 flash
memories include an on-chip WSM to manage
block erase and word write functions. It allows for :
fixed power supplies during block erasure and word
write, and minimal processor overhead with RAMlike interface timings.
2.1
R
Y
After initial device power-up or return from deep
power-down mode (see Table 1 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.
A
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase or word
write command sequences, provides protection
from unwanted operations even when high voltage
is applied to VPP. All write functions are disabled
when VCC is below the write lockout voltage VLKO
or when RP# is at VIL. The device’s blocks locking
capability provides additional protection from
inadvertent code or data alteration by gating erase
and word write operations.
IN
IM
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure and word writing. All functions
associated with altering memory contents—block
erase, word write, status and identifier codes—are
accessed via the CUI and verified through the
status register.
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases or word writes are required) or hardwired to
VPPH1/2. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
R
E
L
Commands are written using standard microprocessor write timings. The CUI contents serve as
input to the WSM, which controls the block erase
and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or
outputs status register data.
P
Interface software that initiates and polls progress
of block erase and word write can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read/write data from/to blocks other than that which
is suspended. Word write suspend allows system
-8-
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier
codes or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep powerdown mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
LH28F160BG-TL/BGH-TL
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase or
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ0-DQ15) control and when active drives
the selected memory data onto the I/O bus. WE#
must be at VIH and RP# must be at VIH or VHH.
Fig. 9 illustrates read cycle.
Output Disable
3.4
Deep Power-Down
3.5
R
Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.
Read Identifier Codes
The read identifier codes operation outputs the
manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms.
IN
3.3
Y
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins (DQ0-DQ15) are
placed in a high-impedance state.
A
3.2
IM
RP# at VIL initiates the deep power-down mode.
FFFFF
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
L
Reserved for
Future Implementation
R
E
00002
P
-9-
Device Code
00000
Manufacture Code
Fig. 2 Device Identifier Code Memory Map
3.6
During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
the reset operation is complete. Memory contents
being altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
after RP# goes to logic-high (VIH) before another
command can be written.
00001
Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
LH28F160BG-TL/BGH-TL
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 10 and
Fig. 11 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled.
Table 1 Bus Operations
Output Disable
Standby
3
3
VIH or VHH
VIH or VHH
Deep Power-Down
4
VIL
Read Identifier Codes
Write
8
VIH or VHH
3, 6, 7, 8 VIH or VHH
CE#
VIL
OE#
VIL
WE#
VIH
ADDRESS
X
VIL
VIH
VIH
X
VIH
X
X
X
X
X
High Z
High Z
X
X
High Z
High Z
X
X
X
X
VIL
VIH
See Fig. 2
X
VIL
VIH
VIL
X
X
IN
4.
5.
6.
7.
8.
E
L
IM
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2 voltages.
RY/BY# is VOL when the WSM is executing internal
block erase or word write algorithm. It is high-impedance
when the WSM is not busy, in block erase suspend
mode (with word write inactive), word write suspend
mode or deep power-down mode.
R
3.
RY/BY#
X
X
P
2.
DQ0-15
DOUT
VIL
NOTES :
1.
VPP
X
R
NOTE
RP#
1, 2, 3, 8 VIH or VHH
A
MODE
Read
Y
Device operations are selected by writing specific
commands into the CUI. Table 2 defines these
commands.
- 10 -
(NOTE 5) High Z
DIN
X
RP# at GND±0.2 V ensures the lowest deep powerdown current.
See Section 4.2 for read identifier code data.
VIH < RP# < VHH produce spurious results and should
not be attempted.
Refer to Table 2 for valid DIN during a write operation.
Don’t use the timing both OE# and WE# are VIL.
LH28F160BG-TL/BGH-TL
Table 2 Command Definitions (NOTE 7)
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
NOTE
REQ’D.
Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
1
≥2
Read Status Register
Clear Status Register
2
1
Block Erase
2
5
Write
BA
20H
Word Write
Block Erase and
2
5, 6
Write
WA
40H or 10H
1
5
Write
X
B0H
1
5
Write
X
D0H
Word Write Suspend
Block Erase and
Word Write Resume
4
Write
Write
X
X
FFH
90H
Write
Write
X
X
70H
50H
NOTES :
A
L
IM
7.
- 11 -
IA
ID
Read
X
SRD
Write
BA
D0H
Write
WA
WD
If the block is boot block, WP# must be at VIH or RP#
must be at VHH to enable block erase or word write
operations. Attempts to issue a block erase or word write
to a boot block while WP# is VIH or RP# is VIH.
Either 40H or 10H is recognized by the WSM as the
word write setup.
Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
IN
6.
E
4.
5.
R
3.
Bus operations are defined in Table 1.
X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.
SRD = Data read from status register. See Table 5 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.
P
1.
2.
Read
R
Read Array/Reset
Read Identifier Codes
Y
COMMAND
LH28F160BG-TL/BGH-TL
4.1
the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to VIH before further reads
to update the status register latch. The Read Status
Register command functions independently of the
VPP voltage. RP# can be VIH or VHH.
Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the VPP voltage and
RP# can be VIH or VHH.
Y
R
A
Read Identifier Codes Command
L
IM
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 3 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
E
Table 3 Identifier Codes
CODE
ADDRESS
Manufacture Code
00B0H
0068H
0069H
00001H
00001H
Read Status Register Command
P
4.3
R
Device Code (Top Boot)
Device Code (Bottom Boot)
DATA
00000H
The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 5). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or word write suspend modes.
IN
4.2
4.4
4.5
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
- 12 -
LH28F160BG-TL/BGH-TL
4.6
Word Write Command
R
E
L
P
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
R
Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to VOH.
Specification tWHRH2 defines the block erase
suspend latency.
A
IM
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.
4.7
IN
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when VCC =
VCC1 and VPP = VPPH1/2. In the absence of this
high voltage, block contents are protected against
erasure. If block erase is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to "1". Successful
block erase for boot blocks requires that the
corresponding if set, that WP# = VIH or RP# = VHH.
If block erase is attempted to boot block when the
corresponding WP# = VIL or RP# = VIH, SR.1 and
SR.5 will be set to "1". Block erase operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
Reliable word writes can only occur when VCC =
VCC1 and VPP = VPPH1/2. In the absence of this
high voltage, memory contents are protected
against word writes. If word write is attempted while
VPP ≤ VPPLK, status register bits SR.3 and SR.4 will
be set to "1". Successful word write for boot blocks
requires that the corresponding if set, that WP# =
VIH or RP# = VHH. If word write is attempted to
boot block when the corresponding WP# = VIL or
RP# = VIH, SR.1 and SR.4 will be set to "1". Word
write operations with VIH < RP# < VHH produce
spurious results and should not be attempted.
Y
The CUI remains in read status register mode until
a new command is issued.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to VOL.
However, SR.6 will remain "1" to indicate block
erase suspend status.
- 13 -
LH28F160BG-TL/BGH-TL
automatically outputs status register data when read
(see Fig. 6). VPP must remain at VPPH1/2 (the same
VPP level used for word write) while in word write
suspend mode. RP# must also remain at VIH or
VHH (the same RP# level used for word write). WP#
must also remain at VIL or VIH (the same WP# level
used for word write).
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). VPP must remain at VPPH1/2 (the
same VPP level used for block erase) while block
erase is suspended. RP# must also remain at VIH
or VHH (the same RP# level used for block erase).
WP# must also remain at VIL or VIH (the same
WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.
Word Write Suspend Command
R
Y
This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.
A
4.9.1 VPP = VIL FOR COMPLETE PROTECTION
R
E
L
IM
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to high-impedance. Specification
tWHRH1 defines the word write suspend latency.
P
At this point, a Read Array command can be written
to read data from location other than that which is
suspended. The only other valid commands while
word write is suspended are Read Status Register
and Word Write Resume. After Word Write Resume
command is written to the flash memory, the WSM
will continues the word write process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Word Write
Resume command is written, the device
Block Locking
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device.
IN
4.8
4.9
4.9.2 WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless VPP is below VPPLK).
4.9.3 BLOCK UNLOCKING
WP# = VIH or RP# =VHH unlocks all lockable
blocks.
These blocks can now be programmed or erased.
WP# or RP# controls all block locking and VPP
provides protection against spurious writes. Table 4
defines the write protection methods.
- 14 -
LH28F160BG-TL/BGH-TL
Table 4 Write Protection Alternatives
OPERATION VPP RP# WP#
EFFECT
VIL
X
VIL
Block Erase
or
Word Write
> VPPLK
VHH
VIH
X
X
All Blocks Locked.
All Blocks Locked.
X All Blocks Unlocked.
VIL 2 Boot Blocks Locked.
VIH All Blocks Unlocked.
Table 5 Status Register Definition
ESS
6
ES
5
WWS
4
VPPS
3
WWSS
2
R
0
R
NOTES :
DPS
1
Y
WSMS
7
Check RY/BY# or SR.7 to determine block erase or word
write completion. SR.6-0 are invalid while SR.7 = "0".
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
A
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
IN
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are "1"s after a block erase attempt, an
improper command sequence was entered.
SR.5 = ERASE STATUS (ES)
IM
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = WORD WRITE STATUS (WWS)
1 = Error in Word Write
0 = Successful Word Write
SR.3 = VPP STATUS (VPPS)
L
1 = VPP Low Detect, Operation Abort
0 = VPP OK
E
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase or Word Write command sequences. SR.3 is not
guaranteed to reports accurate feedback only when VPP ≠
VPPH1/2.
1 = Word Write Suspended
0 = Word Write in Progress/Completed
R
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
P
0 = Unlock
The WSM interrogates the WP# and RP# only after Block
Erase or Word Write command sequences. It informs the
system, depending on the attempted operation, if the WP# is
not VIH, RP# is not VHH.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.0 is reserved for future use and should be masked out
when polling the status register.
- 15 -
LH28F160BG-TL/BGH-TL
BUS
OPERATION COMMAND
Write D0H,
Block Address
Read
Status Register
Suspend Block
Erase Loop
No
0
Suspend
Block Erase
SR.7 =
Yes
1
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Write FFH after the last block erase operation to place device
in read array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
0
IM
VPP Range Error
Device Protect Error
E
SR.1 =
1
BUS
OPERATION COMMAND
L
1
0
1
R
SR.4, 5 =
Command Sequence
Error
P
0
SR.5 =
1
IN
A
Full Status
Check if Desired
SR.3 =
Y
Write 20H,
Block Address
COMMENTS
R
Start
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Block Erase
Error
0
Block Erase
Successful
Fig. 3 Automated Block Erase Flowchart
- 16 -
LH28F160BG-TL/BGH-TL
BUS
OPERATION COMMAND
Write Word
Data and Address
Read
Status Register
Suspend Word
Write Loop
No
0
Suspend
Word Write
SR.7 =
Yes
Write
Setup
Word Write
Data = 40H or 10H
Addr = Location to be Written
Write
Word Write
Data = Data to be Written
Addr = Location to be Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word writes.
SR full status check can be done after each word write or after
a sequence of word writes.
Write FFH after the last word write operation to place device
in read array mode.
1
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
0
IM
VPP Range Error
Device Protect Error
E
SR.1 =
1
BUS
OPERATION COMMAND
L
1
0
1
R
SR.4 =
IN
A
Full Status
Check if Desired
SR.3 =
Y
Write 40H or 10H,
Address
COMMENTS
R
Start
Word Write Error
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4
1 = Data Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
P
0
Word Write
Successful
Fig. 4 Automated Word Write Flowchart
- 17 -
LH28F160BG-TL/BGH-TL
BUS
OPERATION
Write
Write B0H
Read
Status Register
0
SR.7 =
1
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Erase
Resume
Block Erase
Completed
Read
or Word
Write?
Word Write
Word Write Loop
No
IN
Read Array Data
Data = D0H
Addr = X
A
1
Read
Data = B0H
Addr = X
R
0
Erase
Suspend
Read
Write
SR.6 =
COMMENTS
COMMAND
Y
Start
Done?
IM
Yes
Write D0H
Write FFH
Block Erase
Resumed
L
Read
Array Data
P
R
E
Fig. 5 Block Erase Suspend/Resume Flowchart
- 18 -
LH28F160BG-TL/BGH-TL
BUS
OPERATION
Write
Write B0H
0
SR.7 =
1
0
Word Write
Completed
1
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Word Write Suspended
0 = Word Write Completed
Read Array
Word Write
Resume
Data = D0H
Addr = X
A
Write
Data = FFH
Addr = X
Read array locations other
than that being written.
Read
IN
Write FFH
Read
Array Data
No
IM
Done
Reading
Data = B0H
Addr = X
Read
Write
SR.2 =
Word Write
Suspend
Yes
Write FFH
Read
Array Data
E
Word Write Resumed
L
Write D0H
P
R
Fig. 6 Word Write Suspend/Resume Flowchart
- 19 -
Y
Read
Status Register
COMMENTS
COMMAND
R
Start
LH28F160BG-TL/BGH-TL
5 DESIGN CONSIDERATIONS
5.1
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Threeline control provides for :
5.2
RY/BY#, Block Erase and Word
Write Polling
R
E
L
RY/BY# is a output that provides a hardware
method of detecting block erase and word write
completion. It transitions low after block erase or
word write commands and returns to highimpedance when the WSM has finished executing
the internal algorithm.
P
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also high-impedance when the
device is in block erase suspend (with word write
inactive), word write suspend or deep power-down
modes.
5.3
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
R
A
5.4
VPP Trace on Printed Circuit Boards
IN
IM
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
Y
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for word writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5
VCC, VPP, RP# Transitions
Block erase and word write are not guaranteed if
VPP falls outside of a valid VPPH1/2 range, VCC falls
outside of a valid VCC1 range, or RP# ≠ VIH or VHH.
If VPP error is detected, status register bit SR.3 is
set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to VIL
during block erase or word write, RY/BY# will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation
may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP#
- 20 -
LH28F160BG-TL/BGH-TL
transitions to VIL clear the status register.
5.7
The CUI latches commands issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO.
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
R
The device is designed to offer protection against
accidental block erasure or word writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (VPP or VCC)
powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
L
IM
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
A
Power-Up/Down Protection
IN
5.6
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solidstate storage can consume negligible power by
lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read
following the tPHQV and tPHWL wake-up cycles
required after RP# is first raised to VIH. See Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS
- READ-ONLY and WRITE OPERATIONS" and
Fig. 9, Fig. 10 and Fig. 11 for more information.
Y
After block erase or word write, even after VPP
transitions down to VPPLK, the CUI must be placed
in read array mode via the Read Array command if
subsequent access to the memory array is desired.
Power Consumption
P
R
E
WP# provides additional protection from inadvertent
code or data alteration. The device is disabled
while RP# = VIL regardless of its control inputs
state.
- 21 -
LH28F160BG-TL/BGH-TL
6 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings∗
Operating Temperature
• LH28F160BG-TL
During Read, Block Erase and
Word Write ............................ 0 to +70°C (NOTE 1)
Temperature under Bias............. –10 to +80°C
NOTES :
1.
Storage Temperature ........................ –65 to +125°C
2.
Voltage On Any Pin
(except VCC, VPP, and RP#) .. –0.5 V to VCC+0.5 V (NOTE 3)
IM
VPP Update Voltage during
Block Erase and
Word Write .................. –0.2 to +14.0 V (NOTE 3, 4)
Operating temperature is for commercial product defined
by this specification.
Operating temperature is for extended temperature
product defined by this specification.
All specified voltages are with respect to GND. Minimum
DC voltage is –0.5 V on input/output pins and – 0.2 V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and VCC is VCC+0.5 V
which, during transitions, may overshoot to VCC+2.0 V
for periods < 20 ns.
Maximum DC voltage on VPP and RP# may overshoot
to +14.0 V for periods < 20 ns.
Output shorted for no more than one second. No more
than one output shorted at a time.
IN
VCC Supply Voltage ................. –0.2 to +3.9 V (NOTE 3)
3.
R
• LH28F160BGH-TL
During Read, Block Erase and
Word Write ........................ –25 to +85°C (NOTE 2)
Temperature under Bias............. –25 to +85°C
Y
∗WARNING : Stressing the device beyond the
"Absolute
Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
A
6.1
NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.
5.
L
RP# Voltage ........................ –0.5 to +14.0 V (NOTE 3, 4)
4.
Output Short Circuit Current............... 100 mA (NOTE 5)
Operating Conditions
E
6.2
SYMBOL
PARAMETER
Operating Temperature
VCC1
VCC Supply Voltage
R
TA
NOTE
1
MIN.
0
MAX.
+70
–25
+85
3.6
2.7
UNIT
˚C
˚C
VERSIONS
LH28F160BG-TL
LH28F160BGH-TL
V
1.
P
NOTE :
Test condition : Ambient temperature
6.2.1 CAPACITANCE (NOTE 1)
TA = +25˚C, f = 1 MHz
TYP.
MAX.
UNIT
CIN
SYMBOL
Input Capacitance
PARAMETER
7
10
pF
VIN = 0.0 V
COUT
Output Capacitance
9
12
pF
VOUT = 0.0 V
NOTE :
1.
Sampled, not 100% tested.
- 22 -
CONDITION
LH28F160BG-TL/BGH-TL
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
1.35
INPUT
1.35 OUTPUT
TEST POINTS
0.0
AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing
ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Y
Fig. 7 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.6 V
Test Configuration Capacitance Loading Value
TEST CONFIGURATION
VCC = 2.7 to 3.6 V
R
1.3 V
A
1N914
DEVICE
UNDER
TEST
OUT
CL
IM
CL Includes Jig
Capacitance
IN
RL = 3.3 kΩ
P
R
E
L
Fig. 8 Transient Equivalent Testing
Load Circuit
- 23 -
CL (pF)
50
LH28F160BG-TL/BGH-TL
6.2.3 DC CHARACTERISTICS
PARAMETER
NOTE
VCC = 2.7 to 3.6 V
TYP.
MAX.
ILI
Input Load Current
1
±1
µA
ILO
Output Leakage Current
1
±10
µA
25
ICCS
VCC Standby Current
50
TEST
CONDITIONS
UNIT
µA
VCC = VCC Max.
VIN = VCC or GND
VCC = VCC Max.
VOUT = VCC or GND
CMOS Inputs
VCC = VCC Max.
CE# = RP# = VCC±0.2 V
TTL Inputs
1, 3, 6
0.2
2
mA
Y
SYMBOL
VCC = VCC Max.
VCC Deep Power-Down Current
1
5
10
µA
RP# = GND±0.2 V
IOUT (RY/BY#) = 0 mA
CMOS Inputs
A
ICCD
R
CE# = RP# = VIH
VCC = VCC Max.
VCC Read Current
1, 5, 6
VCC Word Write Current
ICCE
VCC Block Erase Current
1, 7
ICCWS VCC Word Write or Block Erase
ICCES Suspend Current
1, 2
IPPR
E
VPP Deep Power-Down Current
1
P
IPPD
1
IPPW
IPPE
VPP Word Write Current
1, 7
VPP Block Erase Current
1, 7
IPPWS VPP Word Write or Block Erase
IPPES Suspend Current
1
IOUT = 0 mA
TTL Inputs
VCC = VCC Max.
mA
17
mA
12
mA
17
mA
VPP = 12.0±0.6 V
VPP = 2.7 to 3.6 V
12
mA
VPP = 12.0±0.6 V
6
mA
CE# = VIH
±15
200
µA
µA
VPP ≤ VCC
VPP > VCC
0.1
5
µA
RP# = GND±0.2 V, VPP ≤ VCC
14
150
µA
12
40
mA
RP# = GND±0.2 V, VPP > VCC
VPP = 2.7 to 3.6 V
30
mA
11
35
mA
VPP = 12.0±0.6 V
VPP = 2.7 to 3.6 V
20
mA
VPP = 12.0±0.6 V
200
µA
VPP = VPPH1/2
1, 7
VPP Standby or Read Current
R
IPPS
L
ICCW
CE# = GND
f = 5 MHz
30
IM
ICCR
mA
IN
25
±2
10
10
- 24 -
CE# = GND
f = 5 MHz
IOUT = 0 mA
VPP = 2.7 to 3.6 V
LH28F160BG-TL/BGH-TL
6.2.3 DC CHARACTERISTICS (contd.)
VIL
Input Low Voltage
7
VCC = 2.7 to 3.6 V
MIN.
MAX.
– 0.5
0.8
VIH
Input High Voltage
7
0.7VCC
VOL
Output Low Voltage
3, 7
VOH1
Output High Voltage (TTL)
3, 7
0.85VCC
V
VCC = VCC Min.
IOH = –2.0 mA
VOH2
Output High Voltage (CMOS)
3, 7
0.5
V
VCC = VCC Min.
IOH = –100 µA
VPPH2
Normal Operations
VPP Voltage during Word Write or
4, 7
Block Erase Operations
VPP Voltage during Word Write or
Block Erase Operations
VLKO
VCC Lockout Voltage
VHH
RP# Unlock Voltage
V
11.4
12.6
IM
VCC = VCC Min.
IOL = 2.0 mA
V
V
5.
6.
7.
8.
L
E
3.
4.
3.6
9.
R
2.
All currents are in RMS unless otherwise noted. Typical
values at VCC = 3.0 V, VPP = 3.0 V and TA = +25˚C.
These currents are valid for all product versions
(packages and speeds).
ICCWS and ICCES are specified with the device deselected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
Includes RY/BY#.
Block erases and word writes are inhibited when VPP ≤
VPPLK, and not guaranteed in the range between VPPLK
(max.) and VPPH1 (min.), between VPPH1 (max.) and
VPPH2 (min.), and above VPPH2 (max.).
V
2.7
P
1.
0.4
V
11.4
NOTES :
V
1.5
1.3
8, 9
V
VCC+0.3
Y
VPP Lockout Voltage during
TEST
CONDITIONS
UNIT
R
VPPH1
NOTE
A
VPPLK
PARAMETER
IN
SYMBOL
- 25 -
12.6
V
Block Erase and Word Write
for Boot Blocks
Automatic Power Saving (APS) reduces typical ICCR to
3 mA at 2.7 V VCC in static operation.
CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
Sampled, not 100% tested.
Boot block erases and word writes are inhibited when
the corresponding RP# = VIH or WP# = VIL. Block erase
and word write operations are not guaranteed with VIH <
RP# < VHH and should not be attempted.
RP# connection to a VHH supply is allowed for a
maximum cumulative period of 80 hours.
LH28F160BG-TL/BGH-TL
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –25 to +85˚C
LH28F160BG-TL10 LH28F160BG-TL12
LH28F160BGH-TL10 LH28F160BGH-TL12 UNIT
VERSIONS
PARAMETER
NOTE
tAVAV
tAVQV
Read Cycle Time
Address to Output Delay
tELQV
tPHQV
CE# to Output Delay
RP# High to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address, CE# or
OE# Change, Whichever Occurs First
3
MAX.
100
MIN.
100
10
45
0
R
50
0
20
0
IN
IM
L
E
R
P
50
0
45
0
120
10
See AC Input/Output Reference Waveform (Fig. 7) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
Sampled, not 100% tested.
- 26 -
120
Y
2
MAX.
120
100
NOTES :
1.
2.
3.
MIN.
A
SYMBOL
0
ns
ns
ns
µs
ns
ns
ns
ns
25
ns
ns
LH28F160BG-TL/BGH-TL
Standby
VIH
Device
Address Selection
ADDRESSES (A)
Data Valid
Address Stable
VIL
tAVAV
VIH
CE# (E)
tEHQZ
VIL
VIH
Y
OE# (G)
tGHQZ
VIL
tGLQV
tELQV
VIL
A
tGLQX
tELQX
High Z
Valid Output
VOL
tAVQV
VCC
tPHQV
IM
VIH
IN
VOH
DATA (D/Q)
(DQ0-DQ15)
R
VIH
WE# (W)
RP# (P)
VIL
P
R
E
L
Fig. 9 AC Waveform for Read Operations
- 27 -
tOH
High Z
LH28F160BG-TL/BGH-TL
6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –25 to +85˚C
LH28F160BG-TL10 LH28F160BG-TL12
LH28F160BGH-TL10 LH28F160BGH-TL12 UNIT
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
NOTE
MIN.
100
2
10
0
tPHHWH RP# VHH Setup to WE# Going High
tSHWH WP# VIH Setup to WE# Going High
2
2
100
100
tVPWH
tAVWH
VPP Setup to WE# Going High
Address Setup to WE# Going High
2
3
100
50
tDVWH
tWHDX
Data Setup to WE# Going High
Data Hold from WE# High
3
50
0
tWHAX
Address Hold from WE# High
0
0
ns
tWHEH
tWHWL
CE# Hold from WE# High
WE# Pulse Width High
0
30
0
30
ns
ns
tWHRL
tWHGL
WE# High to RY/BY# Going Low
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD, RY/BY# High
tQVPH
tQVSL
RP# VHH Hold from Valid SRD, RY/BY# High
tPHWL
tELWL
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
tWLWH
WE# Pulse Width
ns
10
0
µs
ns
50
ns
100
100
ns
ns
100
50
ns
ns
50
0
ns
ns
R
A
IN
MAX.
0
ns
ns
2, 4
0
0
ns
2, 4
0
0
ns
WP# VIH Hold from Valid SRD, RY/BY# High
2, 4
0
0
ns
Read timing characteristics during block erase and word
write operations are the same as during read-only
operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 2 for valid AIN and DIN for block erase or
word write.
4.
IM
0
L
E
R
P
2.
3.
MIN.
120
Y
50
NOTES :
1.
MAX.
- 28 -
100
100
VPP should be held at VPPH1/2 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F160BG-TL/BGH-TL
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
AIN
ADDRESSES (A)
VIL
tAVAV
tAVWH tWHAX
VIH
CE# (E)
VIL
tWHEH
tELWL
tWHGL
VIH
OE# (G)
VIL
tWHQV1/2/3/4
Y
tWHWL
VIH
WE# (W)
High Z
VIL
DIN
tWHRL
High Z
RY/BY# (R)
VOL
tQVSL
tPHHWH
tQVPH
IN
tSHWH
VIH
WP# (S)
RP# (P)
VIH
VIL
IM
VIL
VHH
tVPWH
tQVVL
L
VPPH1/2
Valid
SRD
DIN
tPHWL
A
VIH
DATA (D/Q)
R
tWLWH
tDVWH
tWHDX
VIL
VPP (V)
VPPLK
NOTES :
R
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
P
1.
2.
3.
4.
5.
6.
E
VIL
Fig. 10 AC Waveform for WE#-Controlled Write Operations
- 29 -
DIN
LH28F160BG-TL/BGH-TL
6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –25 to +85˚C
LH28F160BG-TL10 LH28F160BG-TL12
LH28F160BGH-TL10 LH28F160BGH-TL12 UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
100
120
ns
VERSIONS
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tELEH
tPHHEH
tSHEH
CE# Pulse Width
RP# VHH Setup to CE# Going High
WP# VIH Setup to CE# Going High
tVPEH
tAVEH
10
10
µs
0
0
ns
2
2
70
100
100
70
100
100
ns
ns
ns
VPP Setup to CE# Going High
Address Setup to CE# Going High
2
3
100
50
100
50
ns
ns
tDVEH
Data Setup to CE# Going High
3
50
50
ns
tEHDX
Data Hold from CE# High
0
0
ns
tEHAX
Address Hold from CE# High
0
0
ns
tEHWH
tEHEL
WE# Hold from CE# High
CE# Pulse Width High
0
25
0
25
ns
ns
tEHRL
CE# High to RY/BY# Going Low
tEHGL
tQVVL
Write Recovery before Read
VPP Hold from Valid SRD, RY/BY# High
tQVPH
tQVSL
RP# VHH Hold from Valid SRD, RY/BY# High
WP# VIH Hold from Valid SRD, RY/BY# High
IN
100
ns
2, 4
0
0
ns
ns
2, 4
2, 4
0
0
0
0
ns
ns
R
E
L
4.
P
2.
3.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
Refer to Table 2 for valid AIN and DIN for block erase or
word write.
100
0
0
IM
NOTES :
1.
2
Y
WE# Setup to CE# Going Low
R
RP# High Recovery to CE# Going Low
tWLEL
A
tPHEL
- 30 -
VPP should be held at VPPH1/2 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
LH28F160BG-TL/BGH-TL
(NOTE 1) (NOTE 2)
(NOTE 3)
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
AIN
ADDRESSES (A)
VIL
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (W)
VIL
tEHWH
tWLEL
tEHGL
VIH
OE# (G)
VIL
tEHQV1/2/3/4
Y
tEHEL
VIH
CE# (E)
VIH
High Z
DATA (D/Q)
DIN
Valid
SRD
DIN
tEHRL
High Z
RY/BY# (R)
VOL
A
tPHEL
VIL
tQVSL
tPHHEH
tQVPH
IN
tSHEH
VIH
WP# (S)
VHH
VIH
VIL
IM
VIL
RP# (P)
R
tELEH
tDVEH
tEHDX
VIL
tVPEH
tQVVL
L
VPPH1/2
VPP (V)
VPPLK
NOTES :
R
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
P
1.
2.
3.
4.
5.
6.
E
VIL
Fig. 11 AC Waveform for CE#-Controlled Write Operations
- 31 -
DIN
LH28F160BG-TL/BGH-TL
6.2.7 RESET OPERATIONS
High Z
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
Y
(A) Reset During Read Array Mode
High Z
RY/BY# (R)
VOL
R
tPLRH
VIH
RP# (P)
VIL
A
tPLPH
(B) Reset During Block Erase or Word Write
IN
2.7 V
VCC
tVPH
VIL
VIH
RP# (P)
IM
VIL
(C) RP# Rising Timing
L
Fig. 12 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
PARAMETER
NOTE
E
SYMBOL
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable)
tPLRH
tVPH
RP# Low to Reset during Block Erase or Word Write
VCC 2.7 V to RP# High
1.
2.
P
NOTES :
R
tPLPH
These specifications are valid for all product versions
(packages and speeds).
If RP# is asserted while a block erase or word write
operation is not executing, the reset will complete within
100 ns.
3.
4.
- 32 -
VCC = 2.7 to 3.6 V
MIN.
MAX.
100
2, 3
4
ns
22
100
UNIT
µs
ns
A reset time, tPHQV, is required from the latter of RY/BY#
or RP# going high until outputs are valid.
When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
LH28F160BG-TL/BGH-TL
6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (NOTE 3, 4)
• VCC = 2.7 to 3.6 V, TA = 0 to +70°C or –25 to +85˚C
PARAMETER
Block Write Time
tEHQV2
tWHRH1
tEHRH1
tWHRH2
tEHRH2
Block Erase Time
2
55
15
µs
60
1.8
30
0.6
µs
s
32 k-Word Block
2
2
0.3
1.2
0.2
0.7
s
s
4 k-Word Block
2
0.5
32 k-Word Block
4 k-Word Block
Word Write Suspend Latency Time to Read
7.5
Erase Suspend Latency Time to Read
19.3
3.
L
E
R
- 33 -
0.5
8.6
23.6
s
6.5
7.5
µs
11.8
15
µs
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
IN
4.
IM
Typical values measured at TA = +25˚C and VCC = 3.0 V,
VPP = 3.0 V/VCC = 3.0 V, VPP = 12.0 V. Subject to
change based on device characterization.
Excludes system-level overhead.
P
2.
UNIT
2
2
NOTES :
1.
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
A
tWHQV2
32 k-Word Block
4 k-Word Block
VPP = 2.7 to 3.6 V
MIN. TYP.(NOTE 1) MAX.
Y
tWHQV1
Word Write Time
tEHQV1
NOTE
R
SYMBOL
LH28F160BG-TL/BGH-TL
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products
L H 2 8 F 1 6 0 B G (H) E - T T L 1 0
Device Density
160 = 16 M-bit
Access Speed (ns)
10 : 100 ns (2.7 to 3.6 V)
12 : 120 ns (2.7 to 3.6 V)
Architecture
B = Boot Block
Y
Limited Voltage Option
TL = 2.7 to 3.6 V VCC Only
Power Supply Type
G = Smart 3 Technology
R
Block Locate Option
T = Top Boot
B = Bottom Boot
Operating Temperature
Blank = 0 to +70°C
H = –25 to +85°C
ORDER CODE
VALID OPERATIONAL COMBINATIONS
VCC = 2.7 to 3.6 V
IM
OPTION
IN
A
Package
E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend
R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend
B = 60-ball CSP (FBGA060/048-P-0811)
50 pF load,
LH28F160BGXX-XTL10
2
LH28F160BGXX-XTL12
120 ns
P
R
E
L
1
1.35 V I/O Levels
100 ns
- 34 -
PACKAGING
48
24
0.1
12.0 ±0.2
0.10
0.5 TYP.
M
1
48 _ 0.2±0.08
48 TSOP (TSOP048-P-1220)
25
1.2MAX.
1.0 ±0.1
0.125
18.4 ±0.2
Package base plane
19.0 ±0.1
0.1±0.1
0.125 ±0.05
20.0±0.3
PACKAGING
60 CSP (FBGA060/048-P-0811)
A
1.2MAX.
8.00
+ 0.2
B
∗0.4TYP.
/ / 0.1 S
S
∗Land hole diameter
0.35±0.05
for ball mounting
+ 0.2
11.00
0.1 S
C
0.4TYP.
0.8TYP.
1.2TYP.
1.1TYP.
0.8TYP.
0.4TYP.
H
D
A
12
1
0.45±0.03
0.30
M
S
AB
0.15
M
S
CD
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