IDT ICS841608AKIT Femtoclocksâ ¢ crystal-to-hcsl clock generator Datasheet

ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS841608I is an optimized PCIe and sRIO
ICS
clock generator and member of the HiPerClocks™
HiPerClockS™ family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel cr ystal to
generate 100MHz and 125MHz clock signals,
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device has excellent phase jitter (<1ps rms)
suitable for clock components requiring precise and low-jitter
PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the ICS841608I can also
drive the high-speed sRIO and PCIe SerDes clock inputs of
communication processors, DSPs, switches and bridges.
• Eight HCSL outputs: configurable for PCIe (100MHz)
and sRIO (125MHz) clock signals
• Selectable crystal oscillator interface, 25MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended reference clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter @125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.37ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and (RoHs 5) lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
FSEL
IREF
BYPASS
VCO = 500MHz
VDDA
1
÷N
REF_SEL
REF_IN Pulldown
nQ0
0
VDD
FemtoClock
PLL
XTAL_OUT
Q0
1
0
GND
OSC
REF_IN
XTAL_IN
32 31 30 29 28 27 26 25
Q1
÷4
÷5 (default)
nQ1
REF_SEL Pulldown
Q2
M = ÷20
nQ2
IREF
Q3
BYPASS Pulldown
nQ3
XTAL_IN
1
24
VDD
XTAL_OUT
2
23
nQ7
MR/nOE
3
22
Q7
VDD
4
21
nQ6
Q0
5
20
Q6
nQ0
6
19
GND
Q1
7
18
nQ5
nQ1
8
17
Q5
FSEL Pulldown
Q4
nQ4
Q4
VDD
nQ3
nQ6
Q3
Q6
nQ2
nQ5
Q2
Q5
GND
nQ4
9 10 11 12 13 14 15 16
ICS841608I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
Q7
nQ7
MR/nOE Pulldown
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
XTAL_IN,
XTAL_OUT
1, 2
3
Type
Description
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z).
Pulldown
When logic LOW, the internal dividers and the outputs are enabled.
Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C.
Input
MR/nOE
Input
4, 14,
24, 31
5, 6
VDD
Power
Core supply pins.
Q0, nQ0
Output
Differential output pair. HCSL interface levels.
7, 8
Q1, nQ1
Output
Differential output pair. HCSL interface levels.
9, 19, 32
GND
Power
Power supply ground.
10, 11
Q2, nQ2
Output
Differential output pair. HCSL interface levels.
12, 13
Q3, nQ3
Output
Differential output pair. HCSL interface levels.
15, 16
Q4, nQ4
Output
Differential output pair. HCSL interface levels.
17, 18
Q5, nQ5
Output
Differential output pair. HCSL interface levels.
20, 21
Q6, nQ6
Output
Differential output pair. HCSL interface levels.
22, 23
Q7, nQ7
Output
Differential output pair. HCSL interface levels.
25
FSEL
Input
26
IREF
Output
27
BYPASS
Input
28
VDDA
Power
29
REF_SEL
Input
30
REF_IN
Input
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
(475Ω) from this pin to ground provides a reference current used for
differential current-mode Qx/nQx clock outputs.
Selects PLL operation/PLL bypass operation. Asynchronous function.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3B.
Analog supply pin.
Reference select. Selects the input reference source. See Table 3D.
Pulldown
LVCMOS/LVTTL interface levels.
Pulldown LVCMOS/LVTTL PLL reference clock input.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3A. FSEL FUNCTION TABLE (fREF = 25MHZ)
Input
TABLE 3B. BYPASS FUNCTION TABLE
Outputs
Input
FSEL
N
Q0:7/nQ0:7
BYPASS
0
5
VCO/5 (100MHz) PCIe (default)
0
PLL enabled (default)
1
4
VCO/4 (125MHz) sRIO
1
PLL bypassed (fOUT = fREF ÷ N)
TABLE 3C. MR/nOE FUNCTION TABLE
PLL Configuration
TABLE 3D. REF_SEL FUNCTION TABLE
Input
Input
REF_SEL
Input Reference
0
Outputs enabled (default)
0
XTAL (default)
1
Device reset, outputs disabled (high-impedance)
1
REF_IN
MR/nOE
Function
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 37°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.15
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
87
mA
IDDA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum Typical
2
-0.3
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Maximum
VDD + 0.3
Units
V
0.8
V
150
µA
-5
µA
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
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TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random); NOTE 1
Tj
Phase Jitter Peak-to-Peak; NOTE 2
TREFCLK_HF_RMS
Phase Jitter RMS; NOTE 3
Test Conditions
Minimum
VCO/5
Typical
Maximum
Units
100
MHz
VCO/4
125
MHz
100MHz, (1.875MHz - 20MHz)
0.39
ps
125MHz, (1.875MHz - 20MHz)
100MHz, (1.2MHz – 50MHz),
106 samples, 25MHz crystal input
125MHz, (1.2MHz – 62.5MHz),
106 samples, 25MHz crystal input
100MHz, 106 samples,
25MHz crystal input
125MHz, 106 samples,
25MHz crystal input
0.37
ps
24.36
ps
23.76
ps
ps
rms
ps
rms
2.44
2.37
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
50
ps
tsk(o)
Rise Edge
Rate
Fall Edge Rate
Output Skew; NOTE 4, 5
105
ps
Rising Edge Rate; NOTE 6, 7
0.6
4
V/ns
Falling Edge Rate; NOTE 6, 7
0.6
4
V/ns
VRB
Ringback Voltage; NOTE 6, 8
-100
VMAX
Absolute Max. Output Voltage; NOTE 9, 10
VMIN
-300
odc
Absolute Min. Output Voltage; NOTE 9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of VCross over all edges;
NOTE 9, 12, 14
Output Duty Cycle; NOTE 6, 15
TSTABLE
Power-up Stable Clock Output; NOTE 6, 8
500
tL
PLL Lock Time
VCROSS
ΔVCROSS
250
48
100
mV
1150
mV
mV
550
mV
140
mV
52
%
ps
90
ms
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS
for any par ticular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
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TYPICAL PHASE NOISE AT 100MHZ
100MHz
➤
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
NOISE POWER dBc
Hz
Filter
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
125MHz
➤
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
NOISE POWER dBc
Hz
Filter
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
Filter to raw data
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
3.3V±5%
3.3V±5%
3.3V±5%,
3.3V±5%,
VDD
100Ω
33Ω
SCOPE
Measurement
Point
VDD
50Ω
VDDA
VDDA
49.9Ω
2pF
HCSL
100Ω
33Ω
IREF
HCSL
Measurement
Point
50Ω
IREF
GND
GND
49.9Ω
475Ω
2pF
475Ω
0V
0V
This load condition is used for IDD, tsk(o), and t jit measurements.
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQx
Qx
nQy
Phase Noise Mask
Qy
tsk(o)
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
RMS PHASE JITTER
TSTABLE
Rise Edge Rate
Fall Edge Rate
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
+150mV
0.0V
-150mV
Q - nQ
VRB
Q - nQ
TSTABLE
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
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PARAMETER MEASUREMENT INFORMATION, CONTINUED
VMAX = 1.15V
nQ
nQ
VCROSS_MAX = 550mV
VCROSS_DELTA = 140mV
VCROSS_MIN = 250mV
Q
Q
VMIN = -0.30V
SINGLE-ENDED MEASUREMENT POINTS FOR
ABSOLUTE CROSS POINT/SWING
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT
20
0
-3dB
1.2MHz
Clock Period (Differential)
Negative Duty
Cycle (Differential)
-3dB
21.9MHz
-20
Mag (dB)
Positive Duty
Cycle (Differential)
0.0V
Q - nQ
-40
-60
-80
-100
104
105
106
107
108
Frequency (Hz)
H3(s) * (H1(s) – H2(s))
DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD
IDT ™ / ICS™ HCSL CLOCK GENERATOR
COMPOSITE PCIe TRANSFER FUNCTION
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS841608I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V DD and V DDA should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
pin. Figure 1 illustrates this for a generic VDD pin and also shows
that VDDA requires that an additional10Ω resistor along with a
10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
VFQFN EPAD THERMAL RELEASE PATH
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
In order to maximize both the removal of heat from the package
and the electrical performance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 2. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
SOLDER
LAND PATTERN
THERMAL VIA
PIN
PIN PAD
(GROUND PAD)
FIGURE 2. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
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LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one of
two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω.
VDD
VCC
VDD
VCC
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
CRYSTAL INPUT INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
The ICS841608I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 4 below
XTAL_OUT
C1
27p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
FIGURE 4. CRYSTAL INPUt INTERFACE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
OUTPUTS:
HCSL OUTPUTs
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
SCHEMATIC EXAMPLE
adjusted for optimizing frequency accuracy. Two examples of
HCSL terminations are shown in this schematic. The decoupling
capacitors should be located as close as possible to the power
pin.
Figure 5 shows an example of ICS841608I application
schematic. In this example, the device is operated at VDD = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
VDD
R1
VDDA
10
R2
475
C3
0.1u
C4
10u
33
FSEL
Zo = 50
-
TL1
R4
33
32
31
30
29
28
27
26
25
Zo = 50
X1
25MHz
18pF
U1
C2
27pF
VDD
1
2
3
4
5
6
7
8
MR/nOE
+
TL2
GND
VDD
REF_IN
REF_SEL
VDDA
BYPASS
IREF
FSEL
C1
27pF
R3
BYPASS
VDD
REF_SEL
VDD
R5
50
R6
50
Recommended for
PCI Express Add-In
Card
VDD
VDD
nQ7
Q7
nQ6
Q6
GND
nQ5
Q5
XTAL_IN
XTAL_OUT
MR/nOE
VDD
Q0
nQ0
Q1
nQ1
24
23
22
21
20
19
18
17
VDD=3.3V
9
10
11
12
13
14
15
16
GND
Q2
nQ2
Q3
nQ3
VDD
Q4
nQ4
HCSL Termination
ICS841608I
Logic Control Input Examples
RU1
1K
Set Logic
Input to
'0'
VDD
VDD
Set Logic
Input to
'1'
VDD
VDD
Zo = 50
RU2
Not Install
-
TL3
Zo = 50
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
+
TL4
R7
50
RD2
1K
VDD
(U1:6)
C6
.1uf
VDD
(U1:14)
C7
.1uf
Recommended for PCI
Express Point-to-Point
Connection
(U1:24) VDD (U1:31)
C8
.1uf
R8
50
C5
0.1u
FIGURE 5. ICS841608I SCHEMATIC EXAMPLE
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RECOMMENDED TERMINATION
Figure 6A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
0.7V Differential HCSL
Add-In Card
0.7V Differential HCSL
Clock Driver
FIGURE 6A. RECOMMENDED TERMINATION
Figure 6B is the recommended termination for applications
which require a point to point connection and contain the driver
and receiver on the same PCB. All traces should all be 50Ω
impedance.
0.7V Differential HCSL
Clock Driver
FIGURE 6B. RECOMMENDED TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841608I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841608I is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (87mA + 15mA) = 353.43mW
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 44.5mW = 356mW
Total Power_MAX (3.465V, with all outputs switching) = 353.43mW + 356mW =709.43mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.709W * 37°C/W = 111.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ HCSL CLOCK GENERATOR
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
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3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
➤
VOUT
RREF =
475Ω ± 1%
RL
50Ω
IC
FIGURE 7. HCSL DRIVER CIRCUIT
AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD is HIGH.
Power
= (VDD_HIGH – VOUT ) * IOUT, since VOUT = IOUT * RL
= (VDD_HIGH – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
IDT ™ / ICS™ HCSL CLOCK GENERATOR
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RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS841608I is: 2785
IDT ™ / ICS™ HCSL CLOCK GENERATOR
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
0.80
--
1.00
A1
0
--
0.05
0.25 Ref.
A3
b
0.18
0.25
0.30
ND
8
NE
8
5.00 BASIC
D
D2
1.25
2.25
E2
1.25
2.25
3.25
0.50 BASIC
e
L
3.25
5.00 BASIC
E
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ HCSL CLOCK GENERATOR
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TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841608AKI
ICS841608AI
32 Lead VFQFN
tray
-40°C to 85°C
841608AKIT
ICS841608AI
32 Lead VFQFN
2500 tape & reel
-40°C to 85°C
841608AKILF
ICS41608AIL
32 Lead "Lead-Free" VFQFN
tray
-40°C to 85°C
841608AKILFT
ICS41608AIL
32 Lead "Lead-Free" VFQFN
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ HCSL CLOCK GENERATOR
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www.IDT.com
For Sales
For Tech Support
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+408-284-8200 (outside USA)
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[email protected]
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Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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