SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. • • • • • UNIVERSAL 4-BIT SHIFT REGISTER Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) 16 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 PIN NAMES PE P0 – P3 J K CP MR Q0 – Q3 Q3 1 LOADING (Note a) Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b) Complementary Last Stage Output (Note b) HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL FAST AND LS TTL DATA 5-366 SN54/74LS195A LOGIC DIAGRAM FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS195A has two primary modes of operation, shift right (Q0 º Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 º Q1 º Q2 º Q3 following each LOW to HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q 3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 º Q2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation — except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. MODE SELECT — TRUTH TABLE OPERATING MODES INPUTS OUTPUTS MR PE J K Q1 Q2 Q3 Q3 L X X X Pn X Q0 Asynchronous Reset L L L L H Shift, Set First Stage Shift, Reset First Shift, Toggle First Stage Shift, Retain First Stage H H H H h h h h h I h I h I I h X X X X H L q0 q0 q0 q0 q0 q0 q1 q1 q1 q1 q2 q2 q2 q2 q2 q2 q2 q2 Parallel Load H I X X pn p0 p1 p2 p3 p3 L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. FAST AND LS TTL DATA 5-367 SN54/74LS195A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA – 20 VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 21 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 30 39 Max Unit fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Clock to Output 14 17 22 26 ns tPHL Propagation Delay, MR to Output 19 30 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW CP Clock Pulse Width 16 ns tW MR Pulse Width 12 ns ts PE Setup Time 25 ns ts Data Setup Time 15 ns trec Recovery Time 25 ns trel PE Release Time th Data Hold Time 10 0 ns ns FAST AND LS TTL DATA 5-368 Test Conditions VCC = 5.0 V SN54/74LS195A DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. -$ # "!"! # - - # # ! -, -( "!"! Figure 1. Clock to Output Delays and Clock Pulse Width -, -( # -, -( -, -( .# # ! !" ! ! % -$ # Figure 3. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0, P1, P2, P3) # -+'& # ! - "!"! # # -, ! Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time ! ! ! "!"! # -, -+') -+') # # * * * * ! !! $ ! % "! Figure 4. Setup (ts) and Hold (th) Time for PE Input FAST AND LS TTL DATA 5-369 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-370 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! " " -B1 & 9 * * ! ! ! ! * * ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-371