SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset. • • • • • 8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES E D0 – D3 CP Q0 – Q3 Q0 – Q3 LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 732-03 20 1 LOADING (Note a) Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs (Note b) Complemented Outputs (Note b) OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. N SUFFIX PLASTIC CASE 738-03 20 1 DW SUFFIX SOIC CASE 751D-03 20 1 NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXDW SN74LSXXXD FAST AND LS TTL DATA 5-533 Ceramic Plastic SOIC SOIC SN54/74LS377 • SN54/74LS378 • SN54/74LS379 CONNECTION DIAGRAM DIPS (TOP VIEW) SN54 / 74LS377 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 20 19 18 17 16 15 14 13 12 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 9 10 E Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND SN54 / 74LS378 VCC Q5 D5 D4 Q4 D3 Q3 CP 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 E Q0 D0 D1 Q1 D2 Q2 GND VCC Q3 Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 SN54 / 74LS379 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 E Q0 Q0 D0 D1 Q1 Q1 GND FAST AND LS TTL DATA 5-534 SN54/74LS377 • SN54/74LS378 • SN54/74LS379 LOGIC DIAGRAMS SN54 / 74LS377 SN54 / 74LS378 SN54 / 74LS379 FAST AND LS TTL DATA 5-535 SN54/74LS377 • SN54/74LS378 • SN54/74LS379 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH IOL Output Current — High 54, 74 – 0.4 mA Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL IOS Input LOW Current ICC Power Supply Current Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V Short Circuit Current (Note 1) – 20 LS377 LS378 LS379 20 µA 0.1 mA – 0.4 mA – 100 mA VCC = MAX, VIN = 0.4 V VCC = MAX 28 22 15 mA VCC = MAX, NOTE 1 NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Min Typ 30 40 Propagation Delay, Clock to Output Max Unit Test Conditions MHz 17 18 27 27 VCC = 5.0 V CL = 15 pF ns AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW ts Parameter Min Typ Max Unit Any Pulse Width 20 ns Data Setup Time 20 ns Inactive — State 10 ns Active — State 25 ns 5.0 ns ts Enable Setup Time th Any Hold Time DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following Test Conditions VCC = 5.0 V the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. FAST AND LS TTL DATA 5-536 SN54/74LS377 • SN54/74LS378 • SN54/74LS379 TRUTH TABLE E CP Dn Qn Qn H X No Change No Change L H H L L L L H L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial AC WAVEFORMS SN54 / 74LS377 SN54 / 74LS378 SN54 / 74LS379 Figure 2. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock Figure 1. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data or Enable to Clock *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 3. Clock to Output Delays Clock Pulse Width, Frequency, Setup and Hold Times Data, Enable to Clock FAST AND LS TTL DATA 5-537 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-538 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! " " -B1 & 9 * * ! ! ! ! * * ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-539