MOTOROLA SN74LS398N

SN54/74LS398
SN54/74LS399
QUAD 2-PORT REGISTER
The SN54 / 74LS398 and SN54 / 74LS399 are Quad 2-Port Registers. They
are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources). The selected data is transferred to the output register
on the LOW-to-HIGH transition of the Clock input. The SN54/ 74LS398 features both Q and Q inputs, while the SN54/ 74LS399 has only Q outputs.
•
•
•
•
QUAD 2-PORT REGISTER
LOW POWER SCHOTTKY
Select From Two Data Sources
Fully Positive Edge-Triggered Operation
Both True and Complemented Outputs on SN54/ 74LS398
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
J SUFFIX
CERAMIC
CASE 620-09
16
1
SN54 / 74LS398
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
SN54 / 74LS399
J SUFFIX
CERAMIC
CASE 732-03
20
PIN NAMES
S
CP
I0a – I0d
I1a – I0d
Qa – Qd
Qa – Qd
Common Select Input
Clock (Active HIGH Going Edge) Input
Data Inputs From Source 0
Data Inputs From Source 1
Register True Outputs (Note b)
Register Complementary Outputs
(Note b)
D SUFFIX
SOIC
CASE 751B-03
1
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
10 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
FAST AND LS TTL DATA
5-557
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
20
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXDW
SN74LSXXXD
Ceramic
Plastic
SOIC
SOIC
SN54/74LS398 • SN54/74LS399
FUNCTIONAL BLOCK DIAGRAM
IOA
S
QA
S
IIA
R
IOB
*
S
QA
QB
IIB
R
IOC
*
QB
QC
S
IIC
R
IOD
*
QC
QD
S
IID
R
*
QD
* SN54 / 74LS398 only
FUNCTIONAL DESCRIPTION
The SN54 / 74LS398 and SN54 / 74LS399 are high-speed
Quad 2-Port Registers. They select four bits of data from two
sources (Ports) under the control of a common Select Input
(S). The selected data is transferred to a 4-Bit Output Register
synchronous with the LOW-to-HIGH transition of the Clock in-
put (CP). The 4-Bit RS type output register is fully edge-triggered. The Data inputs (I) and Select inputs (S) must be stable
only a setup time prior to and hold time after the LOW-to-HIGH
transition of the Clock input for predictable operation. The
SN54 / 74LS398 has both Q and Q Outputs available.
FUNCTION TABLE
INPUTS
OUTPUTS
S
I0
I1
Q
Q*
I
I
X
L
H
I
h
X
H
L
h
X
I
L
H
h
X
h
H
L
*SN54 / 74LS398 only
I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-558
SN54/74LS398 • SN54/74LS399
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
– 0.4
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
13
mA
VCC = MAX
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tPLH
tPHL
Parameter
Propagation Delay,
Clock to Output Q
Min
Typ
Max
Unit
Test Conditions
18
21
27
32
ns
VCC = 5.0 V
CL = 15 pF
FAST AND LS TTL DATA
5-559
SN54/74LS398 • SN54/74LS399
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
Unit
Max
tW
Clock Pulse Width
20
ns
ts
Data Setup Time
25
ns
ts
Select Setup Time
45
ns
th
Hold Time, Any Input
0
ns
DEFINITIONS OF TERMS
SETUP TIME(ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.
HOLD TIME(th) — is defined as the minimum time following
Test Conditions
VCC = 5.0 V
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative Hold Time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
*The shaded areas indicate when the input is permitted to change for predictable output performance.
FAST AND LS TTL DATA
5-560
Case 751B-03 D Suffix
16-Pin Plastic
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FAST AND LS TTL DATA
5-561
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FAST AND LS TTL DATA
5-562