Mitsubishi MH4V644AXJJ-6S Fast page mode 268435456-bit (4194304-word by 64-bit)dynamic ram Datasheet

MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
ADDRESS
This is family of 4194304 - word by 64 - bit dynamic RAM
module. This consists of four industry standard 4Mx16 dynamic
RAMs in TSOP and one industry EEPROM in TSSOP.
The mounting of TSOP on a card edge dual in line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module,suitable for easy
interchange of addition of modules.
Part No.
MH4V64AXJJ-5,5S
50
13
25
13
90
MH4V64AXJJ-6,6S
60
15
30
15
110
MH4V644AXJJ-5,5S
50
13
25
13
90
MH4V644AXJJ-6,6S
60
15
30
15
110
Refresh
MH4V64AXJJ
A0~A12
/RAS only Ref,Normal R/W
A0~A8 CBR Ref,Hidden Ref
MH4V644AXJJ
A0~A11
A0~A9
/RAS only Ref,Normal R/W
CBR Ref,Hidden Ref
Refresh
Cycle
8192/64ms
4096/64ms
4096/64ms
APPLICATION
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
FEATURES
RAS
CAS Address
OE
access access access access Cycle
time
time
time
time
time (min.ns)
(max.ns) (max.ns) (max.ns) (max.ns)
Row Add. Col Add.
*:Applicable to self refresh version(MH4V64/644AXJJ-5S,-6S)
only
single 3.3V± 0.3V supply
Low stand-by power dissipation
7.2mW- - - - - - - - - LVCMOS input level
operating power dissipation
MH4V64AXJJ-5,5S - - - - - 1584 mW(max.)
MH4V64AXJJ-6,6S - - - - - 1440mW(max.)
MH4V644AXJJ-5,5S - - - - 2016 mW(max.)
MH4V644AXJJ-6,6S - - - - 1872 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output LVTTL compatible and low capacitance
Utilizes industry standard 4Mx16 RAMs in TSOP
and industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx4)
Fast page mode , Read-modify-write,
CAS before RAS refresh,Hidden refresh capabilities.
Early-write mode,OE to control output buffer
impedance.
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
1
Vss
2
Vss
73
/OE
74
3
DQ0
4
DQ32
75
Vss
76
RFU
Vss
5
DQ1
6
DQ33
77
Reserved
78
Reserved
7
DQ2
8
DQ34
79
Reserved
80
Reserved
9
DQ3
10
DQ35
81
Vcc
82
Vcc
11
Vcc
12
Vcc
83
DQ16
84
DQ48
13
DQ4
14
DQ36
85
DQ17
86
DQ49
15
DQ5
16
DQ37
87
DQ18
88
DQ50
17
DQ6
18
DQ38
89
DQ19
90
DQ51
19
DQ7
20
DQ39
91
Vss
92
Vss
21
Vss
22
Vss
93
DQ20
94
DQ52
23
/CAS0
24
/CAS4
95
DQ21
96
DQ53
25
/CAS1
26
/CAS5
97
DQ22
98
DQ54
27
Vcc
28
Vcc
99
DQ23
100
DQ55
29
A0
30
A3
101
Vcc
102
Vcc
31
A1
32
A4
103
A6
104
A7
33
A2
34
A5
105
A8
106
A11
35
Vss
36
Vss
107
Vss
108
Vss
37
DQ8
38
DQ40
109
A9
110
A12/NC(note)
39
DQ9
40
DQ41
111
A10
112
NC
41
DQ10
42
DQ42
113
Vcc
114
Vcc
43
DQ11
44
DQ43
115
/CAS2
116
/CAS6
45
Vcc
46
Vcc
117
/CAS3
118
/CAS7
47
DQ12
48
DQ44
119
Vss
120
Vss
49
DQ13
50
DQ45
121
DQ24
122
DQ56
51
DQ14
52
DQ46
123
DQ25
124
DQ57
53
DQ15
54
DQ47
125
DQ26
126
DQ58
55
Vss
56
Vss
127
DQ27
128
DQ59
57
Reserved
58
Reserved
129
Vcc
130
Vcc
59
Reserved
60
Reserved
131
DQ28
132
DQ60
61
RFU
62
FRU
133
DQ29
134
DQ61
63
Vcc
64
Vcc
135
DQ30
136
DQ62
65
RFU
66
RFU
137
DQ31
138
DQ63
67
/WE
68
RFU
139
Vss
140
Vss
69
/RAS0
70
RFU
141
SDA
142
SCL
71
NC
72
RFU
143
Vcc
144
Vcc
RFU:Reserved Future Use
NC,RFU,Reserved: NO CONNECTION
Note:A12 ... MH4V64AXJJ , NC ... MH4V644AXJJ
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MITSUBISHI LSIs
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MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram
Address
/OE
/WE
/RAS0
/CAS0
/CAS4
/LCAS /RAS /WE /OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/CAS1
/UCAS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
D0
/CAS2
/LCAS /RAS /WE /OE
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/CAS5
/UCAS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
D2
/CAS6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/CAS3
/UCAS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
D1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/CAS7
/UCAS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
D3
SERIAL PD
Vcc
D0 to D3
SCL
C1~C4
Vss
A0 A1 A2
SDA
D0 to D3
Vss
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5,-6)
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
FPM DRAM
01
3
# Row Addresses on this assembly
A0-A12
0D
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
1bank
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
3.3V LVTTL
02
9
RAS# access time of this assembly
10
CAS# access time of this assembly
-5
50ns
32
-6
60ns
3C
-5
13ns
0D
-6
15ns
0F
11
DIMM Configuration type (Non-parity,Parity,ECC)
non parity
00
12
Refresh Rate/Type
N/R(15.625uS)
00
13
DRAM width,Primary DRAM
x16
10
14
Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61
Superset Memory type(may be used in future)
open
00
62
SPD Data Revision Code
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
32
Check sum for -6
3E
64-71
Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
73-90
Manufacturer's Part Number
NC,USA
03
Germany
04
MH4V64AXJJ-5
4D483456363441584A4A2D352D35202020202020
MH4V64AXJJ-6
4D483456363441584A4A2D362D36202020202020
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacturer Specific Data
open
00
Reserved
open
00
open
00
126-127
128-255
Open User Free-Form area not defined
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MITSUBISHI LSIs
Preliminary
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to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5S,-6S)
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
FPM DRAM
01
3
# Row Addresses on this assembly
A0-A12
0D
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
1bank
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
3.3V LVTTL
02
9
RAS# access time of this assembly
10
CAS# access time of this assembly
-5S
50ns
32
-6S
60ns
3C
-5S
13ns
0D
-6S
15ns
0F
11
DIMM Configuration type (Non-parity,Parity,ECC)
non parity
00
12
Refresh Rate/Type
S/R(15.625uS)
80
13
DRAM width,Primary DRAM
x16
10
14
Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61
Superset Memory type(may be used in future)
open
00
62
SPD Data Revision Code
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
B2
Check sum for -6
BE
64-71
Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufacturer's Part Number
MH4V64AXJJ-5S 4D483456363441584A4A2D355335532020202020
MH4V64AXJJ-6S 4D483456363441584A4A2D365336532020202020
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacturer Specific Data
open
00
126-127
Reserved
open
00
128-255
Open User Free-Form area not defined
open
00
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MITSUBISHI LSIs
Preliminary
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to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5,-6)
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
FPM DRAM
01
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A9
0A
5
# Module Banks on this assembly
1bank
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
3.3V LVTTL
02
9
RAS# access time of this assembly
10
CAS# access time of this assembly
-5
50ns
32
-6
60ns
3C
-5
13ns
0D
-6
15ns
0F
11
DIMM Configuration type (Non-parity,Parity,ECC)
non parity
00
12
Refresh Rate/Type
N/R(15.625uS)
00
13
DRAM width,Primary DRAM
x16
10
14
Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61
Superset Memory type(may be used in future)
open
00
62
SPD Data Revision Code
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
32
Check sum for -6
3E
64-71
Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufacturer's Part Number
MH4V644AXJJ-5 4D48345636343441584A4A2D352D352020202020
91-92
Revision Code
PCB revision
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
MH4V644AXJJ-6 4D48345636343441584A4A2D362D362020202020
rrrr
99-125
Manufacturer Specific Data
open
00
126-127
Reserved
open
00
128-255
Open User Free-Form area not defined
open
00
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MITSUBISHI LSIs
Preliminary
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to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5S,-6S)
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
0
1
Defines # bytes written into serial memory at module mfgr
128
80
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
FPM DRAM
01
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A9
0A
5
# Module Banks on this assembly
1bank
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
9
RAS# access time of this assembly
10
CAS# access time of this assembly
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
S/R(15.625uS)
80
13
DRAM width,Primary DRAM
x16
10
3.3V LVTTL
02
-5S
50ns
32
-6S
60ns
3C
-5S
13ns
0D
15ns
0F
non parity
00
-6S
14
Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61
Superset Memory type(may be used in future)
open
00
62
SPD Data Revision Code
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5S
B2
Check sum for -6S
BE
64-71
Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufacturer's Part Number
MH4V644AXJJ-5S 4D48345636343441584A4A2D3553355320202020
MH4V644AXJJ-6S 4D48345636343441584A4A2D3653365320202020
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacturer Specific Data
open
00
126-127
Reserved
open
00
128-255
Open User Free-Form area not defined
open
00
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
FUNCTION
The MH4V64/644AXJJ provide, in addition to
normal read, write, and read-modify-write
operations,
a number of other functions, e.g., Fast page mode,
/RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/RAS-only refresh
Hidden refresh
/CAS before /RAS refresh
Standby
Self refresh *
/RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
/CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
ACT
/W
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
NAC
Input/Output
Remark
Row Column Input Output Refresh
/OE address
address
ACT
APD
APD
OPN
VLD
YES
Fast page
DNC
APD
APD
VLD
OPN
YES
mode
DNC
APD
APD
VLD
IVD
YES
identical
ACT
APD
APD
VLD
VLD
YES
DNC
APD
DNC
DNC
OPN
YES
ACT
APD
DNC
OPN
VLD
YES
DNC
DNC
DNC
DNC
OPN
YES
DNC
DNC
DNC
DNC
OPN
NO
DNC
DNC
DNC
DNC
OPN
YES
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
*MH4V64/644AXJJ-5S,-6S only
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature (SOJ)
Conditions
With respect to Vss
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
4
0~ 70
-40~ 100
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Unit
V
V
V
mA
W
°C
°C
(Ta=0~ 70°C, unless otherwise noted) (Note 1)
Min
3.0
0
2.0
**-0.3
Limits
Nom
3.3
0
Max
3.6
0
Vcc+0.3
0.8
Unit
V
V
V
V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
[MH4V64AXJJ]
Symbol
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
Parameter
VOH
VOL
IOZ
II
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply
-5,-5S
ICC1 (AV) current
from Vcc operating (Note 3,4,5) -6,-6S
ICC2
Supply current from Vcc , stand-by
Average supply current
-5,-5S
ICC4(AV) from Vcc
Fast-Page-Mode (Note 3,4,5) -6,-6S
Average supply current
-5,-5S
from Vcc
ICC6(AV) /CAS before /RAS refresh
mode
(Note 3,5) -6,-6S
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V≤VOUT≤3.6V
0V≤VIN≤3.6V, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS≥Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.,/W≥Vcc-0.2
output open
Min
2.4
0
-10
-40
Limits
Typ Max
Vcc
0.4
10
40
Unit
V
V
uA
uA
440
mA
400
4
2
400
mA
mA
360
560
mA
520
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
MIT-DS-0072-0.5
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ELECTRIC
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MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
ELECTRICAL CHARACTERISTICS
[MH4V644AXJJ]
Symbol
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
Parameter
VOH
VOL
IOZ
II
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply
-5,-5S
ICC1 (AV) current
from Vcc operating (Note 3,4,5) -6,-6S
ICC2
Supply current from Vcc , stand-by
Average supply current
-5,-5S
ICC4(AV) from Vcc
Fast-Page-Mode (Note 3,4,5) -6,-6S
Average supply current
-5,-5S
from Vcc
ICC6(AV) /CAS before /RAS refresh
(Note 3,5) -6,-6S
mode
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V≤VOUT≤3.6V
0V≤VIN≤3.6V, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS≥Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.,/W≥Vcc-0.2
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
Min
2.4
0
-10
-40
Limits
Typ Max
Vcc
0.4
10
40
Unit
V
V
uA
uA
560
mA
520
4
2
420
mA
mA
380
560
mA
520
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
CAPACITANCE
Symbol
CI (A)
CI
C(CAS)
C(DQ)
C(SDA)
C(SCL)
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions
Input capacitance, address inputs
Input capacitance, clock inputs except CAS
Input capacitance, CAS
Input/Output capacitance,DATA
Input/Output capacitance,SDA
Input capacitance, SCL
MIT-DS-0072-0.5
VI=Vss
f=1MHZ
Vi=25mVrms
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ELECTRIC
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Min
Limits
Typ Max
40
45
25
25
12
12
Unit
pF
pF
pF
pF
pF
pF
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless
otherwise noted , see notes 6,13,14)
Limits
Symbol
tCAC
tRAC
tAA
tCPA
tOEA
tCLZ
tOFF
tOEZ
Parameter
(Note 7,8)
Access time from /CAS
(Note 7,9)
Access time from /RAS
(Note 7,10)
Column address access time
(Note 7,11)
Access time from /CAS precharge
(Note 7)
Access time from /OE
Output low impedance time from /CAS low (Note 7)
(Note 12)
Output disable time after /CAS high
(Note 12)
Output disable time after /OE high
-5,-5S
Min Max
13
50
25
30
13
5
13
0
13
0
-6,-6S
Min Max
15
60
30
35
15
5
15
0
15
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max).
9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11: Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ I ±10uAI) and
is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Symbol
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Parameter
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
(Note15)
(Note16)
(Note17)
(Note18)
(Note18)
(Note19)
(Note19)
(Note20)
Limits
-5,-5S
-6,-6S
Min
Max Min
Max
64
64
30
40
18
37
20
45
10
5
0
0
10
10
13
15
25
30
0
0
5
10
0
0
8
10
13
15
0
0
0
0
13
15
13
15
1
50
1
50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics
are 2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min)=tRAH(min)+2tT+tASC(min) .
16: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by
tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
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ELECTRIC
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MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read and Refresh Cycles
Symbol
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tOCH
tORH
Parameter
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
/CAS hold time after /OE low
/RAS hold time after /OE low
Limits
-5,-5S
-6,-6S
Min Max Min Max
90
110
50 10000
60 10000
13 10000
15 10000
50
60
13
15
0
0
(Note 21)
0
0
(Note 21) 10
10
25
30
13
15
13
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Symbol
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Parameter
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
(Note 23)
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
/OE hold time after /W low
MIT-DS-0072-0.5
Limits
-5,-5S
-6,-6S
Min Max Min Max
90
110
50 10000 60 10000
13 10000 15 10000
50
60
13
15
0
0
10
10
13
15
13
15
10
10
0
0
10
10
13
15
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ELECTRIC
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Symbol
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Parameter
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /W low
Date hold time after /W low
/OE hold time after /W low
(Note22)
(Note23)
(Note23)
(Note23)
Limits
-5,-5S
-6,-6S
Min Max Min Max
130
150
85 10000 95 10000
50 10000 50 10000
85
95
50
50
0
0
30
30
65
75
40
45
15
15
15
15
10
10
0
0
10
10
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min)
and tCPWD≥tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until
/CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Symbol
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Parameter
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to /W low
(Note25)
(Note26)
(Note23)
Limits
-5,-5S
-6,-6S
Min Max Min Max
35
40
70
75
85 125000 100 100000
5
10
10
15
30
35
30
35
Unit
ns
ns
ns
ns
ns
ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only.If tCP≥tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Symbol
tCSR
tCHR
tRSR
tRHR
Parameter
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
Limits
-5,-5S
-6,-6S
Min Max Min Max
5
5
10
10
10
10
10
10
Unit
ns
ns
ns
ns
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
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ELECTRIC
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item,line -5S / -6S. The other characteristics
and requirements then below are same as normal device.
ELECTRIC CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless
Symbol
Parameter
otherwise noted) (Note 2)
Test conditions
Min
/RAS=/CAS<0.2V
Average supply current
ICC9(AV)* from Vcc Self-Refresh mode
-5S,-6S /OE=/W=A0~A12(A11)=Vcc-0.2V or
0.2V output=Vcc-0.2V,0.2V or open
(Note 6)
TIMING REQUIREMENTS
Limits
Typ Max
1600
Unit
µA
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
Symbol
Parameter
-5S
Min
tRASS
CBR Self Refresh RAS low pulse width
tRPS
CBR Self Refresh RAS high precharge time
tCHS
CBR Self Refresh RAS hold time
Max
-6S
Min
Unit
Max
100
100
us
90
110
ns
- 50
- 50
ns
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS≤ 64 ms and tSN ≤ 64 ms.
tSN
tNS
Self refresh period
DISTRIBUTED REFRESH
< 64 ms >
DISTRIBUTED REFRESH
< 64 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS ≤ 16ms and tSN ≤ 16 ms.
tSN
tNS
Self refresh period
BURST REFRESH
< 64 ms >
MIT-DS-0072-0.5
BURST REFRESH
< 64 ms >
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Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
Timing Diagrams
Read Cycle
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Note 28)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
VIH
Address
tRAD
tRAL
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
tCPN
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tRRH
tRCH
tRCS
VIH
W
VIL
tDZC
DQ
(INPUTS)
tCDD
VIH
Hi-Z
VIL
tCAC
tAA
tOFF
tCLZ
DQ
(OUTPUTS)
VOH
DATA VALID
Hi-Z
Hi-Z
VOL
tRAC
tOEZ
tDZO
tOEA
tOCH
tODD
VIH
OE
VIL
tORH
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Note 28
Indicates the invalid output.
MIT-DS-0072-0.5
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ELECTRIC
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Early write)
tWC
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
CAS
tRCD
tRSH
tCAS
tRPC
tCRP
VIH
VIL
tASR
Address
VIH
tASR
tRAH
tCAH
tASC
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tWCS
W
tWCH
VIH
VIL
tDS
DQ
(INPUTS)
VIH
tDH
DATA VALID
VIL
DQ
(OUTPUTS)
VOH
Hi-Z
VOL
OE
VIH
VIL
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ELECTRIC
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Delayed write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
VIH
Address
tRAH
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tCWL
tRWL
tWP
tRCS
VIH
W
VIL
tWCH
tDZC
VIH
DQ
(INPUTS)
tDS
tDH
DATA
VALID
Hi-Z
VIL
tCLZ
DQ
(OUTPUTS)
VOH
Hi-Z
Hi-Z
VOL
tDZO
tOEH
tOEZ
tODD
OE
VIH
VIL
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MITSUBISHI LSIs
Preliminary
Some of contents are subject
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tCRP
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tRAD
tASR
VIH
Address
tRAH
tCAH
tASC
ROW
ADDRESS
tASR
COLUMN
ADDRESS
VIL
ROW
ADDRESS
tAWD
tCWD
tRWD
tRCS
tCWL
tRWL
tWP
VIH
W
VIL
tDH
tDS
tDZC
VIH
DQ
(INPUTS)
DATA VALID
Hi-Z
VIL
tCAC
tAA
tCLZ
DQ
(OUTPUTS)
VOH
DATA
VALID
Hi-Z
VOL
tODD
tDZO
OE
Hi-Z
tRAC
tOEA
tOEZ
tOEH
VIH
VIL
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRP
tRC
tRAS
tRAS
tRP
VIH
RAS
VIL
tRPC
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH
CAS
VIL
tCPN
tASR
Address
VIH
ROW
ADDRESS
COLUMN
ADDRESS
VIL
tRCH tRSR
tRHR
tRSR
tRHR
tRCS
VIH
W
VIL
DQ
(INPUTS)
VIH
VIL
tOFF
DQ
(OUTPUTS)
VOH
Hi-Z
VOL
tOEZ
VIH
OE
VIL
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Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tCRP
tRCD
tRSH
tCHR
VIH
CAS
VIL
tRAD
tASR
VIH
Address
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tRCS
tRAL
tRRH
VIH
W
VIL
tDZC
DQ
(INPUTS)
tCDD
VIH
Hi-Z
VIL
tCAC
tAA
tOFF
tCLZ
DQ
(OUTPUTS)
VOH
Hi-Z
Hi-Z
DATA VALID
VOL
tRAC
tDZO
tOEA
tORH
tOEZ
tODD
VIL
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
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MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tPC
tRCD
tCAS
tCP
tCAS
tRSH
tCAS
tCP
VIH
CAS
VIL
tCPRH
tRAD
tASR
Address
VIH
tRAH
tASC
ROW
ADDRESS
tASC
tCAH
COLUMN-1
tCAH
tASC
COLUMN-2
tCAH
tASR
ROW
ADDRESS
COLUMN-3
VIL
tRAL
tRCS
tRCS tRCH
tRCH
tRRH
tRCS
tRCH
VIH
W
VIL
tDZC
DQ
(INPUTS)
tDZC
tDZC
VIH
Hi-Z
VIL
Hi-Z
tCAC
tOFF
tCAC
tAA
VOH
tCAC
tOFF
tAA
tCLZ
tCLZ
DATA
VALID-1
Hi-Z
tOFF
tAA
tCLZ
DQ
(OUTPUTS)
tCDD
DATA
VALID-2
DATA
VALID-3
VOL
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
tCPA
tOEA
tOCH
tOEZ
tOEA
tOCH
tOEZ
VIL
OE
VIH
tDZO
tODD
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 21 / 25 )
tODD
tDZO
tODD
tORH
26/Feb./1997
MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tPC
tCAS
tCP
tCAS
tRSH
tCAS
tCP
VIH
CAS
VIL
tASR
Address
VIH
tRAH
ROW
ADDRESS
tCAH
tASC
tCAH
tASC
COLUMN-1
COLUMN-2
tCAH
tASC
COLUMN-3
tASR
ROW
ADDRESS
VIL
tWCS
tWCH
tWCS
tWCH
tWCS
tDS
tDH
tDS
tDH
tDS
tWCH
VIH
W
VIL
DQ
(INPUTS)
DQ
(OUTPUTS)
OE
VIH
DATA
VALID-1
DATA
VALID-2
tDH
DATA
VALID-3
VIL
VOH
Hi-Z
VOL
VIH
VIL
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 22 / 25 )
26/Feb./1997
MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
tPC
tCAS
tCAS
tCP
VIH
CAS
VIL
tASR
Address
VIH
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN-1
tCAH
tRWL
tCWL
ROW
ADDRESS
COLUMN-2
VIL
tCWL
tRCS
tASR
tPCS
tWP
tWP
VIH
W
VIL
tWCH
tDZC
DQ
(INPUTS)
tWCH
tDH
tDS
VIH
DATA
VALID-1
Hi-Z
VIL
tCLZ
DQ
(OUTPUTS)
tDZC
tDS
tDH
DATA
VALID-2
Hi-Z
tCLZ
VOH
Hi-Z
Hi-Z
Hi-Z
VOL
tDZO
tOEZ
tOEZ
tODD
tDZO
tODD
tOEH
VIH
OE
VIL
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 23 / 25 )
26/Feb./1997
MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
tRWL
tRCD
tCAS
tPRWC
tCAS
tCP
CAS
VIH
VIL
tRAD
tASR
VIH
Address
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN-1
tCAH
tCWL
ROW
ADDRESS
COLUMN-2
VIL
tAWD
tRCS
tAWD
tCWL
tCWD
tCWD
tRCS
tWP
W
tASR
tWP
VIH
VIL
tRWD
tCPWD
tDZC
DQ
(INPUTS)
VIH
tDS
DATA
VALID-1
Hi-Z
tCAC
VIL
tDH
tDS
tDZC
tAA
tAA
DATA
VALID-1
Hi-Z
tRAC
tDZO
OE
tCLZ
VOH
VOL
DATA
VALID-2
Hi-Z
tCAC
tCLZ
DQ
(OUTPUTS)
tDH
tCPA
tODD
tOEA
DATA
VALID-1
Hi-Z
tOEZ
Hi-Z
tODD
tDZO
tOEZ
tOEH
tOEA
VIH
VIL
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 24 / 25 )
26/Feb./1997
MITSUBISHI LSIs
Preliminary
MH4V64/644AXJJ-5,-6,-5S,-6S
Some of contents are subject
to change without notice.
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Outline
3.63MAX
20
25.40
67.6
3.3
23.2
29
3.7
23.2
MIT-DS-0072-0.5
4.6
32.8
1.00
32.8
MITSUBISHI
ELECTRIC
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26/Feb./1997
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