Samsung K7D321874A-HGC37 32mb a-die ddr sram specification Datasheet

K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
32Mb A-die DDR SRAM Specification
153FCBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
Document Title
32M DDR SYNCHRONOUS SRAM
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial document.
Dec. 2002
Advance
Rev. 0.1
Remove /G operation thru the Spec.
- Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION, TRUTH TABLE and TIMING WAVEFORMs
Jan. 2003
Advance
Feb. 2003
Advance
Add 300MHz Speed bin.
- Add Part ID at ORDERING INFORMATION & IDD30 at DC CHARACTERISTICS
Change ILI and ILo at DC CHARCATERISTICS
- ILI : MIN -1 -> -3, MAX 1 -> 3, ILo : MIN -1 -> -5, MAX 1 -> 5
Change the comment of Programmable Impedance Output Driver.
Change RECOMMENDED DC OPERATING CONDITIONS.
- VREF : Min 0.68 -> 0.65, Max 1.0 -> 0.85
Change PIN CAPACITANCE : CIN : 3 -> 3.1
Change AC TEST CONDITIONS : TR/RF: 0.4/0.4 -> 0.5/0.5
Change AC TIMING CHARACTERISTICS
- tCHCL : tKHKL -0.1 -> tKHKL -0.2 , tCLCH : tKLKH -0.1 -> tKLKH -0.2
- tCXCV : 2.10 -> 2.30
Rev 0.2
Change VDDQ RANGE
- In FEATURES : 1.5V VDDQ -> 1.5~.1.8V VDDQ
- In RECOMENDED DC OPERATING CONDITIONS : Max VDDQ : 1.6 -> 1.9
Change TRUTH TABLE : Remove Clock Stop
Change DC CHARACTERISTICS
- x36 IDD :
IDD50 : 950 -> 1050, IDD45 : 850 -> 950, IDD40: 800 -> 860, IDD30: 750 -> 760
- x18 IDD:
IDD50 : 850 -> 1000, IDD45 : 800 -> 900, IDD40: 750 -> 810, IDD30: 700 -> 710
- ISB1 : 150 -> 200
Change PIN CAPACITANCE : CIN : 3.1 -> 3.2, COUT : 4 -> 4.2
Change AC TIMING CHARACTERISTICS
- MIN tKHKL, tKHKL : -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4
- MIN tAVKH, tBVKH, tKHAX, tKHBX : -45 : 0.25 -> 0.27
- tKXCV MIN/MAX : 0.8/2.3 -> 1.0/2.5
Change PACKAGE THERMAL CHARACTERISTICS
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-2-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
Revision History
Rev No.
History
Draft Data
Remark
Rev 0.3
Change DC CHARACTERISTICS
- x36 IDD :
IDD50 : 1050 -> 1150 , IDD45 : 950 -> 1050, IDD40: 860 -> 960, IDD30: 760 ->
860
- x18 IDD:
IDD50 : 1000 -> 1100, IDD45 : 900 -> 1000, IDD40: 810 -> 910, IDD30: 710 ->
810
- ISB1 : 200 -> 300
May. 2003
Advance
Rev 0.4
Change 300Mhz speed bin to 333Mhz
Jun. 2003
Advance
Rev 0.5
Change PIN CONFIGURATIONS
- change DQ pin number
Aug. 2003
Advance
Change AC CHARACTERISTICS
- tCHCL, tCLCH : -/+0.2 -> -/+ 0.1
Rev 0.6
Change AC CHARACTERISTICS
- Remove : tQTRK, tCXCV
- Add : tCXCH,tCXCL,tCHQV,tCLQV,tCHQX,tCLQX,tCLQZ,tCHLZ
Sep. 2003
Advance
Rev 0.7
Add Power-Up/Power-Down Supply Voltage Sequencing
Sep. 2003
Advance
Rev 0.8
Change PACKAGE PIN CONFIGURATIONS
- Remove the number at DQ pins
Oct. 2003
Advance
Rev 0.9
Change Bin
- 50, 45, 40, 33 -> 40, 37, 33
Feb. 2003
Advance
Rev 1.0
Change the word in READ OPERATION
- at least one NOP -> at least two NOP
Mar. 2003
Final
Rev 1.1
Add AC INPUT CHARACTERISTICS and AC INPUT DEFINITION.
Apr. 2004
Final
Rev 1.2
Remove the comment for DDR3 from Spec.
Jun. 2004
Final
Rev 1.3
Modify AC TIMING CHARACTERISTICS
- clock high/low pulse width : -40 : 1.2 -> 1.15
- remove min. value of tCHQV and tCLQV
Jan. 2005
Final
Rev 1.4
Add Pb free.
Oct. 2005
Final
-3-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
FEATURES
• Registered Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Flip Chip Ball Grid Array Package(14mmx22mm)
• No Output enable support.
•
•
•
•
•
1Mx36 or 2Mx18 Organizations.
1.8~2.5V VDD/1.5V ~1.8VDDQ.
HSTL Input and Outputs.
Single Differential HSTL Clock.
Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Registered Addresses, Burst Control and Data Inputs.
GENERAL DESCRIPTION
The K7D323674A and K7D321874A are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
1,048,576 words by 36 bits for K7D323674A and 2,097,152 words by 18 bits for K7D321874A, fabricated using Samsung's
advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access
time for all SDR and DDR operations.
The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid
Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Part Number
Organization
K7D323674A-H(G)C40
K7D323674A-H(G)C37
Maximum
Frequency
400MHz
1Mx36
375MHz
K7D323674A-H(G)C33
333MHz
K7D321874A-H(G)C40
400MHz
K7D321874A-H(G)C37
2Mx18
K7D321874A-H(G)C33
375MHz
333MHz
* G : Lead free package
-4-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
Address
Register
18(or 19)
(Burst Address)
CE
Clock
Buffer
K,K
20(or 21)
Advance
Co
Control
B3
SD/DD
Data Out
36(or 18)x2
Synchronous
Select
&
R/W control
W/D
Array
(Burst Write
Address)
20(or 21)
36(or 18)x2
18(or 19)
36(or18)x2
2 : 1 MUX
CE
Data In
36(or18)x2
S/A Array
Write
Address
Register
(2 stage)
CE
B2
Memory Array
1Mx36
or
(2Mx18)
Dec.
Burst
Counter
Comparator
B1
2:1
MUX
Write Buffer
Strobe_out
Data Output Strobe
LD
Echo Clock
Output
Output
Buffer
R/W
Data In
Register
(2 stage)
Data Output Enable
State Machine
Internal
Clock
Generator
36(or 18)
DQ
XDIN
CQ,CQ
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
Pin Description
K, K
Differential Clocks
TCK
JTAG Test Clock
SA
Synchronous Address Input
TMS
JTAG Test Mode Select
Synchronous Burst Address Input (SA0 = LSB)
TDI
JTAG Test Data Input
Synchronous Data I/O
TDO
JTAG Test Data Output
Differential Output Echo Clocks
VREF
HSTL Input Reference Voltage
SA0, SA1
DQ
CQ, CQ
B1
Load External Address
VDD
Power Supply
B2
Burst R/W Enable
VDDQ
Output Power Supply
B3
Single/Double Data Selection
VSS
GND
Linear Burst Order
NC
No Connection
LBO
ZQ
Output Driver Impedance Control Input
-5-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D323674A(1Mx36)
1
2
3
4
5
6
7
8
9
A
VSS
VDDQ
SA
SA
ZQ
SA
SA
VDDQ
VSS
B
DQ
DQ
SA
VSS
B1
VSS
SA
DQ
DQ
C
VSS
VDDQ
SA
SA
SA
SA
SA
VDDQ
VSS
D
DQ
DQ
SA
Vss(5)
VDD
Vss(6)
SA
DQ
DQ
E
VSS
VDDQ
VSS
VDD
VREF
VDD
VSS
VDDQ
VSS
F
DQ
CQ
DQ
VDD
VDD
VDD
DQ
CQ
DQ
G
VSS
VDDQ
VSS
VSS
K
VSS
VSS
VDDQ
VSS
H
DQ
DQ
DQ
VDD
K
VDD
DQ
DQ
DQ
J
VSS
VDDQ
VSS
VDD
VDD
VDD
VSS
VDDQ
VSS
K
DQ
DQ
DQ
VSS
B2
VSS
DQ
DQ
DQ
L
VSS
VDDQ
VSS
LBO
B3
MODE(7)
VSS
VDDQ
VSS
M
DQ
CQ
DQ
VDD
VDD
VDD
DQ
CQ
DQ
N
VSS
VDDQ
VSS
VDD
VREF
VDD
VSS
VDDQ
VSS
P
DQ
DQ
NC*
VSS
VDD(2)
VSS
SA
DQ
DQ
R
VSS
VDDQ
VDD(4)
SA
SA1
SA
VDD(3)
VDDQ
VSS
T
DQ
DQ
SA
VSS
SA0
VSS
SA
DQ
DQ
U
VSS
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
1
2
3
4
5
6
7
8
9
VSS
VDDQ
SA
SA
ZQ
SA
SA
VDDQ
VSS
K7D321874A(2Mx18)
A
B
NC
DQ
SA
VSS
B1
VSS
SA
NC
DQ
C
VSS
VDDQ
SA
SA
SA
SA
SA
VDDQ
VSS
D
DQ
NC
SA
Vss(5)
VDD
Vss(6)
SA
DQ
NC
E
VSS
VDDQ
VSS
VDD
VREF
VDD
VSS
VDDQ
VSS
F
NC
CQ
NC
VDD
VDD
VDD
DQ
NC
DQ
G
VSS
VDDQ
VSS
VSS
K
VSS
VSS
VDDQ
VSS
H
DQ
NC
DQ
VDD
K
VDD
NC
DQ
NC
J
VSS
VDDQ
VSS
VDD
VDD
VDD
VSS
VDDQ
VSS
K
NC
DQ
NC
VSS
B2
VSS
DQ
NC
DQ
L
VSS
VDDQ
VSS
LBO
B3
MODE(7)
VSS
VDDQ
VSS
M
DQ
NC
DQ
VDD
VDD
VDD
NC
CQ
NC
N
VSS
VDDQ
VSS
VDD
VREF
VDD
VSS
VDDQ
VSS
P
NC
DQ
SA
VSS
VDD(2)
VSS
SA
NC
DQ
R
VSS
VDDQ
VDD(4)
SA
SA1
SA
VDD(3)
VDDQ
VSS
T
DQ
NC
SA
VSS
SA0
VSS
SA
DQ
NC
U
VSS
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
(1) Variable address see "Variable address assignment table"
(2) Variable address see "Variable address assignment table"
(3) Variable address see "Variable address assignment table"
(4) Variable address see "Variable address assignment table"
(5) Variable address see "Variable address assignment table"
(6) Variable address see "Variable address assignment table"
(7) Internally NC
-6-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
VARIABLE ADDRESS ASSIGNMENT TABLE
Density
Ball 5C
(1)
Ball 5P
(2)
Ball 7R
(3)
Ball 3R
(4)
Ball 4D
(5)
Ball 6D
(6)
32 Mb
SA
VDD
VDD
VDD
Vss
Vss
64 Mb
SA
SA
VDD
VDD
Vss
Vss
144 Mb
NC
SA
SA
SA
Vss
Vss
288 Mb
SA
SA
SA
SA
Vss
Vss
576 Mb
NC
SA
SA
SA
SA
SA
1152 Mb
SA
SA
SA
SA
SA
SA
NOTE : - SRAM density definition beyond 144Mb will include the parity bits.
-7-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least two NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Output driver impedance is updated every 64 clock cycles of Non-Read operation (Write or NOP) but since the echo clock drivers are in operation even
during Non-Read operation, the impedance is update only the drivers are not in operation. Therefore impedance updates for "0s" or
pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. Furthermore, to guarantee optimum output
driver impedance after power up, the SRAM need 2048 deselect (or write) cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
-8-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
TRUTH TABLE
K
B1
B2
↑
H
L
↑
L
H
↑
L
H
↑
L
L
B3
DQ
Operation
X
Hi-Z
No Operation, Pipeline High-Z
H
DOUT
Load Address, Single Read
L
DOUT
Load Address, Double Read
H
DIN
Load Address, Single Write
↑
L
L
L
DIN
Load Address, Double Write
↑
H
H
X
B
Increment Address, Continue
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
OUTPUT TRISTATE TRUTH TABLE
K
Operation
DQ (n)
DQ (n+1)
↑
Write (B2=L)
X
High-Z
↑
Deslect (NOP) (B1=H, B2=L)
X
High-Z
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Case 1
Interleaved Burst
First Address
Fourth Address
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Linear Burst Mode
First Address
Fourth Address
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
-9-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
BUS CYCLE STATE DIAGRAM
LOAD
NEW ADDRESS
3
,B
3
B1
B1
B1
B1
,B
B2
B2
,B
B2
B2
,B
3
3
B1, B2
B1, B2
B1, B2
B1, B2
INCREMENT
ADDRESS
B1, B2
B1 , B2
B1, B2
B1 , B2
B1 , B2
B1, B2
POWER
UP
WRITE
DDR
INCREMENT
ADDRESS
B1 , B2
INCREMENT
ADDRESS
B1 , B2
INCREMENT
ADDRESS
READ
DDR
B1, B2
B1, B2
WRITE
SDR
B1, B2
B1, B2
READ
SDR
NO OP
NOTE :
1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)
B2 =(Read), B2 =(Write)
B3 =(Single Data Rate), B3 =(Double Data Rate)
- 10
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
VDDQ
-0.5 to 2.3
V
VIN
-0.5 to VDDQ+0.5 (2.3V MAX)
V
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
IOUT
25
mA
Storage Temperature
TSTR
-55 to 125
°C
Maxmum Junction Temperature
TJ
110
°C
Maxmum Power Dissipation
PD
3.0
W
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Core Power Supply Voltage
Parameter
VDD
1.7
2.5
2.6
V
Output Power Supply Voltage
VDDQ
1.4
1.5
1.9
V
VIH
VREF+0.1
-
VDDQ+0.3
V
1, 2
1, 3
Input High Level Voltage
Input Low Level Voltage
VIL
-0.3
-
VREF-0.1
V
Input Reference Voltage
VREF
0.68
0.75
1.0
V
Note
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time).
DC CHARACTERISTICS
Min
Max
Unit
Note
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
IDD40
IDD37
IDD33
-
960
940
900
mA
1,2
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
IDD40
IDD37
IDD33
-
910
890
850
mA
1,2
Stop Clock Standby Current
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
ISB1
-
300
mA
1
Input Leakage Current
(VIN=VSS or VDDQ)
ILI
-3
3
µA
Output Leakage Current
(VOUT=VSS or VDDQ)
ILO
-5
5
µA
VOH1
VDDQ/2
VDDQ
V
3
4
Parameter
Output High Voltage(Programmable Impedance Mode)
Symbol
Output Low Voltage(Programmable Impedance Mode)
VOL1
VSS
VDDQ/2
V
Output High Voltage(IOH=-0.1mA)
VOH2
VDDQ-0.2
VDDQ
V
Output Low Voltage(IOL=0.1mA)
VOL2
VSS
0.2
V
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 300Ω.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 300Ω.
- 11
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
PIN CAPACITANCE
Parameter
Input Capacitance
Data Output Capacitance
Symbol
Test Condition
TYP
Max
Unit
CIN
VIN=0V
-
3.2
pF
COUT
VOUT=0V
-
4.2
pF
Max
Unit
Note
V
-
VREF - 0.4
V
-
V
-
V
-
Note
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=500MHz)
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
AC Input Logic High
VIH (AC)
VREF + 0.4
AC Input Logic Low
VIL (AC)
Clock Input Differential Voltage
VDIF (AC)
VREF Peak-to-Peak AC Voltage
VREF (AC)
0.8
5% VREF (DC)
AC INPUT DEFINITION
CK
VDIF(AC)
CK
VIH(AC)
VREF
Setup
Time
VIL(AC)
Hold
Time
AC TEST CONDITIONS(TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V)
Symbol
Value
Unit
Input High/Low Level
Parameter
VIH/VIL
1.25/0.25
V
-
Input Reference Level
VREF
0.75
V
-
Input Rise/Fall Time
TR/TF
0.5/0.5
ns
-
0.75
V
-
Clock Input Timing Reference Level
Cross Point
V
-
Output Load
See Below
Output Timing Reference Level
- 12
-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
AC TEST OUTPUT LOAD
50Ω
0.75V
50Ω
5pF
25Ω
DQ
0.75V
50Ω
50Ω
0.75V
5pF
AC TIMING CHARACTERISTICS
PARAMETER
SYMBOL
-40
-37
-33
MIN
MAX
MIN
MAX
MIN
MAX
5.00
2.67
6.00
3.00
6.00
UNITS NOTES
Clock
Clock Cycle Time
tKHKH
2.50
ns
Clock High Pulse Width
tKHKL
1.15
1.25
1.40
ns
Clock Low Pulse Width
tKLKH
1.15
1.25
1.40
ns
Address Setup Time
tAVKH
0.30
0.33
0.35
ns
Control(B1,B2,B3) Setup Time
tBVKH
0.30
0.33
0.35
ns
Data Setup Time
tDVKX
0.20
0.25
0.30
ns
Address Hold Time
tKHAX
0.30
0.33
0.35
ns
Control(B1,B2,B3) Hold Time
tKHBX
0.30
0.33
0.35
ns
Data Hold Time
tKXDX
0.20
0.25
0.30
ns
2
tCHCL
tKHKL-0.1
tKHKL+0.1
tKHKL-0.1
tKHKL+0.1
tKHKL-0.1
tKHKL+0.1
ns
2
Echo Clock Low Pulse Width
tCLCH
tKLKH-0.1
tKLKH+0.1
tKLKH-0.1
tKLKH+0.1
tKLKH-0.1
tKLKH+0.1
ns
2
Clock Crossing to Echo Clock
tCXCH
1.0
2.5
1.0
2.5
1.0
2.5
ns
3
Clock Crossing to Echo Clock
tCXCL
1.0
2.5
1.0
2.5
1.0
2.5
ns
3
Echo Clock High to Output Vaild
tCHQV
0.20
0.20
0.20
ns
Echo Clock Low to Output Valid
tCLQV
0.20
0.20
0.20
ns
Echo Clock High to Output Hold
tCHQX
-0.20
-0.20
-0.20
ns
Echo Clock Low to Output Hold
tCLQX
-0.20
-0.20
-0.20
ns
Echo Clock High to Output High-Z
tCHQZ
Echo Clock High to Output Low-Z
tCHLZ
1
Setup Times
2
Hold Times
Output Times
Echo Clock High Pulse Width
0.20
-0.20
0.20
-0.20
0.20
-0.20
ns
ns
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 32Mb density
5. K and K Clocks must be used differencitally to meet AC timing specifications.
- 13
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
NOP
1
READ
READ
READ
CONTINUE READ
CONTINUE READ
NOP
(burst of 4)
(burst of 4)
(burst of 2)
2
5
4
3
NOP
7
6
8
WRITE
WRITE
(burst of 4)
9
READ
CONTINUE READ
(burst of 4)
10
CONTINUE
12
11
K
tKHKH
K
B1
B2
tBVKH
tKHBX
B3
SA
A5
A0
tAVKH
A2
A1
A3
tKHAX
tKHDX
tDVKH
DQ
Q01
QX2
tKXCH tCHQV
tCHQZ
Q02
Q03
Q04
tCHQX
Q51
tCLQV
Q52
Q53
Q54
tCLQX
Q11
Q12
D21
D22
D23
D24
Q31
tKXCL
tCHCL tCLCH
tCHLZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
- 14
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
NOP
READ
(burst of 4)
1
READ
CONTINUE
2
3
READ
READ
CONTINUE CONTINUE
4
5
READ
NOP
(burst of 1)
6
7
NOP
8
WRITE
WRITE
(burst of 2)
9
READ
CONTINUE READ
CONTINUE
(burst of 2)
10
11
12
K
tKHKH
tKHKL tKLKH
K
B1
B2
tBVKH
tKHBX
B3
tAVKH
A2
A1
A0
SA
A3
tDVKH
tKHAX
tKHDX
DQ
Q01
QX1
Q02
Q03
Q04
Q11
D21
D22
Q31
tKXCH
tCHQV
tCHQZ
tCHLZ
tKXCL
tCHQX
tCHCLtCLCH
CQ
CQ
DON’T CARE
UNDEFINED
NOTE :
1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
- 15
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left
unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
SRAM
CORE
SA
SA
TDI
BYPASS Reg.
Notes
0
0
0
EXTEST
Boundary Scan Register
1
0
0
1
IDCODE
Identification Register
2
0
1
0
SAMPLE-Z Boundary Scan Register
0
1
1
PRIVATE3
Bypass Register
1
0
0
SAMPLE
Boundary Scan Register
1
0
1
PRIVATE2
Bypass Register
3,5
1
1
0
PRIVATE1
Bypass Register
3,5
1
1
1
BYPASS
Bypass Register
3
1
3,5
4
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. Input terminators are switched off.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked.
The Bypass Register also holds serially loaded TDI when exiting the
Shift DR states.
4. SAMPLE instruction dose not places DQs in Hi-Z.
5. PRIVATE1 and PRIVATE2 are reserved for the exclusive use of SAMSUNG. This instruction should not be used.
TDO
Identification Reg.
Instruction Reg.
Control Signals
TMS
TCK
TDO Output
TAP Controller
TAP Controller State Diagram
1
Test Logic Reset
0
0
Run Test Idle
1
Select DR
1
Select IR
0
1
0
1
Capture DR
0
0
1
Pause DR
1
Exit2 DR
1
Update DR
0
- 16
Shift IR
1
Exit1 DR
0
1
Capture IR
0
Shift DR
1
1
0
1
Exit1 IR
0
0
0
Pause IR
1
Exit2 IR
1
Update IR
0
0
0
1
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
1
5P
VDD(2)
38
5C
SA
1
5P
VDD(2)
28
5C
2
5R
SA1
39
4A
SA
2
5R
SA1
29
4A
SA
3
5T
SA0
40
4C
SA
3
5T
SA0
30
4C
SA
4
6R
SA
41
4D
VSS(2
4
6R
SA
31
4D
VSS(2)
5
7T
SA
42
3A
SA
5
7T
SA
32
3A
SA
6
7R
VDD(2)
43
3B
SA
6
7R
VDD(2)
33
3B
SA
7
7P
SA
44
3C
SA
7
7P
SA
34
3C
SA
8
8T
DQ1
45
3D
SA
8
8T
DQ1
35
3D
SA
9
9T
DQ2
46
2B
DQ19
36
2B
DQ10
10
8P
DQ10
47
1B
DQ20
11
7M
DQ0
48
2D
DQ28
12
9P
DQ12
49
3F
DQ18
9
9P
DQ2
13
8M
CQ(3)
50
1D
DQ30
10
8M
CQ(3)
37
1D
DQ11
14
9M
DQ3
51
2F
CQ(3)
38
2F
CQ(3)
39
3H
DQ9
15
7K
DQ9
52
1F
DQ21
16
8K
DQ11
53
3H
DQ27
17
9K
DQ13
54
2H
18
6L
MODE
55
19
5H
K
56
20
5G
K
21
9H
DQ4
22
8H
23
24
SA
11
7K
DQ0
DQ29
12
9K
DQ3
1H
DQ31
13
6L
MODE
40
1H
DQ12
5A
ZQ(1)
14
5H
K
41
5A
ZQ(1)
57
5B
B1
15
5G
K
42
5B
B1
58
5K
B2
43
5K
B2
DQ6
59
5L
B3
44
5L
B3
7H
DQ8
60
4L
LBO
45
4L
LBO
9F
DQ14
61
1K
DQ22
25
8F
CQ(3)
62
2K
DQ24
46
2K
DQ15
26
9D
DQ5
63
3K
DQ26
27
7F
DQ17
64
1M
DQ32
18
7F
DQ8
47
1M
DQ13
28
8D
DQ7
65
2M
CQ(3)
19
8D
DQ7
20
9B
DQ5
16
8H
DQ6
17
9F
DQ4
29
9B
DQ15
66
1P
DQ23
30
8B
DQ16
67
3M
DQ35
48
3M
DQ17
31
7D
SA
68
2P
DQ25
21
7D
SA
49
2P
DQ16
32
7C
SA
69
1T
DQ33
22
7C
SA
50
1T
DQ14
33
7B
SA
70
2T
DQ34
23
7B
SA
51
3P
SA
34
7A
SA
71
3R
VDD(2)
24
7A
SA
52
3R
VDD(2)
35
6D
VSS(2)
72
3T
SA
25
6D
VSS(2)
53
3T
SA
36
6C
SA
73
4R
SA
26
6C
SA
54
4R
SA
37
6A
SA
74
7U
NC
27
6A
SA
55
7U
NC
* Reserved for Mode Pin
* Reserved for Mode Pin
NOTE :
1. If pin is connected as they should, TDO will be low. If pin is open, TDO will be high
2. This pin is place holder for higher density. TDO will be low for VSS and high for VDD
3. CQ and CQ are outputs during boundary scan. CQ reflects the input to K and CQ outputs the inverted value of K. It is prohibited to force CQ and CQ.
And TDO is ’X’.(Don’t Care)
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
Boundary Scan
1M x 36
3 bits
1 bits
32 bits
74 bits
2M x 18
3 bits
1 bits
32 bits
55 bits
- 17
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
ID REGISTER DEFINITION
Part
Revision Number
(31:28)
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit
(0)
1M x 36
0000
01000 00100
XXXXXX
00001001110
1
2M x 18
0000
01001 00011
XXXXXX
00001001110
1
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
1.7
2.5
2.6
V
Input High Level
VIH
0.65*VDD
-
VDD+0.3
V
Input Low Level
VIL
-0.3
-
0.35*VDD
V
Output High Voltage(IOH=-2mA)
VOH
0.75*VDD
-
VDD
V
Output Low Voltage(IOL=2mA)
VOL
VSS
-
0.25*VDD
V
Note
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Symbol
Min
Unit
Input High/Low Level
Parameter
VIH/VIL
VDD/0.0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
VDD/2
V
Input and Output Timing Reference Level
Note
1
NOTE : 1. See SRAM AC test output load on page 5.
JTAG AC Characteristics
Symbol
Min
Max
Unit
TCK Cycle Time
Parameter
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
Note
JTAG TIMING DIAGRAM
TCK
tCHCH
TMS
tCHCL
tMVCH
tCHMX
tDVCH
tCHDX
tCLCH
TDI
tCLQV
TDO
- 18
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
PACKAGE DIMENSIONS
153-FCBGA-14.00x22.00 LID
UNDERFILL
1.27x16=20.320
20.000
22.000
12.000
14.000
0.750 MIN
0.750 MIN
1.270 BSC
0.150 MAX
#A1 INDEX
B
153-∅0.760±0.150
BOTTOM VIEW
2.750
0.600
UNDERFILL
0.200
TOP VIEW
1.200
A
A BCDE FGH J K LMNPR T U
(Datum B)
10.160
(Datum A)
1.270 BSC
7.000
14.000
1.27x8=10.160
5.080
9 8 7 6 5 4 3 2 1
22.000
∅0.300 MAX M
METAL LID
11.000
#A1
Units:millimeters/Inches
153 BGA PACKAGE THERMAL CHARACTERISTICS
Symbol
Thermal Resistance
Unit
Junction to Case
Parameter
θJC
0.9
°C/W
Junction to Board
θJB
6.9
°C/W
Junction to Ambient(at air flow of 1m/sec)
θJA
16.1
°C/W
Junction to Ambient(at still air)
θJA
19.5
°C/W
Note
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x θJA or TJ = TC + PD x θJC
2. Strongly recommends using a heat sink because it greatly improves the ambient temperature requirement
- 19
Rev 1.4
Oct. 2005
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