Maxim DS1805E-100 Addressable digital potentiometer Datasheet

XX-XXXX; Rev 0; 4/02
Addressable Digital Potentiometer
The DS1805 addressable digital potentiometer contains
a single 256-position digitally controlled potentiometer.
Device control is achieved through a 2-wire serial interface. Device addressing is provided through three
address inputs that allow up to eight devices on a single 2-wire bus. The exact wiper position of the potentiometer can be written or read. The DS1805 is
available in 16-pin SO and 14-pin TSSOP packages.
The device is available in three standard resistance values: 10kΩ, 50kΩ, and 100kΩ. The DS1805 is specified
over the industrial temperature range. The DS1805
provides a low-cost alternative for designs based on
the DS1803, but require only a single potentiometer.
Applications
CCFL Inverters
Features
♦ 3V or 5V Operation
♦ Low Power Consumption
♦ One Digitally Controlled, 256-Position
Potentiometer
♦ Compatible with DS1803-Based Designs
♦ 14-Pin TSSOP (173mil) and 16-Pin SO (150mil)
Available for Surface-Mount Applications
♦ Three Address Inputs
♦ Serial 2-Wire Bus
♦ Operating Temperature Range
Industrial: -40°C to +85°C
♦ Standard Resistance Values
PDAs and Cell Phones
DS1805-010: 10kΩ
Portable Electronics
DS1805-050*: 50kΩ
Multimedia Products
DS1805-100*: 100kΩ
Instrumentation and Industrial Controls
Ordering Information
Pin Configurations
TOP VIEW
PART
TEMP RANGE
PIN-PACKAGE
RESISTANCE
(KΩ)
10
DS1805E-010
-40°C to +85°C
14 TSSOP (173mil)
H1 1
14 VCC
H1 1
16 VCC
DS1805E-050*
-40°C to +85°C
14 TSSOP (173mil)
50
L1
2
13 N.C.
N.C. 2
15 N.C.
DS1805E-100*
-40°C to +85°C
14 TSSOP (173mil)
100
W1
3
12 N.C.
L1 3
14 N.C.
DS1805Z-010
-40°C to +85°C
16 SO (150mil)
10
11 N.C.
W1 4
13 N.C.
DS1805Z-050*
-40°C to +85°C
16 SO (150mil)
50
10 N.C.
A2 5
12 N.C.
DS1805Z-100*
-40°C to +85°C
16 SO (150mil)
100
A0 6
9
SDA
A1 6
11 N.C.
Add “/T&R” for tape-and-reel orders.
GND 7
8
SCL
A0 7
10 SDA
*Future product.
A2 4
A1 5
DS1805E
DS1805Z
GND 8
9
SCL
14 TSSOP (173mil)
16 SO (150mil)
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS1805
General Description
DS1805
Addressable Digital Potentiometer
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature............................................See IPC/JEDEC
J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER
CONDITIONS
SYMBOL
MAX
UNITS
Supply Voltage
VCC
(Note 1)
MIN
2.7
TYP
5.5
V
Resistor Inputs
L, H, W
(Note 1)
-0.3
VCC +
0.3
V
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
Supply Current Active
ICC
Input Leakage
IIL
Wiper Resistance
RW
Wiper Current
IW
Input Logic 1
VIH
Input Logic 0
VIL
CONDITIONS
-1
µA
+1
µA
1000
Ω
1
mA
0.7VCC
VCC +
0.3
V
GND 0.3
0.3VCC
V
Input logic 1
0.7VCC
VCC +
0.3
Input logic 0
GND 0.3
0.25VCC
400
0.4V < VI/O < 0.9VCC
-10
µA
(Note 5)
40
µA
VOL1
3mA sink current
0
0.4
V
VOL2
6mA sink current
0
0.6
V
10
pF
50
ns
CI/0
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
tSP
Fast mode
_____________________________________________________________________
20
+10
ISTBY
I/O Capacitance
2
200
V
Input Current each I/O Pin
(Note 4)
Low-Level Output Voltage
TYP
(Note 2)
Input Logic Levels A0, A1, A2
(Note 3)
Standby Current
MIN
0
Addressable Digital Potentiometer
(VCC = 2.7V to 5.5V, TA = -40°C to +85°C)
SYMBOL
PARAMETER
MAX
UNITS
(Note 6)
-20
+20
%
Absolute Linearity
(Note 7)
-0.75
+0.75
LSB
Relative Linearity
(Note 8)
-0.3
+0.3
LSB
End-to-End Resistor Tolerance
fCUTOFF
-3dB Cutoff Frequency
CONDITIONS
MIN
TYP
(Note 9)
Hz
Ratiometric Temperature Coefficient
End-to-End Temperature Coefficient
8
ppm/°C
550
ppm/°C
CI
Capacitance
5
pF
MAX
400
UNITS
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = -40°C to +85°C)
PARAMETER
SYMBOL
SCL Clock Frequency (Note 10)
fSCL
Bus Free Time Between STOP
and START Condition (Note 10)
tBUF
Hold Time (Repeated) START
Condition (Notes 10, 11)
tHD:STA
Low Period of SCL Clock
(Note 10)
tLOW
High Period of SCL Clock
(Note 10)
tHIGH
Data Hold Time
(Notes 10, 12, 13)
tHD:DAT
Data Setup Time
(Note 10)
tSU:DAT
Rise Time of Both SDA and SCL
Signals (Notes 10, 14)
tR
Fall Time of Both SDA and SCL
Signals (Notes 10, 14)
tF
Setup Time for STOP Condition
(Note 10)
tSU:STO
Capacitive Load for Each Bus
Line (Note 14)
CB
CONDITIONS
Fast mode
Standard mode
MIN
0
0
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
Fast mode
1.3
Standard mode
4.7
Fast mode
0.6
Standard mode
4.0
TYP
100
µs
µs
µs
µs
Fast mode
0
0.9
Standard mode
0
0.9
Fast mode
100
Standard mode
250
kHz
µs
ns
Fast mode
20 + 0.1CB
300
Standard mode
20 + 0.1CB
1000
Fast mode
20 + 0.1CB
300
Standard mode
20 + 0.1CB
300
Fast mode
Standard mode
0.6
4.0
ns
ns
µs
400
pF
_____________________________________________________________________
3
DS1805
ANALOG RESISTOR CHARACTERISTICS
DS1805
Addressable Digital Potentiometer
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = -40°C to +85°C)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
4
All voltages are referenced to ground.
ICC specified with SDA pin open. SCL = 400kHz clock rate.
Address inputs A0, A1, and A2 should be connected to either VCC or GND, depending on the desired address selections.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
ISTBY specified with SDA = SCL = VCC = 5.0V.
Valid at +25°C only.
Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position.
Relative linearity is used to determine the change in voltage between successive tap positions.
-3dB cutoff frequency characteristics for the DS1805 depend on potentiometer total resistance: DS1805-010, 1MHz;
DS1805-50, 200kHz; DS1805-100, 100kHz.
A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This
will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns =
1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
CB—total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
_____________________________________________________________________
Addressable Digital Potentiometer
W-L RESISTANCE
vs. WIPER SETTING
VCC = 3V
15
10
8
6
10kΩ POTENTIOMETER
4
2
5
0
40
60
80
0
WIPER = BFh
0
WIPER = BFh
TC = 8.1ppm/°C
TC = 1.3ppm/°C
0
DS1805 toc05
45
10kΩ, WORST CASE
0
-1
-2
TC = 530ppm/°C
20
40
60
5
35
30
25
20
15
SDA = VCC
A0, A1, A2, L1 = GND
W1, H1 = NO CONNECT
10
0
-40
80
40
5
-5
-20
0
20
40
0
80
60
100
TEMPERATURE (°C)
TEMPERATURE (°C)
VOLTAGE-DIVIDER ABSOLUTE LINEARITY
vs. WIPER SETTING (10kΩ)
0.18
0.16
0.14
0.12
0.10
0.08
0.06
200
300
400
SCL FREQUENCY (kHz)
VOLTAGE-DIVIDER RELATIVE LINEARITY
vs. WIPER SETTING (10kΩ)
0.06
0.05
RELATIVE LINEARITY (LSB)
-20
4
50
2
DS1805 toc07
-40
3
-3
3
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
-4
WIPER = 3Fh
-0.06
4
1
2
WIPER VOLTAGE (V)
5
END-TO-END RESISTANCE % CHANGE
DS1805 toc04
WIPER = 7Fh
ABSOLUTE LINEARITY (LSB)
% CHANGE (FROM +25°C)
0.04
-0.04
1
END-TO-END RESISTANCE TEMPERATURE
CHANGE vs. TEMPERATURE
WIPER = 3Fh
-0.02
0
WIPER SETTING
VOLTAGE DIVIDER PERCENT CHANGE
(FROM +25°C) vs. TEMPERATURE
(RATIOMETRIC TC)
0.02
100
0 25 50 75 100 125 150 175 200 225 250
TEMPERATURE (°C)
10kΩ POT
150
DS1805 toc06
20
VCC = 3V
200
DS1805 toc08
0
ACTIVE SUPPLY CURRENT (µA)
-20
250
50
0
-40
0.06
VCC = 5V
300
WIPER RESISTANCE (Ω)
20
350
DS1805 toc02
10
W-L RESISTANCE (kΩ)
VCC = 5V
25
SUPPLY CURRENT (µA)
DS1805 toc01
30
WIPER RESISTANCE vs.
WIPER VOLTAGE (10kΩ)
DS1805 toc03
SUPPLY CURRENT
vs. TEMPERATURE
0.04
0.03
0.02
0.01
0.04
0
0.02
0
-0.01
0
50
100
150
WIPER SETTING
200
250
0
50
100
150
200
250
WIPER SETTING
_____________________________________________________________________
5
DS1805
Typical Operating Characteristics
(VCC = 5.0V, TA = +25°C, unless otherwise noted.)
DS1805
Addressable Digital Potentiometer
L1
POTENTIOMETER-1
H1
256-TO-1 MULTIPLEXER
SRAM
REG-0 (8-BIT REGISTER)
WIPER-1 (8-BIT REGISTER)
W1
SCL
COMMAND/
CONTROL
UNIT
SDA
2-WIRE SERIAL
INTERFACE
A0
DEVICE ADDRESS
SELECTION
A1
A2
Figure 1. Functional Diagram
Detailed Description
Pin Description
PIN
6
NAME
TSSOP
SO
1
1
H1
2
3
L1
3
4
W1
6, 5, 4
7
8
9
10–13
7, 6, 5
8
9
10
2, 11–15
A0, A1, A2
GND
SCL
SDA
N.C.
14
16
VCC
FUNCTION
High End of
Potentiometer
Low End of
Potentiometer
Wiper Terminal of
Potentiometer
Address Select Inputs
Ground
Serial Clock Input
Serial Data I/O
No Connection
3V/5V Power-Supply
Input
The DS1805 addressable digital potentiometer contains a
single 256-position digitally controlled potentiometer.
Device control is achieved through a 2-wire serial interface. Device addressing is provided through three
address inputs that allow up to eight devices on a single
2-wire bus. The exact wiper position of the potentiometer
can be written or read. The DS1805 is available in 16-pin
SO and 14-pin TSSOP packages. The device is available
in three standard resistance values: 10kΩ, 50kΩ, and
100kΩ. The DS1805 specified over the industrial temperature range. The DS1805 is provides a low-cost alternative for designs based on the DS1803, but require only a
single potentiometer.
Device Operation
The DS1805 is an addressable, digitally controlled
device that has a single 256-position potentiometer.
Figure 1 shows a block diagram of the part.
Communication and control of the device is accomplished through a 2-wire serial interface that has SDA
and SDL signals. Device addressing is attained using
the device chip-select inputs A0, A1, and A2.
_____________________________________________________________________
Addressable Digital Potentiometer
DS1805
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
ACK
START
CONDITION
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERED
STOP
CONDITION
OR REPEATED
START
CONDITION
Figure 2. 2-Wire Data Transfer Overview
The potentiometer is composed of a 256-position resistor array. Two 8-bit registers are provided to ensure
compatibility with DS1803-based designs. Register-0 is
a general-purpose SRAM byte, while register-1 is
assigned to the potentiometer and is used to set the
wiper position on the resistor array. The wiper terminal
is multiplexed to one of 256 positions on the resistor array
based on its corresponding 8-bit register value. The highest wiper setting, FFh, is 1 LSB away from H1 (resistor
255), while the lowest setting, 00h, connects to L1.
The DS1805 is a volatile device that does not maintain
the position of the wiper during power-down or loss of
power. On power-up, the wiper position is set to 00h
(the low-end terminal). The user can then set the wiper
value to a desired position.
Communication with the DS1805 takes place over the
2-wire serial interface consisting of the bidirectional
data terminal, SDA, and the serial clock input, SCL.
Complete details of the 2-wire interface are discussed
in the 2-Wire Serial Data Bus section.
The 2-wire interface and address inputs A0, A1, and A2
allow operation of up to eight devices in a bus topology,
with A0, A1, and A2 being the address of the device.
Application Considerations
The DS1805 is offered in three standard resistor values:
10kΩ, 50kΩ, and 100kΩ. The resolution of the potentiometer is defined as RTOT/256, where RTOT is the total
resistor value of the potentiometer. The DS1805 is
designed to operate using 3V or 5V power supplies over
the industrial (-40°C to +85°C) temperature range.
Maximum input signal levels across the potentiometer
cannot exceed the operating power supply of the device.
2-Wire Serial Data Bus
The DS1805 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data on
the bus is called a transmitter, and a device receiving
data is called a receiver. The device that controls the
message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial
clock (SCL), controls the bus access, and generates the
START and STOP conditions. The DS1805 operates as
a slave on the 2-wire bus. Connections to the bus are
made through the open-drain I/O lines, SDA and SCL.
The following bus protocol has been defined (Figure 2):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data
line from high to low while the clock is high defines a
START condition.
_____________________________________________________________________
7
Within the bus specifications a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1805 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the reception of each byte. The master device must generate an
extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate the STOP condition.
Data transfer from a master transmitter to a slave
receiver: The first byte transmitted by the master is the
control byte (slave address). Next follows a number of
data bytes. The slave returns an acknowledge bit after
each received byte.
Data transfer from a slave transmitter to a master
receiver: The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received
byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer
8
MSB
DEVICE
IDENTIFIER
0
1
A2
A1
DEVICE
ADDRESS
A0
R/W
IT
1
RIT
EB
0
LSB
D/W
Stop data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is stable for the duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data. Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of
the R/W bit, two types of data transfer are possible.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP conditions is not limited and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
REA
DS1805
Addressable Digital Potentiometer
Figure 3. Control Byte
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus
will not be released.
The DS1805 can operate in the following two modes:
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed
by hardware after reception of the slave address and
direction bit.
Slave transmitter mode: The first byte is received and
handled as in the slave receiver mode. However, in this
mode the direction bit will indicate that the transfer
direction is reversed. Serial data is transmitted on SDA
by the DS1805 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Slave Address
A control byte is the first byte received following the
START condition from the master device. The control
byte consists of a four-bit control code; for the DS1805,
this is set as 0101 binary for read/write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of eight devices are to be accessed.
The select bits are the three least significant bits (LSB)
of the slave address. Additionally, A2, A1, and A0 can
be changed any time during a powered condition of the
part. The last bit of the control byte (R/W) defines the
operation to be performed. When set to a one, a read
operation is selected; when set to a zero a write operation is selected. Figure 3 shows the control byte structure for the DS1805.
_____________________________________________________________________
Addressable Digital Potentiometer
Command and Protocol
The DS1805’s command and protocol structure of the
DS1805 allows the user to read or write to both the
scratchpad and potentiometer registers. Figures 4 and
5 show the command structures for the part.
Potentiometer data values and control and command
values are always transmitted most significant bit
(MSB) first. During communications, the receiving unit
always generates the acknowledge.
Reading the DS1805
As shown in Figure 4, the DS1805 provides one readcommand operation. This operation allows the user to
read both potentiometers. Specifically, the R/W bit of the
control byte is set equal to a one for a read operation.
Communication to read the DS1805 begins with a START
condition that is issued by the master device. The control
byte from the master device follows the START condition.
Once the control byte has been received by the DS1805,
the part responds with an acknowledge. The read/write
bit of the control byte as stated should be set equal to
one for reading the DS1805.
When the master has received the acknowledge from the
DS1805, the master can then begin to receive potentiometer wiper data. The value of the register-0 wiper
position will be the first returned from the DS1805. Once
the eight bits of the register-0 wiper position have been
transmitted, the master needs to issue an acknowledge,
unless it is the only byte to be read, in which case the
master issues a not acknowledge. If desired, the master
can stop the communication transfer at this point by issuing the STOP condition. However, if the value of the
potentiometer-1 wiper position value is needed, commu-
Table 1. 2-Wire Command Words
COMMAND
COMMAND VALUE
Write Register-0
101010 01
Write Potentiometer-1 Register
101010 10
Write Both Registers
101011 11
nication transfer can continue by clocking the remaining
eight bits of the potentiometer-1 value, followed by a not
acknowledge. Final communication transfer is terminated
by issuing the STOP command. Figure 4 shows the flow
of the read operation.
Writing to the DS1805
Figure 5 shows a data flow diagram for writing the
DS1805. The DS1805 has three write-command operations. These include write reg-0, write pot-1, and write
reg-0/pot-1. The write reg-0 command allows the user to
write the value of scratchpad register-0 and as an option
the value of potentiometer-1. The write-1 command allows
the user to write the value of potentiometer-1 only. The
last write command, write-0/1, allows the user to write
both registers to the same value with one command and
one data value being issued.
All the write operations begin with a START condition.
Following the START condition, the master device issues
the control byte. The read/write bit of the control byte is
set to zero for writing the DS1805. Once the control byte
has been issued and the master receives the acknowledgment from the DS1805, the command byte is transmitted to the DS1805. As mentioned above, there exist
three write operations that can be used with the DS1805.
Figure 5 and Table 1 show the binary value of each write
command.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
OPTIONAL
DATA
BYTE
0
1
A2
A1
A0
1
LSB
REG-0
MSB
LSB
POT-1
STOP
1
MSB
ACK
0
LSB
ACK
START
MSB
DATA
BYTE
ACK
CONTROL
BYTE
R/W = 1
Figure 4. 2-Wire Read Protocols
_____________________________________________________________________
9
DS1805
Following the START condition, the DS1805 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving the 0101 address code
and appropriate device select bits, the slave device
outputs an acknowledge signal on the SDA line.
OPTIONAL
REGISTER-0
0
1
A2
A1
A0
0
1
0
1
0
1
DATA
BYTE
0
0
1
MSB
MSB
LSB
REG-0
LSB
POT-1
STOP
1
LSB
ACK
START
0
MSB
ACK
LSB
MSB
DATA
BYTE
ACK
COMMAND
BYTE
ACK
CONTROL
BYTE
R/W = 0
WRITE POT-1
A2
A1
A0
0
1
0
1
0
1
0
1
0
LSB
POT-1
STOP
1
MSB
STOP
0
LSB
ACK
1
ACK
START
0
DATA
BYTE
MSB
ACK
COMMAND
BYTE
LSB
ACK
CONTROL
BYTE
MSB
R/W = 0
WRITE REGISTER-0 AND POT-1 (SAME VALUE)
CONTROL
BYTE
COMMAND
BYTE
1
0
1
A2
A1
A0
0
1
LSB
0
1
0
1
1
1
1
MSB
ACK
0
DATA
BYTE
MSB
ACK
LSB
MSB
START
DS1805
Addressable Digital Potentiometer
LSB
REG-0/POT-1 VALUE
R/W = 0
Figure 5. 2-Wire Write Protocols
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tSU:STO
tHD:DAT
Figure 6. Timing Diagram
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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