Cypress CY7C1373D-133BGC 18-mbit (512k x 36/1m x 18) flow-through sram with nobltm architecture Datasheet

PRELIMINARY
CY7C1371D
CY7C1373D
18-Mbit (512K x 36/1M x 18) Flow-Through
SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency (NoBL) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100 TQFP, 119-ball
BGA and 165-ball fBGA packages
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x
18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371D/
CY7C1373D is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
210
175
mA
Maximum CMOS Standby Current
70
70
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05556 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 3, 2004
PRELIMINARY
CY7C1371D
CY7C1373D
1
Logic Block Diagram – CY7C1371D (512K x 36)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
BWC
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BWD
WE
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
INPUT
E
REGISTER
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1373D (1 Mbit x 18)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document #: 38-05556 Rev. *A
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Configurations
Document #: 38-05556 Rev. *A
A
40
41
42
43
44
45
46
47
48
49
50
VDD
NC / 72M
NC / 36M
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC / 144M
34
A
38
33
A
NC / 288M
32
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
CEN
VSS
90
WE
VDD
91
88
CE3
92
CLK
BWA
93
89
BWC
BWB
BWD
96
94
CE2
97
95
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1371D
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
100-lead TQFP
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 3 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Configurations (continued)
Document #: 38-05556 Rev. *A
A
40
41
42
43
44
45
46
47
48
49
50
VDD
NC / 72M
NC / 36M
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC / 144M
34
A
38
33
A
NC / 288M
32
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
90
CEN
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
NC
BWB
95
NC
CE2
97
96
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1373D
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
100-lead TQFP
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 4 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Configurations (continued)
119-ball BGA (3 Chip Enables with JTAG)
1
CY7C1371D (512K x 36)
3
4
5
A
A
A
A
VDDQ
2
A
B
C
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
OE
A
WE
VDD
CLK
NC
6
A
7
VDDQ
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
CEN
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC / 72M
TMS
A
TDI
A
TCK
A
TDO
NC / 36M
NC
ZZ
VDDQ
3
4
5
6
7
A
A
A
A
VDDQ
ADV/LD
VDD
A
CE3
A
NC
A
CY7C1373D (1 Mbit x 18)
1
2
A
VDDQ
A
B
NC
CE2
A
C
NC
A
A
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
OE
A
VSS
DQA
VDDQ
NC
DQA
VDD
DQA
NC
VDDQ
NC
F
VDDQ
NC
VSS
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
WE
VDD
NC
VSS
NC
K
NC
DQB
VSS
CLK
VSS
NC
DQA
L
M
DQB
VDDQ
NC
DQB
NC
VSS
NC
BWA
VSS
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
CEN
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC / 72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC / 36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05556 Rev. *A
Page 5 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Configurations (continued)
165-ball fBGA (3 Chip enable with JTAG)
CY7C1371D (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
CE1
BWC
BWB
CE3
CEN
ADV/LD
A
A
NC
R
NC
A
CE2
BWD
BWA
CLK
WE
OE
A
A
NC / 144M
DQPC
DQC
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
CY7C1373D (1 Mbit x 18)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
1
A
CE1
BWB
NC
CE3
CEN
ADV/LD
A
A
A
NC
A
CE2
NC
BWA
CLK
WE
OE
A
A
NC / 144M
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
NC / 72M
A
A
R
MODE
NC / 36M
A
A
Document #: 38-05556 Rev. *A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
TDI
NC
A1
TDO
A
A
A
NC
TMS
A0
TCK
A
A
A
A
Page 6 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Definitions
Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
BWC, BWD
InputSynchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,
I/O pins are tri-stated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
ZZ
InputAsynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. During normal operation, this pin can
be connected to VSS or left floating.
DQs
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are
placed in a tri-state condition.The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQPX
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQs.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply
VSS
Ground
TDO
JTAG serial output
Synchronous
Document #: 38-05556 Rev. *A
Power supply for the I/O circuitry.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be left unconnected. This pin
is not available on TQFP packages.
Page 7 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Pin Definitions (continued)
I/O
Description
TDI
Name
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to VDD through
a pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAGClock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 36 Mbit, 72 Mbit, 144 Mbit and
288 Mbit are address expansion pins and are not internally connected to the die.
Functional Overview
The CY7C1371D/CY7C1373D is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay
from the clock rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Document #: 38-05556 Rev. *A
Burst Read Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BWX signals. The CY7C1371D/CY7C1373D provides byte
write capability that is described in the truth table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs.
Page 8 of 30
PRELIMINARY
Doing so will tri-state the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Linear Burst Address Table (MODE = GND)
Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the
burst write, in order to write the correct bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
CY7C1371D
CY7C1373D
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
Min.
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Max.
Unit
80
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Truth Table [ 2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Address
Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX
None
H
X
X
L
L
X
X
Deselect Cycle
None
X
X
H
L
Deselect Cycle
None
Continue Deselect Cycle
None
X
L
X
X
X
X
Read Cycle (Begin Burst)
External
L
H
Next
X
X
NOP/Dummy Read (Begin Burst) External
L
H
L
Dummy Read (Continue Burst)
X
X
X
Read Cycle (Continue Burst)
Next
OE
CEN
CLK
DQ
X
L
L->H
Tri-State
L
X
X
X
L
L->H
Tri-State
L
L
X
X
X
L
L->H
Tri-State
L
H
X
X
X
L
L->H
Tri-State
L
L
L
H
X
L
L
L->H Data Out (Q)
X
L
H
X
X
L
L
L->H Data Out (Q)
L
L
H
X
H
L
L->H
Tri-State
L
H
X
X
H
L
L->H
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05556 Rev. *A
Page 9 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Truth Table (continued)[ 2, 3, 4, 5, 6, 7, 8]
Address
Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX
Operation
OE
CEN
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Cycle (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
CLK
DQ
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1371D)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
L
H
H
H
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Partial Truth Table for Read/Write[2, 3,9]
Function (CY7C1373D)
WE
BWA
BWB
Read
H
X
X
Write - No bytes written
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
H
H
L
H
H
Write All Bytes
L
L
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371D/CY7C1373D incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The
TAPoperates using JEDEC-standard 3.3V or 2.5V I/O logic
levels.
The CY7C1371D/CY7C1373D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document #: 38-05556 Rev. *A
Page 10 of 30
PRELIMINARY
TAP Controller State Diagram
1
CY7C1371D
CY7C1373D
TAP Controller Block Diagram
TEST-LOGIC
RESET
0
Bypass Register
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
2 1 0
0
1
CAPTURE-DR
TDI
CAPTURE-IR
0
Selection
Circuitry
31 30 29 . . . 2 1 0
0
SHIFT-DR
0
Instruction Register
Selection
Circuitry
TDO
Identification Register
SHIFT-IR
0
x . . . . . 2 1 0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
0
1
EXIT2-DR
0
TCK
TMS
TAP CONTROLLER
EXIT2-IR
1
1
UPDATE-DR
1
Boundary Scan Register
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see figure. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
Document #: 38-05556 Rev. *A
Page 11 of 30
PRELIMINARY
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
CY7C1371D
CY7C1373D
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
IDCODE
Reserved
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
Document #: 38-05556 Rev. *A
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
TAP AC Switching Characteristics Over the Operating
Parameter
UNDEFINED
Range[10, 11]
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
25
ns
tTL
TCK Clock LOW time
25
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
5
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
tTMSH
TMS hold after TCK Clock Rise
5
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
ns
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05556 Rev. *A
Page 13 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall times ................................................... 1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels........................................ .1.25V
Output reference levels...................................................1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
Description
Description
Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –4.0 mA
VDDQ = 3.3V
2.4
V
IOH = –1.0 mA
VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
VIL
Input LOW Voltage
VDDQ = 2.5V
IX
Input Load Current
VDDQ = 2.5V
GND < VIN < VDDQ
V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.5
0.7
V
–0.3
0.7
V
–5
5
µA
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05556 Rev. *A
Page 14 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Identification Register Definitions
Instruction Field
Revision Number (31:29)
CY7C1371D
(512KX36)
CY7C1373D
(1 MbitX18)
000
000
Device Depth (28:24)
01011
01011
Device Width (23:18)
001001
001001
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
100101
010101
00000110100
00000110100
1
1
ID Register Presence Indicator (0)
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball fBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05556 Rev. *A
Page 15 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
119-ball BGA Boundary Scan[13, 14]
CY7C1371D (1 Mbit x 36)
Bit #
Ball ID
Bit #
1
H4
37
2
T4
38
3
T5
39
4
T6
5
6
CY7C1371D (1 Mbit x 36)
Ball ID
Bit #
Ball ID
B6
73
N2
D4
74
P2
B4
75
R3
40
F4
76
T1
R5
41
M4
77
R1
L5
42
A5
78
T2
7
R6
43
K4
79
L3
8
U6
44
E4
80
R2
9
R7
45
G4
81
T3
10
T7
46
A4
82
L4
11
P6
47
G3
83
N4
12
N7
48
C3
84
P4
13
M6
49
B2
85
Internal
14
L7
50
B3
15
K6
51
A3
16
P7
52
C2
17
N6
53
A2
18
L6
54
B1
19
K7
55
C1
20
J5
56
D2
21
H6
57
E1
22
G7
58
F2
23
F6
59
G1
24
E7
60
H2
25
D7
61
D1
26
H7
62
E2
27
G6
63
G2
28
E6
64
H1
29
D6
65
J3
30
C7
66
2K
31
B7
67
L1
32
C6
68
M2
33
A6
69
N1
34
C5
70
P1
35
B5
71
K1
36
G5
72
L2
Notes:
13. Balls which are NC (No Connect) are pre-set LOW
14. Bit# 85 is pre-set HIGH
Document #: 38-05556 Rev. *A
Page 16 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
119-ball BGA Boundary Scan Order[13, 14]
CY7C1373D (2M x 18)
Bit #
Ball ID
Bit #
CY7C1373D (2M x 18)
Ball ID
Bit #
Ball ID
1
H4
37
B6
73
N2
2
T4
38
D4
74
P2
3
T5
39
B4
75
R3
4
T6
40
F4
76
T1
5
R5
41
M4
77
R1
6
L5
42
A5
78
T2
7
R6
43
K4
79
L3
8
U6
44
E4
80
R2
9
R7
45
G4
81
T3
10
T7
46
A4
82
L4
11
P6
47
G3
83
N4
12
N7
48
C3
84
P4
13
M6
49
B2
85
Internal
14
L7
50
B3
15
K6
51
A3
16
P7
52
C2
17
N6
53
A2
18
L6
54
B1
19
K7
55
C1
20
J5
56
D2
21
H6
57
E1
22
G7
58
F2
23
F6
59
G1
24
E7
60
H2
25
D7
61
D1
26
H7
62
E2
27
G6
63
G2
28
E6
64
H1
29
D6
65
J3
30
C7
66
2K
31
B7
67
L1
32
C6
68
M2
33
A6
69
N1
34
C5
70
P1
35
B5
71
K1
36
G5
72
L2
Document #: 38-05556 Rev. *A
Page 17 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
165-ball fBGA Boundary Scan Order[13, 15]
CY7C1371D (1 Mbit x 36)
Bit #
Ball ID
1
2
CY7C1371D (1 Mbit x 36)
Bit #
Ball ID
Bit #
Ball ID
N6
37
A9
73
K2
N7
38
B9
74
L2
3
10N
39
C10
75
M2
4
P11
40
A8
76
N1
5
P8
41
B8
77
N2
6
R8
42
A7
78
P1
7
R9
43
B7
79
R1
8
P9
44
B6
80
R2
9
P10
45
A6
81
P3
10
R10
46
B5
82
R3
11
R11
47
A5
83
P2
12
H11
48
A4
84
R4
13
N11
49
B4
85
P4
14
M11
50
B3
86
N5
15
L11
51
A3
87
P6
16
K11
52
A2
88
R6
89
Internal
17
J11
53
B2
18
M10
54
C2
19
L10
55
B1
20
K10
56
A1
21
J10
57
C1
22
H9
58
D1
23
H10
59
E1
24
G11
60
F1
25
F11
61
G1
26
E11
62
D2
27
D11
63
E2
28
G10
64
F2
29
F10
65
G2
30
E10
66
H1
31
D10
67
H3
32
C11
68
J1
33
A11
69
K1
34
B11
70
L1
35
A10
71
M1
36
B10
72
J2
Note:
15. Bit# 89 is Pre-set HIGH.
Document #: 38-05556 Rev. *A
Page 18 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
165-ball fBGA Boundary Scan Order[13, 15]
CY7C1373D (2M x 18)
CY7C1373D (2M x 18)
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
37
A9
73
K2
2
N7
38
B9
74
L2
3
10N
39
C10
75
M2
4
P11
40
A8
76
N1
5
P8
41
B8
77
N2
6
R8
42
A7
78
P1
7
R9
43
B7
79
R1
8
P9
44
B6
80
R2
9
P10
45
A6
81
P3
10
R10
46
B5
82
R3
11
R11
47
A5
83
P2
12
H11
48
A4
84
R4
13
N11
49
B4
85
P4
14
M11
50
B3
86
N5
15
L11
51
A3
87
P6
16
K11
52
A2
88
R6
17
J11
53
B2
89
Internal
18
M10
54
C2
19
L10
55
B1
20
K10
56
A1
21
J10
57
C1
22
H9
58
D1
23
H10
59
E1
24
G11
60
F1
25
F11
61
G1
26
E11
62
D2
27
D11
63
E2
28
G10
64
F2
29
F10
65
G2
30
E10
66
H1
31
D10
67
H3
32
C11
68
J1
33
A11
69
K1
34
B11
70
L1
35
A10
71
M1
36
B10
72
J2
Document #: 38-05556 Rev. *A
Page 19 of 30
PRELIMINARY
Maximum Ratings
CY7C1371D
CY7C1373D
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[16, 17]
Parameter
Description
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[16]
VIL
Input LOW Voltage[16]
IX
Input Load
Test Conditions
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Min.
Max.
Unit
3.135
3.135
2.375
2.4
2.0
3.6
VDD
2.625
V
V
V
V
V
V
V
V
V
V
V
µA
2.0
1.7
–0.3
–0.3
–5
30
Input = VSS
ISB1
5
µA
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
210
mA
10-ns cycle, 100 MHz
175
mA
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz
140
mA
10-ns cycle, 100 MHz
120
mA
All speeds
70
mA
130
mA
110
mA
80
mA
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
VDD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 10-ns cycle, 100 MHz
Current—CMOS Inputs f = fMAX, inputs switching
Automatic CE
VDD = Max, Device Deselected,
All Speeds
Power-down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f =
Current—TTL Inputs
0, inputs static
ISB4
µA
µA
–30
Input = VDD
IDD
µA
–5
Input = VDD
Input Current of ZZ
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
Notes:
16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05556 Rev. *A
Page 20 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Thermal Resistance[18]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TQFP
Package
BGA
Package
fBGA
Package
Unit
31
45
46
°C/W
6
7
3
°C/W
Capacitance[18]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
BGA
Package
fBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 1538Ω
VT = 1.25V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(c)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05556 Rev. *A
Page 21 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Switching Characteristics Over the Operating Range[23, 24]
133 MHz
Parameter
tPOWER
Description
[19]
Min.
Max.
1
100 MHz
Min.
Max.
Unit
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.1
2.5
ns
tCL
Clock LOW
2.1
2.5
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
2.0
2.0
ns
tCLZ
Clock to Low-Z[20, 21, 22]
2.0
2.0
ns
tCHZ
Clock to
High-Z[20, 21, 22]
tOEV
OE LOW to Output Valid
tOELZ
OE LOW to Output Low-Z[20, 21, 22]
tOEHZ
OE HIGH to Output
6.5
8.5
4.0
3.2
0
High-Z[20, 21, 22]
5.0
ns
3.8
ns
0
4.0
ns
ns
5.0
ns
Setup Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
ns
tALS
ADV/LD Set-up Before CLK Rise
1.5
1.5
ns
tWES
WE, BWX Set-up Before CLK Rise
1.5
1.5
ns
tCENS
CEN Set-up Before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold After CLK Rise
0.5
0.5
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Hold Times
Notes:
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05556 Rev. *A
Page 22 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Switching Waveforms
Read/Write Waveforms[25, 26, 27]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
3
Document #: 38-05556 Rev. *A
Page 23 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Switching Waveforms (continued)
NOP, STALL AND DESELECT Cycles[25, 26, 28]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Note:
28. The Ignore Clock Edge or Stall cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05556 Rev. *A
Page 24 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Switching Waveforms (continued)
ZZ Mode Timing[29, 30]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
4
Document #: 38-05556 Rev. *A
Page 25 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Ordering Information
Speed
(MHz)
133
Ordering Code
CY7C1371D-133AXC
Package
Name
Part and Package Type
Operating
Range
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1371D-133AXI
CY7C1373D-133AXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1371D-133BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
Industrial
CY7C1373D-133AXC
CY7C1373D-133BGC
CY7C1371D-133BGI
CY7C1373D-133BGI
CY7C1371D-133BZC
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
CY7C1373D-133BZC
CY7C1371D-133BZI
CY7C1373D-133BZI
CY7C1371D-133BGXC
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
Commercial
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
Industrial
CY7C1373D-133BGXC
CY7C1371D-133BGXI
CY7C1373D-133BGXI
CY7C1371D-133BZXC
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm)3 Chip Enables and JTAG
Commercial
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm)3 Chip Enables and JTAG
Industrial
CY7C1373D-133BZXC
CY7C1371D-133BZXI
CY7C1373D-133BZXI
100
CY7C1371D-100AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG
Industrial
CY7C1373D-100AXC
CY7C1371D-100AXI
CY7C1373D-100AXI
CY7C1371D-100BGC
CY7C1373D-100BGC
CY7C1371D-100BGI
ICY7C1373D-100BGI
CY7C1371D-100BZC
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
CY7C1373D-100BZC
CY7C1371D-100BZI
CY7C1373D-100BZI
CY7C1371D-100BGXC
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
Commercial
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables
and JTAG
Industrial
CY7C1373D-100BGXC
CY7C1371D-100BGXI
ICY7C1373D-100BGXI
CY7C1371D-100BZXC
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables and JTAG
Commercial
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x
1.4mm) 3 Chip Enables and JTAG
Industrial
CY7C1373D-100BZXC
CY7C1371D-100BZXI
CY7C1373D-100BZXI
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (Ordering Code:
BGX) will be available in 2005.
Document #: 38-05556 Rev. *A
Page 26 of 30
PRELIMINARY
CY7C1371D
CY7C1373D
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
SEE DETAIL
50
0.20 MAX.
1.60 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
GAUGE PLANE
0.10
0° MIN.
0°-7°
A
51
31
R 0.08 MIN.
0.20 MAX.
12°±1°
(8X)
SEATING PLANE
R 0.08 MIN.
0.20 MAX.
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 38-05556 Rev. *A
A
51-85050-*A
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PRELIMINARY
CY7C1371D
CY7C1373D
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05556 Rev. *A
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PRELIMINARY
CY7C1371D
CY7C1373D
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. i486 is a trademark, and Intel and Pentium
are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05556 Rev. *A
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© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1371D
CY7C1373D
Document History Page
Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05556
REV.
ECN NO.
Issue Date
Orig. of
Change
**
254513
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP , 119 BGA and 165 FBGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering Information
Document #: 38-05556 Rev. *A
Description of Change
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