Pr E2L0045-17-Y1 el im DESCRIPTION The MSM5432126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI's CMOS silicon gate process technology. The device operates with a single 5 V power supply. FEATURES • 131,072-word ¥ 32-bit organization • Single 5 V power supply, ±10% tolerance • Refresh: 512 cycles/8 ms • Fast Page Mode with Extended Data Out (EDO) • Write per bit (MSM5432128 only) • Byte write, Byte read • RAS only refresh • CAS before RAS refresh • Hidden refresh • Package: 64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K) (Product : MSM5432126-xxGS-K) (Product : MSM5432128-xxGS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time (Min.) Power Dissipation Operating (Max.) Standby (Max.) MSM5432126/8-45 45 ns 23 ns 13 ns 13 ns 100 ns 935 mW MSM5432126/8-50 50 ns 25 ns 15 ns 15 ns 110 ns 907 mW MSM5432126/8-60 60 ns 30 ns 18 ns 18 ns 130 ns 880 mW 11 mW 1/24 y 131,072-Word ¥ 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO ar This version: Jan. 1998 MSM5432126/8 Previous version: Dec. 1996 in ¡ Semiconductor MSM5432126/8 ¡ Semiconductor ¡ Semiconductor MSM5432126/8 PIN CONFIGURATION (TOP VIEW) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC NC WB* / WE RAS NC A0 A1 A2 A3 VCC 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 VSS DQ31 DQ30 DQ29 DQ28 VCC DQ27 DQ26 DQ25 DQ24 VSS DQ23 DQ22 DQ21 DQ20 VCC DQ19 DQ18 DQ17 DQ16 VSS CAS1 CAS2 CAS3 CAS4 OE A8 A7 A6 A5 A4 VSS 64-Pin Plastic SSOP Pin Name A0 - A8 DQ0 - DQ31 RAS CAS1 - CAS4 WB* / WE Note: *: Function Address Input Data Input / Data Output Row Address Strobe Column Address Strobe OE Write Per Bit* / Write Enable Output Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. MSM5432128 only 2/24 CAS1 I/O Controller CAS2 I/O Controller CAS3 I/O Controller CAS4 Column 8 Address Buffers A0 - A8 8 Internal Address Counter Row 9 Address Buffers Refresh Control Clock 9 Row Decoders Output Buffers 8 DQ0 - DQ7 8 Input Buffers 8 I/O Controller 8 Output Buffers 8 Column Decoders 8 Input Buffers 8 8 Input Buffers 8 Sense Amps DQ8 - DQ15 32 I/O Selector 32 Memory Cells DQ16 - DQ23 8 Output Buffers 8 8 Input Buffers 8 On-chip VBB Generator 3/24 VSS DQ24 - DQ31 8 Output Buffers 8 MSM5432126/8 VCC Word Drivers 8 ¡ Semiconductor OE BLOCK DIAGRAM RAS WB / WE Timing Generator ¡ Semiconductor MSM5432126/8 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VT –0.5 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 3.0 — VCC + 1.0 V Input Low Voltage VIL –0.3 — 0.3 V Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance CIN — 8 pF Input / Output Capacitance CIO — 9 pF Parameter 4/24 ¡ Semiconductor MSM5432126/8 DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition Output High Voltage VOH IOH = –0.1 mA Output Low Voltage VOL IOL = 0.1 mA Input Leakage Current ILI Output Leakage Current MSM5432126/8 MSM5432126/8 MSM5432126/8 Unit Note -45 -50 -60 Min. Max. Min. Max. Min. Max. VCC VCC 2.0 2.0 2.0 VCC V 0 0.8 0 0.8 0 0.8 V 0 V < VIN < VCC; All other pins not under test = 0 V –10 10 –10 10 –10 10 mA ILO 0 V < VOUT < 5.5 V Output Disable –10 10 –10 10 –10 10 mA Average Power Supply Current (Operating) ICC1 RAS, CAS cycling, tRC = Min. — 150 — 140 — 130 mA 1, 2, 3 Power Supply Current (Standby) ICC2 RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V — 2 — 2 — 2 Average Power Supply Current (RAS Only Refresh) ICC3 RAS = cycling, CAS = VIH, tRC = Min. — 150 — 140 — 130 mA 1, 2, 3 Average Power Supply Current (Fast Page Mode) ICC4 RAS = VIL, CAS cycling, tHPC = Min. — 170 — 165 — 160 mA 1, 2, 4 Average Power Supply Current (CAS before RAS Refresh) ICC5 RAS = cycling, CAS before RAS — 150 — 140 — 130 mA 1, 2, 4 Notes: mA 1. Specified values are obtained with minimum cycle time. 2. ICC is dependent on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while RAS = VIL. 4. Address can be changed once or less while CAS = VIH. 5/24 ¡ Semiconductor MSM5432126/8 AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM5432126/8 MSM5432126/8 MSM5432126/8 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. tRC 100 — 110 — 130 — ns Read Modify Write Cycle tRWC 135 — 145 — 170 — ns Fast Page Mode Cycle Time tHPC 20 — 22 — 24 — ns tPRWC 65 — 70 — 80 — ns tRAC — 45 — 50 — 60 ns 4, 9,10 Access Time from Column Address tAA — 23 — 25 — 30 ns 4, 10 Access Time from CAS tCAC — 13 — 15 — 18 ns 4, 9 Access Time from CAS Precharge tCPA — 28 — 30 — 35 ns 4, 13 Output Buffer Turn-off Delay Time from RAS tREZ 3 20 3 20 3 20 ns 5 Output Buffer Turn-off Delay Time from CAS tCEZ 3 20 3 20 3 20 ns 5 tT 3 35 3 35 3 35 ns 3 RAS Precharge Time tRP 49 — 54 — 64 — ns RAS Pulse Width tRAS 45 10k 50 10k 60 10k ns RAS Pulse Width (Hyper Page Mode Only) tRASP 45 100k 50 100k 60 100k ns RAS Hold Time tRSH 12 — 14 — 14 — ns CAS Hold Time tCSH 45 — 50 — 60 — ns Random Read or Write Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from RAS Transition Time (Rise and Fall) CAS Pulse Width tCAS 7 10k 8 10k 9 10k ns RAS to CAS Delay Time tRCD 20 32 20 35 20 42 ns 9 RAS to Column Address Delay Time tRAD 15 22 15 25 15 30 ns 10 Column Address to RAS Lead Time tRAL 22 — 24 — 28 — ns CAS to RAS Precharge Time tCRP 6 — 6 — 8 — ns 13 CAS Precharge Time (Hyper Page Mode) tCP 7 — 8 — 9 — ns 15 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 6 — 7 — 9 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns 12 Column Address Hold Time tCAH 7 — 8 — 10 — ns 12 Column Address Hold Time referenced to RAS tAR 30 — 35 — 40 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns 12 Read Command Hold Time tRCH 0 — 0 — 0 — ns 6, 12 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 6 CAS "H" to RAS "H" Lead Time tCRL 0 — 0 — 0 — ns RAS "H" to CAS "H" Lead Time tRCL 0 — 0 — 0 — ns Data Output Hold after CAS Low tDOH 3 — 3 — 3 — ns 11 Write Command Set-up Time tWCS 0 — 0 — 0 — ns 8, 12 Write Command Hold Time tWCH 7 — 8 — 10 — ns 12 6/24 ¡ Semiconductor MSM5432126/8 AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM5432126/8 MSM5432126/8 MSM5432126/8 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Write Command Hold Time referenced to RAS tWCR 30 — 35 — 40 — ns Write Command Pulse Width tWP 8 — 9 — 10 — ns Write Command to RAS Lead Time tRWL 8 — 9 — 10 — ns Write Command to CAS Lead Time tCWL 8 — 9 — 10 — ns 14 Output Buffer Turn-off Delay Time from WE tWEZ 3 20 3 20 3 20 ns 5 Data Set-up Time tDS 0 — 0 — 0 — ns 7, 12 Data Hold Time tDH 7 — 8 — 10 — ns 7, 12 Data Hold Time referenced to RAS tDHR 30 — 35 — 40 — ns OE to Data-in Delay Time tOED 12 — 12 — 12 — ns RAS to WE Delay Time tRWD 65 — 70 — 80 — ns 8 Column Address to WE Delay Time tAWD 42 — 45 — 50 — ns 8 8 CAS to WE Delay Time tCWD 32 — 35 — 40 — ns Data to CAS Delay Time tDZC 0 — 0 — 0 — ns Data to OE Delay Time tDZO 0 — 0 — 0 — ns Access Time from OE tOEA — 13 — 15 — 18 ns Output Buffer Turn-off Delay Time from OE tOEZ 3 20 3 20 3 20 ns OE Command Hold Time tOEH 8 — 9 — 10 — ns RAS Hold Time referenced to OE tROH 10 — 10 — 12 — ns OE "L" to CAS "H" Lead Time tOCH 10 — 10 — 10 — ns CAS "H" to OE "L" Lead Time tCHO 10 — 10 — 10 — ns 5 High-Z Command Pulse Width tOEP 10 — 10 — 12 — ns WB/WE Pulse Width (Output Disable) tWPE 10 — 10 — 12 — ns CAS Set-up Time for CAS before RAS Cycle tCSR 6 — 8 — 10 — ns 12 CAS Hold Time for CAS before RAS Cycle tCHR 6 — 8 — 10 — ns 13 RAS Precharge to CAS Active Time tRPC 10 — 10 — 10 — ns 12 CAS Precharge Time (Refresh Counter Test) tCPT 20 — 25 — 30 — ns 15 Refresh Period tREF — 8 — 8 — 8 ms WB Set-up Time tWSR 0 — 0 — 0 — ns 16 WB Hold Time tRWH 6 — 7 — 8 — ns 16 Write-Per-Bit Mask Data Set-up Time tMS 0 — 0 — 0 — ns 16 Write-Per-Bit Mask Data Hold Time tMH 7 — 8 — 10 — ns 16 7/24 ¡ Semiconductor Notes: MSM5432126/8 1. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (Example : RAS only refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required. 2. The AC characteristics assume at tT = 3 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. Input levels at the AC testing are 3.0 V/0 V. 4. Data outputs are measured with a load of 30 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V. 5. tREZ (Max.), tCEZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. This parameter is sampled and not 100% tested. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to CAS leading edge of early write cycles and to WE leading edge in OE controlled write cycles and read modify write cycles. 8. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an early write cycle and the data out pin will remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 9. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 11. This is guaranteed by design. (tDOH = tCAC - output transition time) This parameter is not 100% tested. 12. These parameters are determined by the earliest falling edge of CAS1, CAS2, CAS3, or CAS4. 13. These parameters are determined by the latest rising edge of CAS1, CAS2, CAS3, or CAS4. 14. tCWL should be satisfied by all CASes. 15. tCP and tCPT are determined by the time that all CASes are high. 16. Only MSM5432128. 8/24 ¡ Semiconductor MSM5432126/8 CASn-DQ FUNCTION TABLE CAS1 CAS2 CAS3 CAS4 DQ0-7 DQ8-15 DQ16-23 DQ24-31 H H H H * * * * H H H L * * * Enable H H L H * * Enable * H H L L * * Enable Enable H L H H * Enable * * H L H L * Enable * Enable H L L H * Enable Enable * H L L L * Enable Enable Enable L H H H Enable * * * L H H L Enable * * Enable L H L H Enable * Enable * L H L L Enable * Enable Enable L L H H Enable Enable * * L L H L Enable Enable * Enable L L L H Enable Enable Enable * L L L L Enable Enable Enable Enable Enable * Read cycle Valid Data-out High-Z Write cycle Write Data Don't Care WRITE CYCLE FUNCTION TABLE RAS falling edge CODE CAS or WB / WE falling edge A B C Function WB / WE DQ DQ RWM (*1) L Write mask Write data Write per bit RW H (*2) Don't care Write data Normal write Write mask : 'L' = Mask, 'H' = No mask (*1): MSM5432128 only. (*2): In case of MSM5432126, don't care. 9/24 , ,, , ¡ Semiconductor MSM5432126/8 TIMING WAVEFORM Read Cycle (Outputs Controlled by RAS) tRC tRP tRAS RAS tCSH tCRP CAS1 | CAS4 tCRP tRSH tCAS tASR Address tRCD tRAD tRAH tASC Row tCRL tCAH tRAL Column tAR tRRH tRCS tRCH WB / WE tROH tOEA OE tCAC tAA DQ0 - DQ31 Open tRAC tOEZ tREZ Valid Data-out "H" or "L" 10/24 , ,, , ¡ Semiconductor MSM5432126/8 Read Cycle (Outputs Controlled by CAS) tRC tRP tRAS RAS tCSH tCRP CAS1 | CAS4 tCRP tRSH tCAS tASR Address tRCD tRAD tRAH tASC Row tCAH tRAL tRCL Column tRCH tAR tRCS tRRH WB / WE tROH tOEA OE tCAC tAA DQ0 - DQ31 Open tOEZ tCEZ Valid Data-out tRAC "H" or "L" 11/24 ¡ Semiconductor MSM5432126/8 Write Cycle (Early Write) tRC tRAS tRP tAR RAS tCSH CAS1 | CAS4 tCRP tRSH tRCD tCAS , ,,,, ,, tRAD tASR Address tRAL tASC tRAH Row Column tCWL tRWL tRWH tWSR WB / WE tCAH tWP A tWCS tWCH tWCR OE tMS DQ0 - DQ31 tMH tDS B tDH C tDHR "H" or "L" 12/24 ¡ Semiconductor MSM5432126/8 Write Cycle (OE Control Write) tRC tRAS RAS tRP tAR , ,,, ,, tCSH CAS1 | CAS4 tCRP tRAD tRAH tASR Address tRAL tASC Row tWSR WB / WE tRSH tCAS tRCD tCAH Column tRWH tCWL tRWL tRCS tWP A tWCR tOEH OE tOED tDHR tMS DQ0 - DQ31 tMH B tDS tDH C "H" or "L" 13/24 ¡ Semiconductor MSM5432126/8 Read Modify Write Cycle tRWC tRAS RAS tRP tAR , ,, tCSH CAS1 | CAS4 tCRP tRCD tCAS tRAD tASR Address tRSH tRAL tASC tRAH Row tCAH Column tCWL tWSR WB / WE tRWH tCWD tRCS tRWL tWP A tAWD tRWD tOEA OE tDZO tMS DQ0 - DQ31 tMH tAA B tRAC tDZC tCAC tOEZ OUT tOEH tOED tDS tDH C "H" or "L" 14/24 ,, ,, ¡ Semiconductor MSM5432126/8 Fast Page Mode Read Cycle with EDO tRC tRASP tAR RAS tCSH tCRP CAS1 | CAS4 tHPC tRCD tRSH tCP tCAS tCAS tRAD tRAL tASC tASC tCAH tRAH tCRP tCP tCAS tASR Address tRP Row Column tASC tCAH Column tRCS tRCS tRCH tCAH Column tRRH tRCS tRCH tRCH WB / WE tOEA OE tCAC tAA DQ0 - DQ31 tCAC tDOH Valid Data-out Open tRAC tAA tCPA tCAC tDOH Valid Data-out tREZ tOEZ Valid Data-out tAA tCPA "H" or "L" 15/24 ¡ Semiconductor MSM5432126/8 Fast Page Mode Write Cycle (Early Write) tRC tRASP tRP tAR RAS tCSH tCRP tHPC tRCD tCAS CAS1 | CAS4 tCP tCAS tRSH tCRP tCP tCAS ,, ,, tRAD tASR tRAH Address tASC Row tCAH tASC Column tCAH Column tCWL tWSR tRWH tWCS WB / WE tWCH tWP A tASC tRAL tCAH Column tCWL tWCS tWCH tWP tCWL tWCS tWCH tWP tWCR tRWL OE tDHR tMS tMH DQ0 - DQ31 B tDS tDH C tDS tDH tDS tDH C C "H" or "L" 16/24 ¡ Semiconductor MSM5432126/8 Fast Page Mode Read Modify Write Cycle tRC tRASP tRP tAR RAS tCSH tCRP tPRWC tRCD tCP tCAS tRSH tCRP tCP tCAS tCAS ,, ,, , CAS1 | CAS4 tRAD tASR tRAH Address tASC Row Column tASC tCWL tRWD tAWD tOEA tCWD tCWL tAWD tOEA tWP tOED tAA tMS tMH tDS B OUT tCAC tAA tOEZ tDH C tDS OUT tCAC tRAL tCAH Column A OE DQ0 - DQ31 tCAH Column tCWD tWSR tRWH tRCS WB / WE tASC tCAH tWP tOED tAA tOEZ tDH C tRWL tCWL tCWD tAWD tOEA tWP tROH tOED tOEZ tDS OUT tOEH tDH C tCAC tRAC "H" or "L" 17/24 ,,,, ¡ Semiconductor MSM5432126/8 RAS Only Refresh Cycle tRC tRP tRAS RAS tRPC tCRP CAS1 | CAS4 Address tASR tRAH Row Note: DQs are open, WB / WE, OE = "H" or "L" "H" or "L" 18/24 ¡ Semiconductor MSM5432126/8 CAS before RAS Refresh Cycle tRC tRP RAS tRAS tRP tRPC tCP tCSR tCHR CASn tCEZ DQ0 - DQ31 Open Note: WB / WE, OE, A0 - A8 = "H" or "L" 19/24 ,,, , ¡ Semiconductor MSM5432126/8 Hidden Refresh Read Cycle tRC tRC tRAS tRP tRAS tRP RAS tCRP tRSH tRCD tCHR CAS1 | CAS4 tASR Address tRAD tRAH tASC Row tRAL tCAH Column tAR tRCS tRRH WB / WE tROH OE tOEA tCAC DQ0 - DQ31 tOEZ tREZ Valid Data-out tAA tRAC "H" or "L" 20/24 ¡ Semiconductor MSM5432126/8 Hidden Refresh Write Cycle tRC tRAS tRC tRAS tRP tRP ,,,, ,, RAS tCRP CAS1 | CAS4 tRSH tCHR tRAL tRAD tASC tASR Address tRCD tRAH tCAH Column Row tAR tWSR WB / WE tRWH tWCS tWCH tWP A tRWL tWCR OE tMS DQ0 - DQ31 tMH tDS tDH B C tDHR "H" or "L" 21/24 ¡ Semiconductor MSM5432126/8 , , ,,, , CAS before RAS Refresh Counter Test Cycle tRAS tRP RAS CAS1 | CAS4 tCSR tCHR tCPT tRSH tCAS tASC tCAH Column Address tRAL Read Cycle tRCS WB / WE tRRH tRCH tCAC tROH tAA tOEA OE tAA DQ0 - DQ31 tOEZ Open tCEZ Valid Data-out tRWL tCWL Write Cycle tWCS tWCH tWP tDS tDH WB / WE OE DQ0 - DQ31 Open Valid Data-in tRWL tCWL tAWD tCWD Read Modify Write Cycle tRCS tWP WB / WE tOEA OE tAA DQ0 - DQ31 Open tCAC tOEZ Valid Data-out tOED tDS tDH Valid Data-in "H" or "L" 22/24 tAR RAS tCSH tCRP CAS1 | CAS4 tHPC tRCD tCP tCAS tRSH tCP tCP tCAS tCRP tCAS tCAS , tRAL tRAD tASR tRAH Address tASC Row tCAH tASC tCAH tASC tCAH tASC tCAH Column Column Column Column tRRH tRCS tRCH tRCH tRCS WB / WE tRAC tCHO tOEA tCAC tCAC Valid Data-out tOEP tAA tOEZ Valid Data-out tOEA tCAC tOEZ tOEA Valid* Data-out tWEZ tAA Valid* Data-out tREZ Valid Data-out 23/24 * : Same Data "H" or "L" MSM5432126/8 Open tDOH tWPE tCAC tCPA tAA DQ0 - DQ31 tOEP tAA OE tOCH ¡ Semiconductor tRP Fast Page Mode Read with EDO High-Z Operation tRC tRASP ¡ Semiconductor MSM5432126/8 PACKAGE DIMENSIONS (Unit : mm) SSOP64-P-525-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.34 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/24