Infineon BTS740S2 Smart high-side power switch Datasheet

Smart High-Side Power Switch
BTS740S2
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Data Sheet
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V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
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Channel 1
Control and protection circuit
of
channel 2
287
PROFET
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
7
17,18
13,14
4
8
2
6
5
9
Data Sheet
Pin configuration
Symbol Function
Vbb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
IN1
Input 1,2, activates channel 1,2 in case of
IN2
logic high signal
OUT1
Output 1,2, protected high-side power output
OUT2
of channel 1,2. Both pins of each output have
to be connected in parallel for operation
according ths spec (e.g. kilis). Design the wiring
for the max. short circuit current
ST1
Diagnostic feedback 1,2 of channel 1,2,
ST2
open drain, invers to input level
GND1
Ground 1 of chip 1 (channel 1)
GND2
Ground 2 of chip 2 (channel 2)
IS1
Sense current output 1,2; proportional to the
load current, zero in the case of current
IS2
limitation of the load current
2
(top view)
Vbb
GND1
IN1
ST1
IS1
GND2
IN2
ST2
IS2
Vbb
1
2
3
4
5
6
7
8
9
10
•
20
19
18
17
16
15
14
13
12
11
Vbb
Vbb
OUT1
OUT1
Vbb
Vbb
OUT2
OUT2
Vbb
Vbb
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Maximum Ratings at Tj = 25°C unless otherwise specified
Parameter
Symbol
Supply voltage (overvoltage protection see page 5)
Supply voltage for full short circuit protection
Tj,start = -40 ...+150°C
Load current (Short-circuit current, see page 5)
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V
RI2) = 2 Ω, td = 200 ms; IN = low or high,
each channel loaded with RL = 7.0 Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)4)
Ta = 25°C:
(all channels active)
Ta = 85°C:
Maximal switchable inductance, single pulse
Vbb = 12V, Tj,start = 150°C4),
IL = 5.5 A, EAS = 370 mJ, 0 Ω
one channel:
IL = 8.5 A, EAS = 790 mJ, 0 Ω
two parallel channels:
Vbb
Vbb
Values
Unit
43
34
V
V
IL
VLoad dump3)
self-limited
60
A
V
Tj
Tstg
Ptot
-40 ...+150
-55 ...+150
3.8
2.0
°C
18
16
mH
1.0
4.0
8.0
kV
-10 ... +16
±2.0
±5.0
±14
V
mA
Values
typ
Max
Unit
ZL
W
see diagrams on page 10
Electrostatic discharge capability (ESD)
IN: VESD
(Human Body Model)
ST, IS:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
VIN
IIN
IST
IIS
nput voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
Current through current sense pin (DC)
see internal circuit diagram page 9
Thermal Characteristics
Parameter and Conditions
Symbol
min
Thermal resistance
junction - soldering point4),5)
each channel: Rthjs
4)
junction - ambient
one channel active: Rthja
all channels active:
)
----
-40
33
12
---
K/W
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
) R = internal resistance of the load dump test pulse generator
I
) V
Load dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for V
bb
connection PCB is vertical without blown air See page 15
Data Sheet
3
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT); IL = 5 A
each channel,
Tj = 25°C: RON
Tj = 150°C:
Values
min
typ
max
--
IL = 0.5 A
Nominal load current
mΩ
27
54
30
60
14
15
--
50
--
mV
4.9
7.8
5.5
8.5
--
A
--
--
8
mA
25
25
70
80
150
200
µs
dV/dton
0.1
--
1
V/µs
-dV/dtoff
0.1
--
1
V/µs
5.0
3.2
--
--4.5
34
5.0
5.5
6.0
V
V
V
----
4.7
-0.5
6.5
7.0
--
V
34
33
---
43
--
V
V
two parallel channels, Tj = 25°C:
Output voltage drop limitation at small load
currents, see page 14
Unit
VON(NL)
Tj =-40...+150°C:
one channel active: IL(NOM)
two parallel channels active:
Device on PCB6), Ta = 85°C, Tj ≤ 150°C
Output current while GND disconnected or pulled up7); IL(GNDhigh)
Vbb = 30 V, VIN = 0, see diagram page 10
Turn-on time8)
IN
Turn-off time
IN
RL = 12 Ω
Slew rate on 8)
10 to 30% VOUT, RL = 12 Ω:
Slew rate off 8)
70 to 40% VOUT, RL = 12 Ω:
to 90% VOUT: ton
to 10% VOUT: toff
Operating Parameters
Operating voltage9)
Undervoltage shutdown
Undervoltage restart
Vbb(on)
Vbb(under)
Tj =-40...+25°C: Vbb(u rst)
Tj =+150°C:
Undervoltage restart of charge pump
see diagram page 13
Tj =-40...+25°C: Vbb(ucp)
Tj =150°C:
Undervoltage hysteresis
∆Vbb(under)
V
∆Vbb(under) = Vbb(u rst) - Vbb(under)
Vbb(over)
Vbb(o rst)
Overvoltage shutdown
Overvoltage restart
6)
7)
8)
9)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 15
not subject to production test, specified by design
See timing diagram on page 11.
At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT ≈Vbb - 2 V
Data Sheet
4
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
∆Vbb(over)
Tj =-40: Vbb(AZ)
Ibb=40 mA
Tj =+25...+150°C:
Standby current11)
Tj =-40°C...25°C: Ibb(off)
VIN = 0;
Tj =150°C:
Leakage output current (included in Ibb(off))
IL(off)
VIN = 0
Operating current 12), VIN = 5V,
IGND = IGND1 + IGND2,
one channel on: IGND
two channels on:
Overvoltage hysteresis
Overvoltage protection10)
Values
min
typ
max
Unit
-41
43
----
1
-47
8
24
--
--52
30
50
20
V
V
---
1.2
2.4
3
6
mA
48
40
31
56
50
37
65
58
45
A
---
24
24
---
A
--
2.0
--
ms
41
43
150
--
-47
-10
-52
---
V
µA
µA
Protection Functions13)
Current limit, (see timing diagrams, page 12)
Tj =-40°C: IL(lim)
Tj =25°C:
Tj =+150°C:
Repetitive short circuit current limit,
Tj = Tjt
each channel IL(SCr)
two parallel channels
(see timing diagrams, page 12)
Initial short circuit shutdown time
Tj,start =25°C: toff(SC)
(see timing diagrams on page 12)
Output clamp (inductive load switch off)14)
at VON(CL) = Vbb - VOUT, IL= 40 mA
Tj =-40°C: VON(CL)
Tj =25°C...150°C:
Thermal overload trip temperature
Tjt
Thermal hysteresis
∆Tjt
10)
11)
12)
13
14)
°C
K
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram page 9.
Measured with load; for the whole device; all channels off
Add IST, if IST > 0
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
Data Sheet
5
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Reverse Battery
Reverse battery voltage 15)
Drain-source diode voltage (Vout > Vbb)
IL = - 4.0 A, Tj = +150°C
Values
min
typ
max
Unit
-Vbb
-VON
---
-600
32
--
kILIS
4350
3100
4800
4800
5800
7800
4350
3800
4800
4800
5350
6300
5.4
6.1
6.9
V
IIS(LL)
IIS(LH)
IIS(SH) 18)
0
0
0
----
1
15
10
µA
tson(IS)
--
--
300
µs
Current sense settling time to 10% of IIS static after
0A
tsoff(IS)
negative input slope18), IL = 5
--
30
100
µs
Current sense rise time (60% to 90%) after change
5A
tslc(IS)
of load current18) IL = 2.5
--
10
--
µs
VOUT(OL)
2
3
4
V
RO
5
15
40
kΩ
V
mV
Diagnostic Characteristics
Current sense ratio16), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.517)...27V,
kILIS = IL / IIS
Tj = -40°C, IL = 5 A:
Tj= -40°C, IL= 0.5 A:
Tj= 25...+150°C, IL= 5 A:
Tj= 25...+150°C, IL = 0.5 A:
Current sense output voltage limitation
Tj = -40 ...+150°C
IIS = 0, IL = 5 A:
Current sense leakage/offset current
Tj = -40 ...+150°C
VIN=0, VIS = 0, IL = 0:
VIN=5 V, VIS = 0, IL = 0:
VIN=5 V, VIS = 0, VOUT = 0 (short circuit)
Current sense settling time to IIS static±10% after
5A
positive input slope18), IL = 0
Open load detection voltage19) (off-condition)
Internal output pull down
(pin 17,18 to 2 resp. 13,14 to 6), VOUT=5 V
15)
VIS(lim)
Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and
circuit page 9).
16) This range for the current sense ratio refers to all devices. The accuracy of the k can be raised at least by
ILIS
a factor of two by matching the value of kILIS for every single device.
In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is
High. See figure 2c, page 12.
17) Valid if V
bb(u rst) was exceeded before.
18) not subject to production test, specified by design
19) External pull up resistor required for open load detection in off state
Data Sheet
6
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Parameter and Conditions, each of the two channels
Symbol
Values
min
typ
max
RI
3.0
4.5
7.0
kΩ
VIN(T+)
VIN(T-)
∆ VIN(T)
IIN(off)
IIN(on)
td(ST OL3)
-1.5
-1
20
--
--0.5
-50
400
3.5
--50
90
--
V
V
V
µA
µA
µs
tdon(ST)
--
13
--
µs
tdoff(ST)
--
1
--
µs
5.4
----
6.1
----
6.9
0.4
0.7
2
V
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Input and Status Feedback20)
Input resistance
Unit
(see circuit page 9)
Input turn-on threshold voltage
Input turn-off threshold voltage
Input threshold hysteresis
Off state input current
VIN = 0.4 V:
On state input current
VIN = 5 V:
Delay time for status with open load
after Input neg. slope (see diagram page 13)
Status delay after positive input slope
(not subject to production test, specified by design)
Status delay after negative input slope
(not subject to production test, specified by design)
Status output (open drain)
Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: VST(high)
ST low voltage
Tj =-40...+25°C, IST = +1.6 mA: VST(low)
Tj = +150°C, IST = +1.6 mA:
Status leakage current, VST = 5 V,
Tj=25 ... +150°C: IST(high)
20)
µA
If ground resistors RGND are used, add the voltage drop across these resistors.
Data Sheet
7
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Truth Table
Input 1
Output 1
Status 1
Input 2
Output 2
Status 2
level
level
level
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
L21)
L
L
H
H
H
L
H
H
H
H
H
H
L22)
L
H (L25))
L
H
L
H
L
H
Normal
operation
Currentlimitation
Short circuit to
GND
Overtemperature
Short circuit to
Vbb
Open load
Undervoltage
Overvoltage
L24)
H
L
L
L
L
L
Current
Sense 1
Current
Sense 2
IIS
0
nominal
0
0
0
0
0
0
0
<nominal 23)
0
0
0
0
0
0
0
Negative output
voltage clamp
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal after the time delay shown in the diagrams (see fig 5. page 13)
Parallel switching of channel 1 and 2 is possible by connecting the inputs and outputs in parallel. The status
outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor. The current
sense outputs IS1 and IS2 have to be connected with a single pull-down resistor.
Terms
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Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.
21)
The voltage drop over the power transistor is Vbb-VOUT > 3V typ. Under this condition the sense current IIS is
zero
22) An external short of output to V , in the off state, causes an internal current from output to ground. If R
bb
GND
is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
23) Low ohmic short to V may reduce the output current I and therefore also the sense current I .
bb
L
IS
24) Power Transistor off, high impedance
Data Sheet
8
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Input circuit (ESD protection), IN1 or IN2
Inductive and overvoltage output clamp,
OUT1 or OUT2
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The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
Status output, ST1 or ST2
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Overvoltage and reverse batt. protection
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ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 Ω
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
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VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 Ω,
RST=15kΩ, RI=4.5kΩ typ., RIS=1kΩ, RV=15kΩ,
In case of reverse battery the current has to be limited
by the load. Temperature protection is not active
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Open-load detection OUT1 or OUT2
ESD-Zener diode: 6.1 V typ., max 14 mA;
RIS = 1 kΩ nominal
OFF-state diagnostic condition:
VOUT > 3 V typ.; IN low
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Data Sheet
9
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Inductive load switch-off energy
dissipation
GND disconnect
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Any kind of load. In case of IN = high is VOUT ≈ VIN - VIN(T+).
Due to VGND > 0, no VST = low signal available.
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Energy stored in load inductance:
2
EL = 1/2·L·I L
GND disconnect with GND pull up
While demagnetizing load inductance, the energy
dissipated in PROFET is
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EAS= Ebb + EL - ER= VON(CL)·iL(t) dt,
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with an approximate solution for RL > 0 Ω:
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Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
IL· L
(V + |VOUT(CL)|)
2·RL bb
OQ(1+ |V
IL·RL
OUT(CL)|
)
Maximum allowable load inductance for
a single switch off (one channel)4)
/ I ,/ Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
ZL [mH]
Vbb disconnect with energized inductive
load
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For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 10) each switch is
protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current
flows through the GND connection.
Data Sheet
10
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
Figure 1a: Switching a resistive load,
change of load current in on-condition:
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition:
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W doff(ST)
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W off
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W slc(IS)
W soff(IS)
W
off
,/
/RDG
W son(IS)
G9GWRII
W
W
The sense signal is not valid during settling time after turn or
change of load current.
Figure 2b: Switching a lamp:
Figure 1b: Vbb turn on:
,1
,1
,1
67
9 EE
9
287
9
9
287
287
,
67RSHQGUDLQ
/
W
67RSHQGUDLQ
W
proper turn on under all conditions
Data Sheet
11
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Figure 2c: Switching a lamp with current limit:
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
,1
,1
67
,
RWKHUFKDQQHOQRUPDORSHUDWLRQ
/
,
9287
/ OLP
,
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67
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Heating up of the chip may require several milliseconds, depending
on external conditions
Figure 2d: Switching an inductive load
,1
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
,1
67
,,
//
[,/ OLP
9
287
,
,
/ 6&U
/
, / 2/
W
W
RII 6&
6 ,6 *) if the time constant of load is too large, open-load-status may
occur
67
W
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor
Data Sheet
12
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Figure 6a: Undervoltage:
Figure 4a: Overtemperature:
Reset if Tj <Tjt
,1
,1
67
67
,/
QRWGHILQHG
9
EE
Vbb(u cp)
V
bb(under)
, ,6
,
7-
9bb(u rst)
/
,,6
W
W
Figure 6b: Undervoltage restart of charge pump
Figure 5a: Open load: detection (with REXT),
turn on/off to open load
921 &/
9RQ
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charge pump starts at Vbb(ucp) =4.7 V typ.
Data Sheet
13
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Figure 8b: Current sense ratio:
Figure 7a: Overvoltage:
N ,/,6
,1
67
VON(CL)
9bb
V
bb(over)
V
bb(o rst)
,/
,
,6
W
Figure 8a: Current sense versus load current26::
>P$@
>$@ , /
Figure 9a: Output voltage drop versus load current:
921
>9@
, ,6
521
921 1/
,/
>$@ ,/
26
>$@ This range for the current sense ratio refers to all
devices. The accuracy of the kILIS can be raised at
Data Sheet
14
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
1.27
0.35
0.35 x 45˚
7.6 -0.2 1)
0.23 +0.0
9
8˚ ma
x
2.65 max
2.45 -0.2
0.2 -0.1
Package Outlines
0.4 +0.8
+0.15 2)
0.2 24x
20
0.1
10.3 ±0.3
11
GPS05094
1 12.8 1) 10
-0.2
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Figure 1
PG-DSO-20 (Plastic Dual Small Outline Package) (RoHS-compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Please specify the package needed (e.g. green package) when placing an order
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
17
Dimensions in mm
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS740S2
Revision History
Version
1.0
Data Sheet
Date
Changes
2007-05-13
Creation of the green datasheet.
18
V1.0, 2007-05-13
Edition 2007-05-13
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 5/13/07.
All Rights Reserved.
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stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
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