Revised March 2005
74ABT541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The ABT541 is an octal buffer and line driver with 3-STATE
outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The ABT541 is similar to the ABT244 with broadside pinout.
■ Non-inverting buffers
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance, glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
■ Flow-through pinout for ease of PC board layout
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT541CSC
74ABT541CSJ
Package Number
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT541CMSA
MSA20
74ABT541CMTC
MTC20
74ABT541CPC
Package Description
M20B
N20A
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
Description
OE1, OE2
Output Enable Input (Active LOW)
I0–I7
Inputs
O0–O7
Outputs
Truth Table
Inputs
OE1
DS011501
I
L
L
H
H
X
X
Z
X
H
X
Z
L
L
L
L
H HIGH Voltage Level
L LOW Voltage Level
© 2005 Fairchild Semiconductor Corporation
Outputs
OE2
X
Z
H
Immaterial
High Impedance
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74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
September 1992
74ABT541
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-Off State
in the HIGH State
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
500 mA
DC Latchup Source Current
Over Voltage Latchup (I/O)
10V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
IIN
18 mA
VOH
Output HIGH Voltage
2.5
V
Min
IOH
3 mA
2.0
V
Min
IOH
32 mA
V
Min
IOL
64 mA
PA
Max
VIN
2.7V (Note 4)
VIN
VCC
PA
Max
VIN
7.0V
PA
Max
VIN
0.5V (Note 4)
V
0.0
VOL
Output LOW Voltage
IIH
Input HIGH Current
2.0
V
0.55
1
1
IBVI
Input HIGH Current
7
Breakdown Test
IIL
1
Input LOW Current
1
Recognized HIGH Signal
Recognized LOW Signal
VIN
0.0V
IID
1.9 PA
VID
Input Leakage Test
IOZH
Output Leakage Current
10
PA
0 5.5V
VOUT
2.7V; OEn
2.0V
IOZL
Output Leakage Current
10
PA
0 5.5V
VOUT
0.5V; OEn
2.0V
IOS
Output Short-Circuit Current
275
mA
Max
VOUT
0.0V
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
VCC
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.5V; All Others GND
ICCH
Power Supply Current
50
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
PA
Max
4.75
All Other Pins Grounded
100
OEn
VCC;
All Others at VCC or Ground
ICCT
Additional ICC/Input
Outputs Enabled
2.5
mA
Outputs 3-STATE
2.5
mA
Outputs 3-STATE
50
PA
VI
Max
VCC 2.1V
VCC 2.1V
Enable Input VI
Data Input VI
VCC 2.1V;
All Others at VCC or Ground
ICCD
Dynamic ICC
No Load
mA/
(Note 4)
0.1
MHz
Outputs Open, OEn
Max
50% Duty Cycle
Note 3: For 8 bits toggling, ICCD 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
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2
GND,
One Bit Toggling (Note 3),
(SOIC Package)
Symbol
Parameter
Min
Conditions
Typ
Max
Units
VCC
0.7
1.0
V
5.0
TA
25qC (Note 5)
CL
50 pF, RL
VOLP
Quiet Output Maximum Dynamic VOL
VOLV
Quiet Output Minimum Dynamic VOL
1.3
0.8
V
5.0
TA
25qC (Note 5)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.7
3.1
V
5.0
TA
25qC (Note 6)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.4
V
5.0
TA
25qC (Note 7)
VILD
Maximum LOW Level Dynamic Input Voltage
V
5.0
TA
25qC (Note 7)
1.1
0.6
500:
Note 5: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
25qC
TA
Symbol
VCC
Parameter
CL
TA
5V
40qC to 85qC
VCC
50 pF
4.5V–5.5V
CL
Units
50 pF
Min
Typ
Max
Min
tPLH
Propagation Delay
1.0
2.0
3.6
1.0
3.6
tPHL
Data to Outputs
1.0
2.4
3.6
1.0
3.6
tPZH
Output Enable Time
1.5
3.1
6.0
1.5
6.0
1.5
3.7
6.0
1.5
6.0
1.7
3.5
6.1
1.7
6.1
1.7
3.1
5.6
1.7
5.6
40qC to 85qC
TA
tPZL
tPHZ
Output Disable Time
tPLZ
Max
ns
ns
ns
Extended AC Electrical Characteristics
(SOIC Package)
40qC to 85qC
Symbol
CL
Parameter
TA
4.5V–5.5V
VCC
VCC
50 pF
CL
8 Outputs Switching
250 pF
1 Output Switching
(Note 8)
Min
4.5V–5.5V
(Note 9)
Typ
40qC to 85qC
VCC
CL
4.5V–5.5V
250 pF
(Note 10)
Max
Min
Max
Min
Max
fTOGGLE
Max Toggle Frequency
tPLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.5
tPHL
Data to Outputs
1.5
5.0
1.5
6.0
2.5
8.5
tPZH
Output Enable Time
1.5
6.5
2.5
7.5
2.5
9.5
1.5
6.5
2.5
7.5
2.5
10.5
1.0
6.1
1.0
5.6
tPZL
tPHZ
tPLZ
Output Disable Time
Units
8 Outputs Switching
100
MHz
(Note 11)
ns
ns
ns
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delays are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
3
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74ABT541
DC Electrical Characteristics
74ABT541
Skew
(SOIC Package)
TA
40qC to 85qC
VCC
Symbol
tOSHL
CL
Parameter
4.5V–5.5V
50 pF
TA
40qC to 85qC
VCC
CL
4.5V–5.5V
250 pF
Units
8 Outputs Switching
8 Outputs Switching
(Note 12)
(Note 13)
Max
Max
Pin to Pin Skew, HL Transitions
1.3
2.3
ns
Pin to Pin Skew, LH Transitions
1.0
1.8
ns
Duty Cycle, LH/HL Skew
2.0
3.5
ns
Pin to Pin Skew, LH/HL Transitions
2.0
3.5
ns
Device to Device Skew, LH/HL Transitions
2.0
3.5
ns
(Note 14)
tOSLH
(Note 14)
tPS
(Note 15)
tOST
(Note 14)
tPV
(Note 16)
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). The specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
TA
25qC
CIN
Input Capacitance
5.0
pF
VCC
0.0V
COUT (Note 17)
Output Capacitance
9.0
pF
VCC
5.0V
Note 17: COUT is measured at frequency of f
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1 MHz, per MIL-STD-883, Method 3012.
4
74ABT541
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW
Enable and Disable Time
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and
Recovery Time Waveforms
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74ABT541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
74ABT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74ABT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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8
74ABT541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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