MCNIX MX27C1100PC-10 1m-bit [128k x 8/64k x 16] cmos eprom Datasheet

MX27C1100/27C1024
1M-BIT [128K x 8/64K x 16] CMOS EPROM
FEATURES
• 64K x 16 organization(MX27C1024, JEDEC pin out)
• 128K x 8 or 64K x 16 organization(MX27C1100, ROM
•
•
•
•
• Operating current: 40mA
• Standby current: 100uA
• Package type:
pin out compatible)
+12.5V programming voltage
Fast access time: 55/70/85/100/120/150 ns
Totally static operation
Completely TTL compatible
- 40 pin plastic DIP
- 40 pin plastic SOP
- 44 pin PLCC
GENERAL DESCRIPTION
The MX27C1024 is a 5V only, 1M-bit, One Time
Programmable Read Only Memory. It is organized as
64K words by 16 bits per word(MX27C1024), 128K x 8
or 64K x 16(MX27C1100), operates from a single + 5
volt supply, has a static standby mode, and features
fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing
EPROM programmers may be used. The MX27C1100/
1024 supports a intelligent fast programming algorithm
which can result in programming time of less than thirty
seconds.
PIN CONFIGURATIONS
BLOCK DIAGRAM (MX27C1100)
This EPROM is packaged in industry standard 40 pin
dual-in-line packages, 40 lead SOP and 44 lead PLCC
packages.
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MX27C1100
PDIP/SOP(MX27C1100)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CE
OE
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
CONTROL
LOGIC
BYTE/VPP
A0~A15
ADDRESS
INPUTS
.
.
.
.
.
.
.
.
Y-DECODER
X-DECODER
OUTPUT
BUFFERS
.
.
.
.
.
.
.
.
Q0~Q14
Q15/A-1
Y-SELECT
1M BIT
CELL
MAXTRIX
VCC
GND
P/N: PM0156
REV. 4.6, JAN. 14, 2003
1
MX27C1100/27C1024
PIN CONFIGURATIONS
PDIP/SOP(MX27C1024)
Q12
7
6
1 44
A14
A15
NC
PGM
VCC
NC
VPP
CE
Q15
Q14
Q13
VCC
PGM
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
40
39
A13
Q11
A12
Q10
A11
Q9
A10
Q8
GND
A9
MX27C1024
12
34
GND
NC
NC
Q7
A8
Q6
A7
A6
Q5
29
28
A3
A2
A1
A0
NC
OE
Q0
23
A5
A4
17
18
Q1
Q4
Q2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MX27C1024
VPP
CE
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
GND
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE
PLCC(MX27C1024)
BLOCK DIAGRAM (MX27C1024)
CE
PGM
OE
A0~A15
ADDRESS
INPUTS
CONTROL
LOGIC
.
.
.
.
.
.
.
Y-DECODER
X-DECODER
P/N: PM0156
.
.
.
.
.
.
.
Q0~Q15
Y-DECODER
1M BIT
CELL
MAXTRIX
.
.
VCC
GND
OUTPUT
BUFFERS
VPP
2
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
PIN DESCRIPTION(MX27C1024)
PIN DESCRIPTION(MX27C1100)
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A0~A15
Address Input
A0~A15
Address Input
Q0~Q14
Data Input/Output
Q0~Q15
Data Input/Output
CE
Chip Enable Input
CE
Chip Enable Input
OE
Output Enable Input
OE
Output Enable Input
BYTE/VPP
Word/Byte Selection
PGM
Program Enable Input
/Program Supply Voltage
VPP
Program Supply Voltage
Q15/A-1
Q15(Word mode)/LSB addr. (Byte mode)
VCC
Power Supply Pin (+5V)
VCC
Power Supply Pin (+5V)
GND
Ground Pin
GND
Ground Pin
TRUTH TABLE OF BYTE FUNCTION(MX27C1100)
BYTE MODE(BYTE = GND)
CE
OE
Q15/A-1
MODE
Q0-Q7
SUPPLY CURRENT
H
X
X
Non selected
High Z
Standby(ICC2)
L
H
X
Non selected
High Z
Operating(ICC1)
L
L
A-1 input
Selected
DOUT
Operating(ICC1)
WORD MODE(BYTE = VCC)
CE
OE
Q15/A-1
MODE
Q0-Q14
SUPPLY CURRENT
H
X
High Z
Non selected
High Z
Standby(ICC2)
L
H
High Z
Non selected
High Z
Operating(ICC1)
L
L
DOUT
Selected
DOUT
Operating(ICC1)
NOTE : X = H or L
P/N: PM0156
3
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
FUNCTIONAL DESCRIPTION
VIL(for MX27C1024), OE at VIL, CE at VIH(for
MX27C1100)and VPP at its programming voltage.
THE PROGRAMMING OF THE MX27C1100/1024
When the MX27C1100/1024 is delivered, or it is
erased, the chip has all 1M bits in the "ONE" or HIGH
state. "ZEROs" are loaded into the MX27C1100/1024
through the procedure of programming.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient
temperature range that is required when programming
the MX27C1100/1024.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP, and
removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm
is shown in Figure 1). The programming is achieved by
applying a single TTL low level 100us pulse to the PGM
input after addresses and data line are stable. If the data
is not verified, an additional pulse is applied for a
maximum of 25 pulses. This process is repeated while
sequencing through each address of the device. When
the programming mode is completed, the data in all
address is verified at VCC = VPP = 5V ± 10%.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C1100/1024, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
READ MODE
The MX27C1100/1024 has two control functions, both
of which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - t OE.
PROGRAM INHIBIT MODE
Programming of multiple MX27C1100/1024's in parallel
with different data is also easily accomplished by using
the Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C1100/1024 may be
common. A TTL low-level program pulse applied to an
MX27C1100/1024 CE input with VPP = 12.5 ± 0.5 V will
program the MX27C1100/1024. A high-level CE input
inhibits the other MX27C1100/1024s from being
programmed.
WORD-WIDE MODE
PROGRAM VERIFY MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE and CE at
P/N: PM0156
4
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
BYTE-WIDE MODE
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
STANDBY MODE
The MX27C1100/1024 has a CMOS standby mode
which reduces the maximum VCC current to 100 uA. It
is placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C1100/1024 also has a TTL-standby mode
which reduces the maximum VCC current to 1.5 mA. It
is placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
P/N: PM0156
5
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
MODE SELECT TABLE (MX27C1024)
PINS
MODE
CE
OE
PGM
A0
A9
VPP
OUTPUTS
Read
VIL
VIL
X
X
X
VCC
DOUT
Output Disable
VIL
VIH
X
X
X
VCC
High Z
Standby (TTL)
VIH
X
X
X
X
VCC
High Z
Standby (CMOS)
VCC±0.3V
X
X
X
X
VCC
High Z
Program
VIL
VIH
VIL
X
X
VPP
DIN
Program Verify
VIL
VIL
VIH
X
X
VPP
DOUT
Program Inhibit
VIH
X
X
X
X
VPP
High Z
Manufacturer Code(3)
VIL
VIL
X
VIL
VH
VCC
00C2H
Device Code(3)
VIL
VIL
X
VIH
VH
VCC
0115H
NOTES:1. VH = 12.0 V ± 0.5 V
2 . X = Either VIH or VIL
3. A1 - A8 = A10 - A15 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during
programming.
MODE SELECT TABLE (MX27C1100)
BYTE/
MODE
CE
OE
A9
A0
Q15/A-1
VPP(5)
Q8-14
Q0-7
Read (Word)
VIL
VIL
X
X
Q15 Out
VCC
Q8-14 Out
Q0-7 Out
Read (Upper Byte)
VIL
VIL
X
X
VIH
GND
High Z
Q8-15 Out
Read (Lower Byte)
VIL
VIL
X
X
VIL
GND
High Z
Q0-7 Out
Output Disable
VIL
VIH
X
X
High Z
X
High Z
High Z
Standby
VIH
X
X
X
High Z
X
High Z
High Z
Program
VIL
VIH
X
X
Q15 In
VPP
Q8-14 In
Q0-7 In
Program Verify
VIH
VIL
X
X
Q15 Out
VPP
Q8-14 Out
Q0-7 Out
Program Inhibit
VIH
VIH
X
X
High Z
VPP
High Z
High Z
Manufacturer Code(3)
VIL
VIL
VH
VIL
0B
VCC
00H
C2H
Device Code(3)
VIL
VIL
VH
VIH
0B
VCC
01H
12H
NOTES: 1. VH = 12.0V ± 0.5V
2. X = Either VIH or VIL
3. A1 - A8, A10 - A15 = VIL(For auto select)
P/N: PM0156
4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage conditions
only.
6
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
FIGURE 1. FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X=0
PROGRAM ONE 50us PULSE
INCREMENT X
INTERACTIVE
SECTION
YES
X = 25?
NO
FAIL
VERIFY WORD
?
PASS
NO
LAST ADDRESS
INCREMENT ADDRESS
FAIL
YES
VCC = VPP = 5.25V
VERIFY SECTION
VERIFY ALL WORDS
?
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0156
7
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance (30pF for 55/70ns parts)
SWITCHING TEST WAVEFORMS
2.0V
2.0V
TEST POINTS
AC driving levels
0.8V
0.8V
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V .
Input pulse rise and fall times are <20ns.
1.5V
AC driving levels
1.5V
TEST POINTS
OUTPUT
INPUT
AC TESTING: (1) AC driving levels are 3.0V/0V.
Input pulse rise and fall times are < 10ns.
(2) For MX27C1100/1024-55/70
P/N: PM0156
8
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
ABSOLUTE MAXIMUM RATINGS
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
RATING
VALUE
Ambient Operating Temperature
-40oC to 85oC
Storage Temperature
-65oC to 125oC
Applied Input Voltage
-0.5V to 7.0V
Applied Output Voltage
-0.5V to VCC + 0.5V
VCC to Ground Potential
-0.5V to 7.0V
A9 & Vpp
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are subject to
change.
DC/AC Operating Conditions for Read Operation
MX27C1100/1024
Operating Temperature
Commercial
-55*
-70
-85
-10
-12
-15
0°C to 55°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Industrial **
Vcc Power Supply
-40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
Vcc ± 5%
Vcc ± 10%
Vcc ± 10%
Vcc ± 10%
Vcc ± 10%
Vcc ± 10%
* : 55ns for MX27C1024 only
**:Industrial grade for MX27C1024 only
DC CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
MAX.
UNIT
CONDITIONS
V
IOH = -0.4mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VIN = 0 to 5.5V
ILO
Output Leakage Current
-10
10
uA
VOUT = 0 to 5.5V
ICC3
VCC Power-Down Current
100
uA
CE = VCC ± 0.3V
ICC2
VCC Standby Current
1.5
mA
CE = VIH
ICC1
VCC Active Current
40
mA
CE = VIL, f=5MHz, Iout = 0mA
IPP
VPP Supply Current Read
10
uA
CE = OE = VIL, VPP = 5.5V
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
CONDITIONS
CIN
Input Capacitance
8
12
pF
VIN = 0V
COUT
Output Capacitance
8
12
pF
VOUT = 0V
CVPP
VPP Capacitance
18
25
pF
VPP = 0V
P/N: PM0156
9
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
AC CHARACTERISTICS
27C1024-55
SYMBOL
PARAMETER
MIN.
tACC
Address to Output Delay
55
tCE
Chip Enable to Output Delay
55
tOE
Output Enable to Output Delay
30
tDF
OE High to Output Float,
tOH
Output Hold from Address,
0
27C1100/1024-70
MAX.
MIN.
20
0
MAX.
27C1100/1024-85
MAX.
UNIT
CONDITIONS
70
85
ns
CE = OE = VIL
70
85
ns
OE = VIL
35
40
ns
CE = VIL
25
ns
20
MIN.
0
or CE High to Output Float
0
0
0
ns
CE or OE which ever occurred first
*tBHA
BYTE Access Time
*tOHB
BYTE Output Hold Time
*tBHZ
BYTE Output Delay Time
*tBLZ
BYTE Output Set Time
70
0
85
0
70
10
ns
ns
70
10
ns
ns
* : for MX27C1100 only
AC CHARACTERISTICS
27C1100/1024-10
SYMBOL
PARAMETER
MIN.
tACC
Address to Output Delay
100
tCE
Chip Enable to Output Delay
100
tOE
Output Enable to Output Delay
45
tDF
OE High to Output Float,
tOH
Output Hold from Address,
0
MAX.
30
27C1100/1024-12
MIN.
0
MAX.
27C1100/1024-15
MAX.
UNIT
CONDITIONS
120
150
ns
CE = OE = VIL
120
150
ns
OE = VIL
50
65
ns
CE = VIL
50
ns
35
MIN.
0
or CE High to Output Float
0
0
0
ns
CE or OE which ever occurred first
*tBHA
BYTE Access Time
*tOHB
BYTE Output Hold Time
*tBHZ
BYTE Output Delay Time
*tBLZ
BYTE Output Set Time
100
120
0
0
70
10
ns
70
ns
0
70
10
150
10
ns
ns
* : for MX27C1100 only
P/N: PM0156
10
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC
SYMBOL
PARAMETER
MIN.
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
MAX.
UNIT
CONDITIONS
V
IOH = -0.40mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VH
A9 Auto Select Voltage
11.5
12.5
V
ICC3
VCC Supply Current (Program & Verify)
50
mA
IPP2
VPP Supply Current(Program)
30
mA
VCC1
Fast Programming Supply Voltage
6.00
6.50
V
VPP1
Fast Programming Voltage
12.5
13.0
V
MAX.
UNIT
VIN = 0 to 5.5V
CE = VIL, OE = VIH
AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C
SYMBOL
PARAMETER
MIN.
tAS
Address Setup Time
2.0
us
tOES
OE Setup Time
2.0
us
tDS
Data Setup Time
2.0
us
tAH
Address Hold Time
0
us
tDH
Data Hold Time
2.0
us
tDFP
Output Enable to Output Float Delay
0
tVPS
VPP Setup Time
2.0
tPW
PGM Program Pulse Width
95
tVCS
VCC Setup Time
2.0
us
tCES
CE Setup Time
2.0
us
tOE
Data valid from OE
P/N: PM0156
130
ns
us
105
150
11
CONDITIONS
us
ns
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
WAVEFORMS(MX27C1024)
READ CYCLE(WORD MODE)
ADDRESS
INPUTS
DATA ADDRESS
tACC
CE
tCE
OE
tDF
DATA
OUT
VALID DATA
tOE
tOH
FAST PROGRAMMING ALGORITHM WAVEFORMS
PROGRAM
PROGRAM VERIFY
VIH
Addresses
VIL
DATA
tAH
Hi-z
tAS
DATA OUT VALID
DATA IN STABLE
tDH
tDS
tDFP
VPP1
VPP
VCC
tVPS
VCC1
VCC
VCC
tVCS
VIH
CE
VIL
tCES
VIH
PGM
VIL
tPW
tOES
tOE
Max
VIH
OE
P/N: PM0156
VIL
12
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
WAVEFORMS(MX27C1100)
READ CYCLE(BYTE MODE)
A-1
HIGH-Z
HIGH-Z
tACC
tOH
BYTE/VPP
Q0-Q7
VALID DATA
VALID DATA
tBHA
tOHB
VALID DATA
Q15-Q8
tBHZ
tBLZ
FAST PROGRAMMING ALGORITHM WAVEFORM
VERIFY
PROGRAM
VIH
Addresses
VALID ADDRESS
VIL
tAH
tAS
DATA OUT VALID
DATA SET
DATA
tDS
tDFP
tDH
VPP1
BYTE/VPP
VCC
tVPS
VCC1
VCC
VCC
tVCS
VIH
CE
VIL
tPW
tOES
tOE
VIH
OE
P/N: PM0156
VIL
13
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
ORDER INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
PACKAGE
(ns)
MAX.(mA)
MAX.(uA)
MX27C1100PC-70
70
40
100
40 Pin DIP(ROM pin out)
MX27C1100PC-85
85
40
100
40 Pin DIP(ROM pin out)
MX27C1100PC-10
100
40
100
40 Pin DIP(ROM pin out)
MX27C1100PC-12
120
40
100
40 Pin DIP(ROM pin out)
MX27C1100PC-15
150
40
100
40 Pin DIP(ROM pin out)
MX27C1100MC-70
70
40
100
40 Pin SOP
MX27C1100MC-85
85
40
100
40 Pin SOP
MX27C1100MC-10
100
40
100
40 Pin SOP
MX27C1100MC-12
120
40
100
40 Pin SOP
MX27C1100MC-15
150
40
100
40 Pin SOP
MX27C1024PC-55
55
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024PC-70
70
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024PC-85
85
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024PC-10
100
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024PC-12
120
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024PC-15
150
40
100
40 Pin DIP(JEDEC pin out)
MX27C1024QC-55
55
40
100
44 Pin PLCC
MX27C1024QC-70
70
40
100
44 Pin PLCC
MX27C1024QC-85
85
40
100
44 Pin PLCC
MX27C1024QC-10
100
40
100
44 Pin PLCC
MX27C1024QC-12
120
40
100
44 Pin PLCC
MX27C1024QC-15
150
40
100
44 Pin PLCC
MX27C1024MC-55
55
40
100
40 Pin SOP
MX27C1024MC-70
70
40
100
40 Pin SOP
MX27C1024MC-85
85
40
100
40 Pin SOP
MX27C1024MC-10
100
40
100
40 Pin SOP
MX27C1024MC-12
120
40
100
40 Pin SOP
MX27C1024MC-15
150
40
100
40 Pin SOP
P/N: PM0156
14
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
PACKAGE INFORMATION
P/N: PM0156
15
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
P/N: PM0156
16
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
P/N: PM0156
17
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
REVISION HISTORY
Revision No. Description
3.0
Revise speed grade from 70/90/120/150ns to 55/70/85/100/
120/150ns.
Add 40 pin SOP package type.
4.0
1) Eliminate Interactive Programming Mode.
2) 40-CDIP package quartz lens, change to square shape.
4.1
IPP : 100uA ----> 10uA
4.2
Add industrial grade 70/85/100/120/150ns 40-TSOP(I)
4.3
Cancel ceramic DIP package type
4.4
Cancel "Ultraviolet Erasable" wording in General Description
To modify Package Information
4.5
To modify Package Information
4.6
1. To remove 10 x 14mm 40-TSOP package type.
2. To modify 40-PDIP package information
P/N: PM0156
18
Page
Date
10/15/1996
06/14/1997
P15
P1,2,4,15,16
P1
P15~18
P15~18
P1,2,14,18
P15
08/08/1997
11/19/1998
FEB/25/2000
AUG/20/2001
NOV/19/2002
JAN/14/2003
REV. 4.6, JAN. 14, 2003
MX27C1100/27C1024
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
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TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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