NXP GTL2002DC-T Nxp bidirectional low-voltage translator Datasheet

NXP bidirectional
low-voltage translators
GTL20xx
Low
cost bidirectional voltage
Headline
translation without directional control
Unlike level-shifting bus switches, which only translate between fixed voltages, these bidirectional
low-voltage translators can translate any voltage between 1 and 5 V to any other voltage between
1 and 5 V. They also reduce ON-state resistance and minimize propagation delay.
Key features
4 No directional control required for
bidirectional voltage translations
4 Low RON resistance (6.5 Ω) between
input and output pins (Sn/Dn)
4 Propagation delay: 1.5 ns (typ)
4 Channel off-state capacitance: 7.5 pF
4 Very low (5 µA) standby current
4 No power supply required – prevents
latch-ups
4 Very small QFN package options
Applications
4 Uni- and bidirectional translation for
any voltage between 1 and 5 V
4 Bidirectional translation of lowvoltage and legacy I2C-bus signals
4 Shifting processor sideband I/O
signals between GTL and LVTTL/TTL
levels
The NXP family of Gunning Transceiver
Logic (GTL) bidirectional low-voltage
translators includes the 22-bit GTL2000,
the 2-bit GTL2002, the 8-bit GTL2003,
and the 10-bit GTL2010.
Each delivers high-speed translation
between different voltage levels with
low ON-state resistance and minimal
propagation delay.
They can translate any voltage between
1 and 5 V to any other voltage between
1 and 5 V as long as there is at least 1 V
difference between the voltage levels, so
they offer greater design flexibility than
level-shifting bus switches, which only
translate between fixed voltages.
Each GTL20xx device includes NMOS
pass transistors (Sn and Dn pins) with a
common gate (GREF pin) and a reference
transistor (SREF and DREF pins).
When one of the Sn or Dn ports is low,
the clamp is in the ON-state and the Sn
and Dn ports are linked through a low
ON-resistance connection. Assuming the
higher voltage is applied on the Dn port,
when the Dn port is high, the voltage on
the Sn port is limited to the voltage set
by SREF. When the Sn port is high, the Dn
port is pulled to a higher voltage by a
pull-up resistor.
This set-up enables seamless translation
between user-selected voltages, without
the need for directional control signals.
All transistors have the same electrical
characteristics so deviation from one
output to another in voltage and
propagation delay is kept to a minimum.
The transistors also provide excellent
ESD protection in case the low-voltage
devices that are less resistant to ESD.
The translators can be used in any
The translators can also be used in
designs that combine GTL and LVTTL/
TTL signals, shifting processor sideband
I/O signals between voltage levels.
Bidirectional voltage translation
To configure the translators for
bidirectional clamping, the GREF input
must be connected to DREF and both
pins must be pulled to the high-side
VCC through a pull-up resistor (typically
200 kΩ). A filter capacitor on DREF is
recommended.
The CPU output can be set as totem
pole or open drain (pull-up resistors may
be required), as can the chipset output
(pull-up resistors are required to pull
the Dn outputs to VCC). No directional
control is needed if both outputs are set
as open drain. If either output is set to
totem pole, however, there may be highto-low contentions in either direction. To
prevent this, set data as unidirectional
or use 3-stateable outputs with a
mechanism for direction control.
The opposite side of SREF is connected
to the CPU power-supply voltage. When
DREF is connected through a 200-kΩ
resistor to VCC and SREF is set between 1.0
and VCC minus 1.5 V, the output of each
Sn has a maximum output voltage equal
to SREF and the output of each Dn has a
maximum output voltage equal to the
voltage of the pull-up resistor (3.3 and/or
5 V).
Unidirectional voltage translation
The same configuration can be used for
one-way voltage translation, either up
or down. For down-only translation, if
the chipset I/O are open drain, pull-up
resistors are required.
GND
1
48
GREF
SREF
2
47
DREF
3
46
D1
4
45
D2
S3
5
44
D3
S4
6
43
D4
S5
7
42
D5
S6
8
41
D6
S7
9
40
D7
39
D8
1.2 V
38
D9
1.0 V
37
D10
36
D11
35
D12
D13
S8 10
S9 11
S10 12
S11
13
S12
14
S13
15
34
S14
16
33
D14
S15
17
32
D15
S16
18
31
D16
S17
19
30
D17
S18
20
29
D18
S19
21
28
D19
S20
22
27
D20
S21
23
26
D21
S22 24
25
D22
For up-only translation, a pull-up resistor
is required on the high-side voltage (Dn).
This is because the translator will only
pass the reference source voltage (SREF)
as a high when doing up-translation. The
driver on the low-side voltage only needs
a pull-up resistor if it is set as open drain.
For more information on using the
GTL20xx family, please refer to
Application Note AN10145 at www.nxp.
com/interface.
GTL2002
S1
S2
GTL2000
application that requires uni- or
bidirectional voltage translation for
voltage levels between 1 and 5 V.
The open-drain construction, which
eliminates the need for directional
control, makes the translators ideal for
designs that combine low-voltage (1.0 to
1.8 V) and legacy (3.3 and/or 5.5 V) I2Cbus signals. The translators can change
I2C-bus signal levels at speeds up to 3.4
MHz.
GTL2003
GTL20xx pinout diagram
5V
1.8 V
GTL2010
1.5 V
Totem Pole or
Open Drain I/O
200 K7
GTL2002
VCORE
GND
GREF
S REF
D REF
S1
D1
S2
D2
CPU I/O
VCC
Chipset I/O
3.3 V
Increase bit size by using
8-bit GTL2003 or 10-bit
GTL2010 or 22-bit GTL2000
VCC
S3
D3
S4
D4
S5
D5
Sn
Dn
Chipset I/O
Typical configuration for bidirectional voltage translation
Ordering information
Package
SO
SSOP
TSSOP
HVQFN
DHVQFN
VSSOP
XQFN
Container
Tube
T&R
Tube
T&R
Tube
T&R
T&R
T&R
T&R
T&R
GTL2000
--GTL2000DL
GTL2000DL-T
GTL2000DGG
GTL2000DGG-T
-----
GTL2002
GTL2002D
GTL2002D-T
---GTL2002DP-T
--GTL2002DC-T
GTL2002GM-T
GTL2003
----GTL2003PW
GTL2003PW-T
-GTL2003BQ-T
---
GTL2010
----GTL2010PW
GTL2010PW-T
GTL2010BS-T
----
Note: In Europe and Asia, for tube orders, add “, 112” (e.g. GTL2010PW, 112), and for tape and
reel orders, replace “-T” with “, 118” (e.g. GTL2010PW, 118).
www.nxp.com
© 2007 NXP N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
Date of release: March 2007
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
Document order number: 9397 750 15911
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
Printed in the USA
does not convey nor imply any license under patent or other industrial or intellectual property rights.
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