SEMICONDUCTOR TECHNICAL DATA The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard voltage PECL signals and translates them to differential ECL output signals. • • • • • • MC100LVEL91 Supports Low Voltage Operation MC100LVEL91 Has 620ps Typical Propagation Delays MC100EL91 Supports Standard Voltage Operation MC100EL91 Has 670ps Typical Propagation Delays Fully Differential Design 20–lead SOIC Packaging A VBB output is provided for interfacing with single ended PECL signals at the input. If a single ended input is to be used the VBB output should be connected to the D input. The active signal would then drive the D input. When used the VBB output should be bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the EL/LVEL91 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current. To accomplish the level translation the EL/LVEL91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plain. Both VEE and VCC should be bypassed to ground via 0.01µF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability. VCC Q0 Q0 GND Q1 Q1 GND Q2 Q2 VCC 20 19 18 17 16 15 14 13 12 11 ECL PECL PECL PECL 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 D1 D1 PECL_VBB ECL PECL_VBB ECL D2 D2 VEE DW SUFFIX 20–LEAD PLASTIC SOIC WIDE PACKAGE CASE 751D–04 PIN NAMES Pins Function Dn Qn PECL_VBB PECL/LVPECL Inputs ECL/LVECL Outputs PECL Reference Voltage Output Figure 1. 20–Lead Pinout (Top View) and Logic Diagram 8/97 Motorola, Inc. 1997 4–1 REV 1 MC100LVEL91 MC100EL91 LVPECL INPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Max Min Max Min Typ Max Min Max Unit VCC Power Supply Voltage 3.0 3.6 3.0 3.6 3.0 3.3 3.6 3.0 3.6 V IIH Input HIGH Current 150 µA IIL Input LOW Current 0.5 VIH Input HIGH Voltage (Note 1.) 2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V VCC = 3.3V VIL Input LOW Voltage (Note 1.) 1.49 1.825 1.49 1.825 1.49 1.825 1.49 1.825 V VCC = 3.3V VBB Reference Output (Note 1.) 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V VCC = 3.3V 10 mA 150 IGND Power Supply Curremt 1. DC levels vary 1:1 with VCC. 150 0.5 150 0.5 10 10 µA 0.5 6.0 Condition 10 PECL INPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Max Min Max Min Typ Max Min Max Unit VCC Power Supply Voltage 4.75 5.25 4.75 5.25 4.75 5.0 5.25 4.75 5.25 V IIH Input HIGH Current 150 µA IIL Input LOW Current 0.5 VIH Input HIGH Voltage (Note 2.) 3.835 4.120 3.835 4.12 3.835 4.12 3.835 4.120 V VCC = 5.0V VIL Input LOW Voltage (Note 2.) 3.19 3.525 3.19 3.525 3.19 3.525 3.19 3.525 V VCC = 5.0V VBB Reference Output (Note 2.) 3.62 3.74 3.62 3.74 3.62 3.74 3.62 3.75 V VCC = 5.0V 11 mA 150 IGND Power Supply Curremt 2. DC levels vary 1:1 with VCC. 150 0.5 150 0.5 11 11 µA 0.5 6.0 Condition 11 ECL/LVECL OUTPUT DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Max Min Max Min Typ Max Min Max Unit VEE Power Supply EL91 Voltage LVEL91 –4.2 –3.0 –5.5 –3.8 –4.2 –3.0 –5.5 –3.8 –4.2 –3.0 –4.5 –3.3 –5.5 –3.8 –4.2 –3.0 –5.5 –3.8 V VOH Output HIGH Voltage –1085 –880 –1025 –880 –1025 –955 –880 –1025 –880 mV VOL Output LOW Volrage –1830 –1555 –1810 –1620 –1810 –1705 –1620 –1810 –1620 mV IEE Power Supply EL91 Current LVEL91 22 21 28 27 30 29 mA MOTOROLA 28 27 28 27 4–2 Condition ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL91 MC100EL91 MC100LVEL91 AC CHARACTERISTICS (VEE = –3.0V to –3.8V; VCC = 3.0V to 3.6V) –40°C Symbol Characteristic tPLH tPHL Propagation Delay D to Q Diff S.E. tSKEW Skew Output–to–Output (Note 3.) Part–to–Part (Diff) (Note 3.) Duty Cycle (Diff) (Note 4.) VPP Minimum Input Swing (Note 5.) VCMR Common Mode Range (Note 6.) VPP < 500mV VPP ≥ 500mV tr tf 3. 4. 5. 6. Output Rise/Fall Times Q (20% – 80%) 0°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit 490 440 590 590 690 740 510 460 610 610 710 760 520 470 620 620 720 770 560 510 660 660 760 810 ps 40 100 200 40 100 200 40 100 200 40 100 200 ps 25 25 200 25 200 25 200 200 mV V 1.3 1.5 320 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 VCC–0.2 400 580 ps Skews are valid across specified voltage range, part–to–part skew is for a given temperature. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak–to–peak voltage lies between VPPmin and 1V. MC100EL91 AC CHARACTERISTICS (VEE = –4.20V to –5.5V; VCC = 4.75V to 5.25V) –40°C Symbol 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max tPLH tPHL Propagation Delay D to Q (Note 11.) Diff S.E. 540 490 640 640 740 790 560 510 660 660 760 810 570 520 670 670 770 820 610 560 710 710 810 860 tSKEW Skew Output–to–Output (Note 7.) Part–to–Part (Diff) (Note 7.) Duty Cycle (Diff) (Note 8.) 40 100 200 40 100 200 40 100 200 40 100 200 VPP Minimum Input Swing (Note 9.) VCMR Common Mode Range (Note 10.) VPP < 500mV VPP ≥ 500mV tr tf Output Rise/Fall Times Q (20% – 80%) Unit ps ps 25 25 200 25 200 25 200 200 mV V 1.3 1.5 320 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 1.2 1.4 580 320 VCC–0.2 400 VCC–0.2 VCC–0.2 400 580 ps 7. Skews are valid across specified voltage range, part–to–part skew is for a given temperature. 8. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device. 9. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. 10. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak–to–peak voltage lies between VPPmin and 1V. 11. The MC100EL91 design has different propagation delays compared to the MC100LVEL91 due to differences in the translation structure. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVEL91 MC100EL91 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A – 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 1 –B – P 10 PL A B 0.010 (0.25) M B M 10 D 20 PL 0.010 (0.25) J M T S S F R X 45° C –T G K 18 PL SEATING – PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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