Intersil CD40208BMS Cmos 4 x 4 multiport register Datasheet

CD40208BMS
CMOS 4 x 4 Multiport Register
December 1992
Features
Description
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The CD40208BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
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High Voltage Types (20V Rating)
One Input and Two Output Buses
Unlimited Expansion in Bit and Word Directions
Data Lines have Latched Inputs
3-State Outputs
Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of any of Four Registers on Bus
A and Bus B and Independent Writing Into any of the
Four Registers
100% Tested for Quiescent Current at 20V
Standardized, Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC
Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Devices”
Applications
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in
a bus organized system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines independent of the state of the CLOCK input.
The CD40208BMS types are supplied in hermetic 24-lead
dual-in-line ceramic packages (D and F suffixes), 24-lead
dual-in-line plastic packages (E suffix), 24-lead ceramic flat
packages (K suffix), and in chip form (H suffix).
The CD40208BMS is supplied in these 24-lead outline packages:
Braze Seal DIP
Ceramic Flatpack
• Scratch Pad Memories
• Arithmetic Units
• Data Storage
HNZ
H4P
Functional Diagram
Pinout
CD40208BMS
TOP VIEW
Q3B
1
WRITE
ENABLE
15
24 VDD
Q2B
2
23 Q1B
ENABLE A
3
22 Q0B
Q0A
4
21 ENABLE B
Q1A
5
20 D0
Q2A
6
19 D1
Q3A
7
18 D2
WRITE 0
8
17 D3
D0
DATA
INPUTS
D1
D2
D3
WRITE 1
9
READ 0B 10
18
6
17
7
Q0
Q1
Q2
WORD A
OUTPUT
Q3
9
READ 1A
READ 1B
13 READ 0A
5
WRITE 1
15 WRITE ENABLE
VSS 12
4
19
WRITE 0
READ 0A
14 READ 1A
3
20
8
16 CLOCK
READ 1B 11
ENABLE A
READ 0B
22
14
23
13
2
1
11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1431
Q1
Q2
WORD B
OUTPUT
Q3
10
16
VDD = 24
VSS = 12
Q0
CLOCK
21
ENABLE B
File Number
3396
Specifications CD40208BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance
θja
θjc
Ceramic DIP and Frit Package . . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
SYMBOL
IDD
IIL
TEMPERATURE
MIN
MAX
1
+25oC
-
10
µA
2
+125oC
-
1000
µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
10
µA
VIN = VDD or GND
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
-
50
mV
VDD = 20V, VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
LIMITS
GROUP A
SUBGROUPS
CONDITIONS (NOTE 1)
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
UNITS
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25oC
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
-2.8
-0.7
V
0.7
2.8
V
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1
+25oC
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1
+25oC
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
Functional
F
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
Tri-State Output
Leakage
IOZL
VIN = VDD or GND
VOUT = 0V
IOZH
VIN = VDD or GND
VOUT = VDD
V
-55oC
+25oC,
Tri-State Output
Leakage
VOH > VOL <
VDD/2 VDD/2
+125oC, -55oC
-
1.5
V
+25oC, +125oC, -55oC
3.5
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
1
+25oC
-0.4
-
µA
2
+125oC
-12
-
µA
VDD = 18V
3
-55oC
-0.4
-
µA
VDD = 20V
1
+25oC
-
0.4
µA
2
+125oC
-
12
µA
3
-55oC
-
0.4
µA
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/NoGo test with limits applied to inputs.
7-1432
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD40208BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
Propagation Delay
Clock or Write Enable to Q
TPHL1
TPLH1
Propagation Delay
Read or Write Enable to Q
TPHL2
TPLH2
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
Propagation Delay
TPZH, HZ VDD = 5V, VIN = VDD or GND
3-State Disable Delay Time
(Notes 2, 3)
Propagation Delay
TPZL, LZ VDD = 5V, VIN = VDD or GND
3-State Disable Delay Time
(Notes 2, 3)
Transition Time
Maximum Clock Input
Frequency
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
720
ns
-
972
ns
-
600
ns
-
810
ns
-
200
ns
-
270
ns
-
260
ns
-
351
ns
-
200
ns
-
270
ns
1.5
-
MHz
1.11
-
MHz
MIN
MAX
UNITS
-
5
µA
-
150
µA
-
10
µA
-
300
µA
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
-55oC,
+25oC
+125oC
VDD = 15V, VIN = VDD or GND
1, 2
-
10
µA
+125oC
-
600
µA
-55oC,
+25oC
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL4
VDD = 4.5V, VOUT = 0.4V
1, 2
+125oC
-
-
mA
-55oC
-
-
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
IOL5
IOL10
IOL15
IOH5A
VDD = 5V, VOUT = 0.4V
1, 2
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
7-1433
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
Specifications CD40208BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
Output Current (Source)
Output Current (Source)
SYMBOL
IOH5B
IOH10
IOH15
CONDITIONS
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
+125oC
-
-2.4
mA
-55 C
-
-4.2
mA
+25oC, +125oC,
-
3
V
1, 2
1, 2
o
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
-55oC
Input Voltage High
VIH
Propagation Delay
Clock or Write Enable to Q
TPHL1
TPLH1
Propagation Delay
Read or Write Address to Q
TPHL2
TPLH2
Propagation Delay
Output Disable to Output
1, 2
+25oC, +125oC,
-55oC
+7
-
V
VDD = 10V
1, 2, 3
+25oC
-
280
ns
VDD = 15V
1, 2, 3
+25oC
-
200
ns
VDD = 10V
1, 2, 3
+25oC
-
240
ns
1, 2, 3
+25oC
-
170
ns
1, 2, 4
+25oC
-
120
ns
1, 2, 4
+25oC
-
100
ns
1, 2, 4
+25oC
-
100
ns
1, 2, 4
+25oC
-
80
ns
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 15V
TPZL, LZ VDD = 10V
VDD = 15V
Propagation Delay
TPZH, HZ VDD = 10V
Output Disable to Output
VDD = 15V
Minimum Write Enable to
Clock Setup Time
Minimum Data to Clock
Setup Time
TS (WE)
TS (D)
VDD = 5V
1, 2, 3
+25oC
-
250
ns
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
70
ns
1, 2, 3
+25oC
-
0
ns
1, 2, 3
+25oC
-
0
ns
1, 2, 3
+25oC
-
0
ns
1, 2, 3
+25oC
-
250
ns
1, 2, 3
+25oC
-
100
ns
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Write Address
to Clock Setup Time
Minimum Write Enable to
Clock Hold Time
TS (WA)
VDD = 5V
VDD = 10V
TH (WE)
VDD = 15V
1, 2, 3
+25oC
-
70
ns
VDD = 5V
1, 2, 3
+25oC
-
270
ns
VDD = 10V
1, 2, 3
+25oC
-
130
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
220
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
330
ns
VDD = 10V
1, 2, 3
+25oC
-
140
ns
VDD = 15V
1, 2, 3
+25oC
-
90
ns
VDD = 5V
1, 2, 3
+25oC
-
350
ns
1, 2, 3
+25oC
-
130
ns
1, 2, 3
+25oC
-
90
ns
1, 2, 3
+25oC
-
300
ns
1, 2, 3
+25oC
-
150
ns
1, 2, 3
+25oC
-
90
ns
VDD = 15V
Minimum Data to Clock
Hold Time
TH (D)
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Write Address
to Clock Hold Time
Minimum Clock Pulse
Width, Clock or Write Enable
TH (WA)
TW (CL)
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width, Write Address
TW (WA) VDD = 5V
VDD = 10V
VDD = 15V
7-1434
Specifications CD40208BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Maximum Clock Input
Frequency
FCL
Clock Rise and Fall Time
tRCL
tFCL
CONDITIONS
Input Capacitance
MAX
UNITS
VDD = 10V
1, 2, 3
3.5
-
MHz
1, 2, 3
+25oC
4.5
-
MHz
VDD = 5V
1, 2, 3
+25oC
-
15
µs
1, 2, 3
+25oC
-
5
µs
1, 2, 3
+25oC
-
5
µs
VDD = 10V
VDD = 15V
CIN
MIN
VDD = 15V
VDD = 10V
TTHL
TTLH
TEMPERATURE
+25oC
VDD = 15V
Transition Time
NOTES
Any Input
o
1, 2, 3
+25 C
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K., Input TR, TF < 20ns
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VNTH
P Threshold Voltage
P Threshold Voltage
Delta
CONDITIONS
NOTES
TEMPERATURE
MAX
UNITS
1, 4
+25 C
-
25
µA
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.2
V
VDD = 10V, ISS= -10µA
1, 4
+25 C
-
±1
V
VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
∆VPTH
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
o
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
MIN
VDD = 20V, VIN = VDD or GND
o
TPHL
TPLH
VDD = 5V
NOTES:
1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input tR, tF < 20ns.
3. See Table 2 for +25oC limit.
4. Read and Record.
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
7-1435
Specifications CD40208BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
1, 7, 9
100% 5004
1, 7, 9, Deltas
IDD, IOL5, IOH5A, RONDEL10
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group A
Group B
100% 5004
READ AND RECORD
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
(Note 1)
1, 2, 4-7, 22, 23
3, 8-21
24
Static Burn-In 2
(Note 1)
1, 2, 4-7, 22, 23
12
3, 8-11, 13-21, 24
12
3, 15, 16, 21, 24
12
3, 8-11, 13-21, 24
Dynamic BurnIn (Note 1)
Irradiation
(Note 2)
1, 2, 4-7, 22, 23
9V ± -0.5V
50kHz
25kHz
1, 2, 4-7, 22, 23
8, 10, 14, 19, 20
9, 11, 13, 17, 18
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Block Diagram
W0 W1 R0A R1A R0B R1B
CL
WE
DEC.
DEC.
D0
DATA
INPUTS
D1
D2
DEC.
ENABLE A
Q0A
Q1A
Q2A
Q3A
WORD A
OUTPUT
Q0B
Q1B
Q2B
Q3B
WORD B
OUTPUT
4X4
MEMORY
D3
ENABLE B
FIGURE 1.
7-1436
CD40208BMS
Logic Diagram
*
13 R0A
*
14 R1A
R0B 10
*
*
11 R1B
*
C
3
3-STATE
A ENABLE
C
16
*
CLOCK
15
* WRITE
4
Q0A
5
Q1A
6
Q2A
7
Q3A
ENABLE
8
*
W0
*
W1
A B
QA
D
QB
W
9
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
C
P
N
20
* D0
C
A B
QA
QB
W
C
P
N
C
A B
QA
QB
W
A B
QA
QB
W
D
D
22 Q0B
C
D1
C
C
P
N
C
D2
C
C
P
N
C
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
A B
QA
D
QB
W
* D3
C
2
Q2B
1
Q3B
C
P
N
17
23 Q1B
C
P
N
18
*
D
P
N
19
*
A B
QA
QB
W
D
*
21
B ENABLE
3-STATE
C
P
N
A
D
C
VDD = 24
VSS = 12
P
N
P
N
VDD
QA
VDD
P
N
B
W
P
N
INPUT
QB
VSS
VSS
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
OUTPUT
DETAIL OF
MEMORY CELL
FIGURE 2.
7-1437
DETAIL OF
3-STATE OUTPUTS
CD40208BMS
TRUTH TABLE
WRITE
CLOCK ENABLE
X
X
WRITE
1
WRITE
0
READ
1A
READ
0A
READ
1B
READ
0B
ENABLE ENABLE
A
B
1
S1
S2
S1
S2
S1
S2
1
1
1
1
1
1
S1
S2
S1
S2
S1
S2
1
1
0
0
0
X
X
X
X
X
X
X
0
0
X
Z
Z
1
0
0
0
1
1
0
1
1
Dn to
Word 0
Word 1
Out
Word 2
Out
0
0
0
0
1
1
0
1
1
Word 0
Not
Altered
Word 1
Out
Word 2
Out
X
X
X
1
0
0
1
1
1
X
Word 2
Out
Word 1
Out
X
X
X
X
X
X
X
1
1
X
NC
NC
Dn
QnA
QnB
1 = High Level; 0 = Low Level; X = Don’t Care; Z = High Impedance
NOTE: S1 and S2 refer to input states of either 1 or 0.
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-15
-20
-25
-15V
10.0
10V
7.5
5.0
2.5
5V
5
10
15
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-10
-10V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-30
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
15.0
0
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-15V
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
30
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1438
CD40208BMS
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
525
TRANSITION TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (LtPLH, tPHL) (ns)
Typical Performance Characteristics
450
SUPPLY VOLTAGE (VDD) = 5V
375
300
225
10V
150
5V
75
0
0
10
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
90
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
15V
50
0
0
100
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CL OR WE TO Q)
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
106
POWER DISSIPATION (PD) (µW)
SUPPLY VOLTAGE (VDD) = 15V
105
10V
5V
10V
104
CL = 50pF
CL = 15pF
103
AMBIENT TEMPERATURE (TA) = +25oC
102
1
10
102
103
INPUT FREQUENCY (fI) (kHz)
104
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
trCL
tfCL
tW(CL)
CL
tH(D)
tS(D)
Dn
tH(WE)
tS(WE)
WE
tH(WA)
tS(WA)
tW(WA)
WA
RA
tPLH
tPHL
tPHL
Qn
tTLH
tTHL
FIGURE 10. TIMING DIAGRAM
7-1439
tPLH
tPHL
tPLH
CD40208BMS
0.1µF
VDD
500µF
ID
CL
CL
CL
CL
CL
CL
PULSE GEN. 3
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
(fI)
P.G. 1
CL
CL
P.G. 2
P.G. 3
PULSE GEN. 2
Qn A, B
PULSE GEN. 1
REPETITIVE WAVEFORMS
FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS
VDD
CL
P.G. 1
Q
1kΩ
TO ANY
OUTPUT
50pF
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
PULSE GEN. 2
ENABLE
P.G. 2
ENABLE
INPUT
D
VDD
50%
50%
tPLZ
Q
OUTPUTS
PULSE GEN. 1
CHAR
tPHZ
tPZH
tPLZ
tPZL
TEST VOLTAGE
AT D
AT Q
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
10%
90%
tPHZ
FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS
7-1440
VSS
tPZL
90%
VDD
VOL
VOH
10%
tPZH
VSS
CD40208BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ, AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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