BELLING BLV7002 Blv7002 Datasheet

BLV7002
BLV7002 N-channel Enhancement Mode
Vertical D-MOS Transistor Chip
Description
N-channel enhancement mode field-effect transistor
Features
Very fast switching
Logic level compatible
Applications
Relay driver
High speed line driver
Logic level translator.
Size
Chip size: 495µm ×490µm
structure
Chip thickness: 220±20µm.
Planar type
Electrodes: Aluminum alloy
Backside metal: Au alloy
Scribe street width: 50µm
Pad size: 90µm x90µm
Die per wafer: 25800
ABSOLUTE MAXIMUM RATING
Symbol
VDS
VGS
ID
IDM
Ptot
TSTG
Tj
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Parameter
Drain – source voltage (DC)
Gate – source voltage (DC)
Drain current (DC)
Peak drain current
Total power dissipation
Storage temperature
Junction temperature
-1Total 2 Pages
Min.
-55
-
Max.
60
±20
115
0.46
0.2
+150
150
Unit
V
V
mA
A
W
o
C
o
C
8/18/2006
BLV7002
CHARACTERISTICS
Tj = 25oC unless otherwise specified
Parameter
Symbol
Test conditions
Min.
BVDSS Drain-source breakdown voltage VGS=0V,ID=250µ A
60
IDSS
Drain-source leakage current
VDS=60V, VGS=0V
I GSS
Gate-source leakage current VGS=+20V, VDS=0V
VGSth
Gate-source threshold voltage VDS=2.5V, ID=250uA
1
RDSon Drain-source on-state resistance VGS=10V,ID=100mA
Ciss
Input capacitance
VDS=25V,VGS=0V
Coss
Output capacitance
f =1MHz
Crss
Reverse transfer capacitance
ton
Turn-On time
VDD=30V, ID=200mA
VGS=0-10V
toff
Turn-Off time
-
Typ.
73
1
1
1.3
-
Max.
500
±100
2.5
5
50
25
5
30
Unit
V
nA
nA
V
Ω
pF
pF
pF
ns
-
30
ns
PATTERN DRAWING
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-2Total 2 Pages
8/18/2006
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