ACTS240T Data Sheet July 1999 High Reliability, Radiation Hardened Octal Buffer/Line Driver, Three-State, Inverting Intersil‘s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil ACTS240T is a Radiation Hardened High Reliability, High-Speed CMOS/SOS Octal Buffer/Line Driver with three-state outputs having two active low enable inputs. Each enable input controls a set of four inverting buffer/line drivers. A HIGH on the enable input places the outputs in a high impedance state. Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. • QML Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) - SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm2/mg • 1.25 Micron Radiation Hardened SOS CMOS • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range . . . . . . . . . . . . 4.5V to 5.5V • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min • Fast Propagation Delay . . . . . . . 17.5ns (Max), 12ns (Typ) Pinouts ACTS240T (SBDIP), CDIP2-T20 TOP VIEW Intersil‘s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information PART NUMBER TEMP. RANGE (oC) 5962R9671701TRC ACTS240DTR -55 to 125 5962R9671701TXC ACTS240KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 1 4610.1 Features Detailed Electrical Specifications for the ACTS240T are contained in SMD 5962-96717. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp ORDERING NUMBER File Number AEN 1 AI1 2 19 BEN BO4 3 18 AO1 AI2 4 17 BI4 BO3 5 16 AO2 AI3 6 15 BI3 BO2 7 14 AO3 AI4 8 13 BI2 BO1 9 12 AO4 20 VCC GND 10 11 BI1 ACTS240T (FLATPACK), CDFP4-F20 TOP VIEW AEN 1 20 VCC AI1 2 19 BEN BO4 3 18 AO1 AI2 4 17 BI4 BO3 5 16 AO2 AI3 6 15 BI3 BO2 7 14 AO3 AI4 8 13 BI2 BO1 9 12 AO4 GND 10 11 BI1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 ACTS240T Functional Diagram NOTE: (1 of 2) AE 1(19) P AO1 N 18(9) AI1 2(11) P AO2 N 16(7) AI2 4(13) P AO3 N 14(5) AI3 6(15) P AO4 N 12(3) AI4 8(17) TRUTH TABLE INPUTS OUTPUT AE, BE AIn, BIn AOn, BOn L L H L H L H X Z NOTE: H = High Voltage Level, L = Low Voltage Level, X = Immaterial, Z = High Impedance 2 ACTS240T Die Characteristics BACKSIDE FINISH: DIE DIMENSIONS: (2540µm x 2540µm x 533µm ±51µm) 100 x 100 x 21mils ±2mil Sapphire PASSIVATION: METALLIZATION: Type: Silox (SiO2) Thickness: 8.0kÅ ±1.0kÅ Type: Al Si Cu Thickness: 10.0kÅ ±2kÅ WORST CASE CURRENT DENSITY: SUBSTRATE POTENTIAL: < 2.0e5 A/cm2 Unbiased (Silicon on Sapphire) Bond Pad #20 (VCC) First Bond Pad #10 (Gnd) Uses Two Bond Wires Bond Pad #20 (VCC) Uses Two Bond Wires TRANSISTOR COUNT: 164 PROCESS: CMOS SOS Metallization Mask Layout ACTS240T AI1 (2) VCC (20) AEN (1) VCC (20) BEN (19) (18) AO1 BO4 (3) (17) BI4 AI2 (4) (16) AO2 BO3 (5) (15) BI3 AI3 (6) (14) AO3 BO2 (7) (13) BI2 AI4 (8) BO1 (9) AO4 (12) (10) (10) GND GND (11) BI1 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3