NSC ADC0819 8-bit serial i/o a/d converter with 19-channel multiplexer Datasheet

ADC0819
8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer
General Description
The ADC0819 is an 8-Bit successive approximation A/D converter with simultaneous serial I/O. The serial input controls
an analog multiplexer which selects from 19 input channels
or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive reference ladder and sampled data comparator. This allows the
input signal to vary during the conversion cycle.
Separate serial I/O and conversion clock inputs are provided
to facilitate the interface to various microprocessors.
Features
■ Separate asynchronous converter clock and serial data I/
O clock
■ 19-Channel multiplexer with 5-Bit serial address logic
■
■
■
■
■
■
■
Built-in sample and hold function
Ratiometric or absolute voltage referencing
No zero or full-scale adjust required
Internally addressable test voltage
0V to 5V input range with single 5V power supply
TTL/MOS input/output compatible
28-pin molded chip carrier or 28-pin molded DIP
Key Specifications
■
■
■
■
■
Resolution: 8-Bits
Total unadjusted error: ± ½ LSB and ± 1 LSB
Single supply: 5 VDC
Low Power: 15 mW
Conversion Time: 16 μs
Connection Diagrams
Molded Chip Carrier (PCC) Package
Dual-In-Line Package
928701
Top View
Order Number ADC0819BCV, CCV
See NS Package Number V28A
928720
Top View
Order Number ADC0819BCN, CIN
See NS Package Number N28B
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
9287
9287 Version 2 Revision 4
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Print Date/Time: 2009/08/26 15:48:51
ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer
OBSOLETE
September 26, 2009
ADC0819
Functional Diagram
928702
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If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
215°C
220°C
2000V
Operating Ratings
Supply Voltage (VCC)
6.5V
Voltage
Inputs and Outputs
−0.3V to VCC +0.3V
Input Current Per Pin (Note 2)
±5mA
Total Package Input Current (Note 2)
±20mA
Storage Temperature
−65°C to +150°C
Package Dissipation at TA=25°C
875 mW
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic)
260°C
Surface Mount Package
(Notes 1, 2)
Supply Voltage (VCC)
Temperature Range
4.5 VDC to 6.0 VDC
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°
C
ADC0819BCV, ADC0819CCV
0°C ≤ TA ≤ +70°C
ADC0819BCN
−40°C ≤ TA ≤ +85°
C
ADC0819CIN
Electrical Characteristics
The following specifications apply for VCC = 5V, VREF = 5V, φ2 CLK = 2.097 MHz unless otherwise specified. Boldface limits apply
from TMIN to TMAX; all other limits TA = TJ = 25°C.
Parameter
Typical
(Note 6)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
±½
±1
±½
±1
LSB
5
kΩ
11
kΩ
V
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADC0819BCV, BCN
VREF=5.00 VDC
(Note 4)
ADC0819CCV, CIN
Minimum Reference Input Resistance
8
Maximum Reference Input
Resistance
8
Maximum Analog Input Range
(Note 5)
11
LSB
VCC+0.05
VCC+0.05
GND−0.05
GND−0.05
V
(Note 9)
On Channel=5V
Off Channel=0V
400
1000
nA
On Channel=0V
Off Channel=5V
(Note 9)
−400
−1000
nA
(Note 9)
On Channel=5V
Off Channel=0V
−400
−1000
nA
On Channel=0V
Off Channel=5V
(Note 9)
400
1000
nA
Minimum VTEST
VREF=VCC,
125
125
(Note 10)
Internal Test Voltage
CH 19 Selected
Maximum VTEST
VREF=VCC,
130
130
(Note 10)
Internal Test Voltage
CH 19 Selected
Minimum Analog Input Range
On Channel Leakage Current
Off Channel Leakage Current
Counts
Counts
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input Voltage (Min) VCC=5.25V
VIN(0), Logical “0” Input Voltage (Max) VCC=4.75V
2.0
2.0
V
0.8
0.8
V
IIN(1), Logical “1” Input Current (Max)
VIN=5.0V
0.005
2.5
2.5
μA
IIN(0), Logical “0” Input Current (Max)
VIN=0V
−0.005
−2.5
−2.5
μA
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ADC0819
Vapor Phase (60 sec.)
Infrared (15 sec.)
ESD Susceptibility (Note 11)
Absolute Maximum Ratings (Notes 1, 2)
ADC0819
Parameter
Typical
(Note 6)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
VOUT(1), Logical “1”
VCC=4.75V
Output Voltage (Min)
IOUT=−360 μA
2.4
2.4
V
IOUT=−10 μA
4.5
4.5
V
VOUT(0), Logical “0”
VCC=5.25V
0.4
0.4
V
Output Voltage (Max)
IOUT=1.6 mA
IOUT, TRI-STATE®Output Current
(Max)
VOUT=0V
−0.01
−3
−3
μA
VOUT=5V
0.01
3
3
μA
ISOURCE, Output Source Current (Min) VOUT=0V
−14
−6.5
−6.5
mA
ISINK, Output Sink Current (Min)
VOUT=VCC
16
8.0
8.0
mA
ICC, Supply Current (Max)
CS =1, VREF Open
1
2.5
2.5
mA
IREF (Max)
VREF=5V
0.7
1
1
mA
AC Characteristics
The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF = 5V, unless otherwise specified. Boldface limits apply from
TMIN to TMAX; all other limits TA = TJ = 25°C.
Parameter
Typical
(Note 6)
Conditions
φ2 CLK, φ2 Clock
MIN
0.70
Frequency
MAX
4.0
SCLK, Serial Data
Clock Frequency
MIN
MAX
TC, Conversion
Process Time
MIN Not Including MUX Addressing and Analog
MAX Input Sampling Times
tACC, Access Time
Delay From CS
Falling Edge to DO
Data Valid
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
1.0
2.0
2.1
5.0
1000
525
525
26
26
32
32
MIN
1
MAX
3
tSET-UP, Minimum Set-up
Time of CS Falling Edge to
SCLK Rising Edge
MHz
KHz
φ2 cycles
φ2 cycles
sec
tHCS, CS Hold Time After the
Falling Edge of SCLK
tCS, Total CS Low
Time
Units
0
ns
MIN
tset-up+8/SCLK
sec
MAX
tCS(min)+26/φ2CLK
sec
0
ns
10
ns
400
ns
tHDI, Minimum DI Hold Time
from SCLK Rising Edge
0
tHDO, Minimum DO Hold
RL=30k,
Time from SCLK Falling Edge CL=100 pF
tSDI, Minimum DI Set-up
Time to SCLK Rising Edge
200
tDDO, Maximum Delay From RL=30k,
SCLK Falling Edge to DO
CL=100 pF
Data Valid
180
200
250
ns
tTRI, Maximum DO Hold
Time, (CS Rising Edge to
DO TRI-STATE)
90
150
150
ns
RL=3k,
CL=100 pF
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Typical
(Note 6)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
3/SCLK+1 μs
sec
tCA, Analog
After Address Is Latched
Sampling Time
CS = Low
tRDO, Maximum DO Rise
Time
RL=30 kΩ,
“TRI-STATE” to “HIGH” State
75
150
150
CL=100 pF
“LOW” to “HIGH” State
150
300
300
tFDO, Maximum DO Fall
Time
RL=30 kΩ,
“TRI-STATE” to “LOW” State
75
150
150
CL=100 pF
“HIGH” to “LOW” State
150
300
300
CIN, Maximum Input
Analog Inputs, ANO–AN10 and VREF
11
55
Capacitance
All Others
5
15
ns
ns
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Under over voltage conditions (VIN<0V and VIN>VCC) the maximum input current at any one pin is ±5 mA. If the voltage at more than one pin exceeds
VCC + .3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level
of ±5 mA is four.
Note 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than VCC supply. Be careful during testing at low VCClevels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range
will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 6: Typicals are at 25°C and represent most likely parametric norm.
Note 7: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 9: Channel leakage current is measured after the channel selection.
Note 10: 1 count = VREF/256.
Note 11: Human body model; 100 pF discharged through a 1.5 kΩ resistor.
Test Circuits
Leakage Current
D0 Except “TRI-STATE”
928704
928703
tTRI “TRI-STATE”
928705
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ADC0819
Parameter
ADC0819
Data Input and Output Timing
Timing Diagrams
D0 “TRI-STATE” Rise & Fall Times
928706
D0 Low to High State
928709
928707
D0 High to Low State
928708
Timing with a continuous SCLK
928710
Strobing CS High and Low will abort the present conversion and initiate a new serial I/O exchange.
Timing with a gated SCLK and CS Continuously Low
928711
Using CS To TRI-STATE D0
928712
Strobing CS Low during this time interval will abort the conversion in process.
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ADC0819
CS High During Conversion
928713
CS Low During Conversion
928714
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ADC0819
Channel Addressing Table
TABLE 1. ADC 0819 Channel Addressing
A7
A6
A5
MUX ADDRESS
A4
A3
A2
A1
A0
ANALOG
CHANNEL
SELECTED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
VTEST
1
1
1
1
1
0
0
0
0
1
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Channel Select
No Channel Select
No Channel Select
No Channel Select
Logic Test Mode
(Note 12)
Note 12: Analog channel inputs CH0 thru CH4 are logic outputs
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ADC0819
928715
Functional Block Diagram
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ADC0819
The following seven falling edges of SCLK shift out this data
on DO.
The 8th SCLK falling edge initiates the beginning of the A/D's
>actual conversion process which takes between 26 and 32
φ2 cycles (TC). During this time CS can go high to TRI-STATE
DO and disable the SCLK input or it can remain low. If CS is
held low a new I/O exchange will not start until the conversion
sequence has been completed, however once the conversion
ends serial I/O will immediately begin. Since there is an ambiguity in the conversion time (TC) synchronizing the data
exchange is impossible. Therefore CS should go high before
the 26th φ2 clock has elasped and return low after the 32nd
φ2 to synchronize serial communication.
A conversion or I/O operation can be aborted at any time by
strobing CS . If CS is high or low less than one φ2 clock it will
be ignored by the A/D. If the CS is strobed high or low between
1 to 3 φ2 clocks the A/D may or may not respond. Therefore
CS must be strobed high or low greater than 3 φ2 clocks to
ensure recognition. If a conversion or I/O exchange is aborted
while in process the consequent data output will be erroneous
until a complete conversion sequence has been implemented.
Functional Description
1.0 DIGITAL INTERFACE
The ADC0819 uses five input/output pins to implement the
serial interface. Taking chip select (CS ) low enables the I/O
data lines (DO and DI) and the serial clock input (SCLK). The
result of the last conversion is transmitted by the A/D on the
DO line, while simultaneously the DI line receives the address
data that selects the mux channel for the next conversion. The
mux address is shifted in on the rising edge of SCLK and the
conversion data is shifted out on the falling edge. It takes eight
SCLK cycles to complete the serial I/O. A second clock (φ2)
controls the SAR during the conversion process and must be
continuously enabled.
1.1 CONTINUOUS SCLK
With a continuous SCLK input CS must be used to synchronize
the serial data exchange (Figure 1). The ADC0819 recognizes a valid CS one to three φ2 clock periods after the actual
falling edge of CS . This is implemented to ensure noise immunity of the CS signal. Any spikes on CS less than one φ2
clock period will be ignored. CS must remain low during the
complete I/O exchange which takes eight SCLK cycles. Although CS is not immediately acknowledged for the purpose
of starting a new conversion, the falling edge of CS immediately enables DO to output the MSB (D7) of the previous
conversion.
The first SCLK rising edge will be acknowledged after a setup
time (tset-up) has elapsed from the falling edge of CS . This and
the following seven SCLK rising edges will shift in the channel
address for the analog multiplexer. Since there are 19 channels only five address bits are utilized. The first five SCLK
cycles clock in the mux address, during the next three SCLK
cycles the analog input is selected and sampled. During this
mux address/sample cycle, data from the last conversion is
also clocked out on DO. Since D7 was clocked out on the
falling edge of CS only data bits D6–D0 remain to be received.
1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its 8th
falling edge (Figure 2). SCLK must remain low for at least 32
φ2 clocks to ensure that the A/D has completed its conversion.
If SCLK is enabled sooner, synchronizing to the data output on
DO is not possible since an end of conversion signal from the
A/D is not available and the actual conversion time is not
known. With CS low during the conversion time (32 φ2 max)
DO will go high or low after the eighth falling edge of SCLK until
the conversion is completed. Once the conversion is through
DO will transmit the MSB. The rest of the data will be shifted
out once SCLK is enabled as discussed previously.
928716
FIGURE 1.
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ADC0819
928717
FIGURE 2.
If CS goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains
high until the end of the conversion.
pacitance to settle to the analog input voltage. Any change in
the analog voltage before or after the acquisition window will
not effect the A/D conversion result.
In the most simple case, the ladder's acquisition time is determined by the Ron (3K) of the multiplexer switches and the
total ladder capacitance (90 pF). These values yield an acquisition time of about 2 μsec for a full scale reading. Therefore the analog input must be stable for at least 2 μsec before
and 1 μsec after the eighth SCLK falling edge to ensure a
proper conversion. External input source resistance and capacitance will lengthen the acquisition time and should be
accounted for.
Other conventional sample and hold error specifications are
included in the error and timing specs of the A/D. The hold
step and gain error sample/hold specs are taken into account
in the ADC0819's total unadjusted error, while the hold settling time is included in the A/D's max conversion time of 32
φ2 clock periods. The hold droop rate can be thought of as
being zero since an unlimited amount of time can pass between a conversion and the reading of data. However, once
the data is read it is lost and another conversion is started.
1.2 MULTIPLEXER ADDRESSING
The five bit mux address is shifted, MSB first, into DI. Input
data corresponds to the channel selected as shown in Table
1. Care should be taken not to send an address greater than
or equal to twenty four (11XXX) as this puts the A/D in a digital
testing mode. In this mode the analog inputs CH0 thru CH4
become digital outputs, for our use in production testing.
2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD
The ADC0819's sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 μsec after the
eighth SCLK falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
3tSCLK+1 μsec is therefore available to allow the ladder ca-
Typical Applications
ADC0819-INS8048 INTERFACE
928718
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ADC0819
ADC0819 FUNCTIONAL CIRCUIT
928719
Ordering Information
Temperature Range
Total Unadjusted
Error
±½ LSB
0°C to +70°C
ADC0819BCN
±1 LSB
Package Outline
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N28B
−40°C to +85°C
ADC0819BCV
ADC0819CCV
ADC0819CIN
V28A
N28B
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ADC0819
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number ADC0819BCN or ADC0819CIN
NS Package Number N28B
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ADC0819
Molded Chip Carrier (V)
Order Number ADC0819BCV, CCV
NS Package Number V28A
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ADC0819
Notes
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ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer
Notes
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