Renesas HM628100LTTI-5SL Wide temperature range version 8 m sram (1024-kword x 8-bit) Datasheet

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HM628100I Series
Wide Temperature Range Version
8 M SRAM (1024-kword × 8-bit)
ADE-203-1302B (Z)
Rev. 1.0
Sep. 25, 2002
Description
The Hitachi HM628100I Series is 8-Mbit static RAM organized 1,048,576-word × 8-bit. HM628100I Series
has realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable
for battery backup systems. It is packaged in standard 44-pin TSOP II for high density surface mounting.
Features
•
•
•
•
•
•
•
•
Single 5.0 V supply: 5.0 V ± 10 %
Fast access time: 55 ns (max)
Power dissipation:
 Active: 10 mW/MHz (typ)
 Standby: 7.5 µW (typ)
Completely static memory.
 No clock or timing strobe required
Equal access and cycle times
Common data input and output.
 Three state output
Battery backup operation.
 2 chip selection for battery backup
Temperature range: –40 to +85°C
HM628100I Series
Ordering Information
Type No.
Access time
Package
HM628100LTTI-5SL
55 ns
400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE)
2
HM628100I Series
Pin Arrangement
44-pin TSOP
A4
A3
A2
A1
A0
CS1
NC
NC
I/O0
I/O1
VCC
VSS
I/O2
I/O3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
NC
NC
I/O7
I/O6
VSS
VCC
I/O5
I/O4
NC
NC
A9
A10
A11
A12
A13
A14
(Top view)
Pin Description (TSOP)
Pin name
Function
A0 to A19
Address input
I/O0 to I/O7
Data input/output
CS1
Chip select 1
CS2
Chip select 2
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
3
HM628100I Series
Block Diagram (TSOP)
LSB
A5
A6
A7
A4
A3
A9
A10
A11
A12
A13
MSB A14
V CC
V SS
•
•
•
•
•
Row
decoder
I/O0
Memory matrix
2,048 x 4,096
Column I/O
•
•
Input
data
control
Column decoder
I/O7
LSB
MSB
A16 A17A18 A19 A0 A1 A2 A15A8
•
•
CS2
CS1
Control logic
WE
OE
4
•
•
HM628100I Series
Operation Table
CS1
CS2
WE
OE
I/O0 to I/O7
Operation
H
×
×
×
High-Z
Standby
×
L
×
×
High-Z
Standby
L
H
H
L
Dout
Read
L
H
L
×
Din
Write
L
H
H
H
High-Z
Output disable
Note: H: V IH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to V SS
VCC
–0.5 to + 7.0
1
V
2
Terminal voltage on any pin relative to V SS
VT
–0.5* to V CC + 0.3*
V
Power dissipation
PT
1.0
W
Storage temperature range
Tstg
–55 to +125
°C
Storage temperature range under bias
Tbias
–40 to +85
°C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +7.0 V.
DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input high voltage
VIH
2.2
—
VCC + 0.3
V
Input low voltage
VIL
–0.3
—
0.8
V
Ambient temperature range
Ta
–40
—
85
°C
Note:
Note
1
1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
5
HM628100I Series
DC Characteristics
Parameter
Symbol Min
Typ* 1 Max
Unit
Test conditions
Input leakage current
|ILI|
—
—
1
µA
Vin = VSS to V CC
Output leakage current
|ILO |
—
—
1
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL, or
VI/O = VSS to V CC
Operating current
I CC
—
—
20
mA
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL, I I/O = 0 mA
Average operating current
I CC1
—
14
25
mA
Min. cycle, duty = 100%,
I I/O = 0 mA, CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
I CC2
—
2
4
mA
Cycle time = 1 µs, duty = 100%,
I I/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ V CC – 0.2 V
VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V
Standby current
I SB
—
0.1
0.3
mA
CS2 = VIL
Standby current
I SB1
—
0.8
10
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ V CC – 0.2 V,
CS2 ≥ V CC – 0.2 V
Output high voltage
VOH
2.4
—
—
V
I OH = –1 mA
Output low voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
Note:
1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Note
Input capacitance
Cin
—
—
8
pF
Vin = 0 V
1
Input/output capacitance
CI/O
—
—
10
pF
VI/O = 0 V
1
Note:
6
1. This parameter is sampled and not 100% tested.
HM628100I Series
AC Characteristics (Ta = –40 to +85°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: VIL = 0.4 V, VIH = 2.2 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: 1 TTL Gate + C L (50 pF) (Including scope and jig)
Read Cycle
HM628100I
-5
Parameter
Symbol
Min
Max
Unit
Read cycle time
t RC
55
—
ns
Address access time
t AA
—
55
ns
Chip select access time
t ACS1
—
55
ns
t ACS2
—
55
ns
Output enable to output valid
t OE
—
35
ns
Output hold from address change
t OH
10
—
ns
Chip select to output in low-Z
t CLZ1
10
—
ns
2, 3
t CLZ2
10
—
ns
2, 3
Output enable to output in low-Z
t OLZ
5
—
ns
2, 3
Chip deselect to output in high-Z
t CHZ1
0
20
ns
1, 2, 3
t CHZ2
0
20
ns
1, 2, 3
t OHZ
0
20
ns
1, 2, 3
Output disable to output in high-Z
Notes
7
HM628100I Series
Write Cycle
HM628100I
-5
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t WC
55
—
ns
Address valid to end of write
t AW
50
—
ns
Chip selection to end of write
t CW
50
—
ns
5
Write pulse width
t WP
40
—
ns
4
Address setup time
t AS
0
—
ns
6
Write recovery time
t WR
0
—
ns
7
Data to write time overlap
t DW
25
—
ns
Data hold from write time
t DH
0
—
ns
Output active from end of write
t OW
5
—
ns
2
Output disable to output in high-Z
t OHZ
0
20
ns
1, 2
Write to output in high-Z
t WHZ
0
20
ns
1, 2
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest
transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest
transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the
beginning of write to the end of write.
5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. t AS is measured from the address valid to the beginning of write.
7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
8
HM628100I Series
Timing Waveform
Read Cycle
t RC
Address
Valid address
tAA
tACS1
CS1
tCLZ1*2, 3
CS2
tCHZ1*1, 2, 3
tACS2
tCLZ2*2, 3
tCHZ2*1, 2, 3
tOHZ*1, 2, 3
tOE
OE
tOLZ*2, 3
Dout
High impedance
tOH
Valid data
9
HM628100I Series
Write Cycle (1) (WE Clock)
tWC
Valid address
Address
tWR*7
tCW*5
CS1
tCW*5
CS2
tAW
tWP*4
WE
tAS*6
tDW
tDH
Valid data
Din
tWHZ*1, 2
tOW*2
High impedance
Dout
10
HM628100I Series
Write Cycle (2) (CS Clock, OE = VIH)
tWC
Valid address
Address
tAW
tAS*6
tWR*7
tCW*5
CS1
tCW*5
CS2
tWP*4
WE
tDW
tDH
Valid data
Din
High impedance
Dout
11
HM628100I Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ* 2
Max
Unit
Test conditions*1
VCC for data retention
VDR
2.0
—
—
V
Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V
CS1 ≥ V CC – 0.2 V
Data retention current
I CCDR
—
0.8
10
µA
VCC = 3.0 V, Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ V CC – 0.2 V,
CS1 ≥ V CC – 0.2 V
Chip deselect to data
retention time
t CDR
0
—
—
ns
See retention waveform
Operation recovery time
tR
t RC* 3
—
—
ns
Notes: 1. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1
controls data retention mode, CS2 must be CS2 ≥ V CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other
input levels (address, WE, OE, I/O) can be in the high impedance state.
2. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.
3. t RC = read cycle time.
12
HM628100I Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR
Data retention mode
tR
VCC
4.5 V
2.2 V
VDR
CS1
0V
CS1 ≥ VCC – 0.2 V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR
Data retention mode
tR
VCC
4.5 V
CS2
VDR
0.8 V
0 V < CS2 < 0.2 V
0V
13
HM628100I Series
Package Dimensions
HM628100LTTI Series (TTP-44DE)
As of January, 2002
Unit: mm
18.41
18.81 Max
23
10.16
44
0.80
*0.27 ± 0.07
0.25 ± 0.05
22
0.80
0.13 M
11.76 ± 0.20
1.005 Max
*Dimension including the plating thickness
Base material dimension
14
0.13 ± 0.05
0.10
*0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0˚ – 5˚
0.50 ± 0.10
Hitachi Code
JEDEC
JEITA
Mass (reference value)
TTP-44DE
—
—
0.43 g
0.68
1
HM628100I Series
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Tel: (03) 3270-2111 Fax: (03) 3270-5109
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Copyright C Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 7.0
15
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