Intersil DG508ACJ Cmos analog multiplexer Datasheet

[ /Title
(DG50
6A,
DG507
A,
DG508
A,
DG509
A)
/Subject
(CMO
S Analog
Multiplexers)
/Autho
r ()
/Keywords
(Intersil
Corporation,
semiconductor,
Multiplexer,
Mux,
channel,
latched
,
video)
/Creator ()
DG508A
Data Sheet
September 13, 2004
FN3137.5
CMOS Analog Multiplexers
Features
The DG508A is a CMOS Monolithic 8-Channel Analog
Multiplexer, which can also be used as a demultiplexer. An
enable input is provided. When the enable input is high, a
channel is selected by the address inputs, and when low, all
channels are off.
• Low Power Consumption
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
• Break-Before-Make Switching
The DG508A is pinout compatible with the industry standard
devices.
• TTL and CMOS-Compatible Address and Enable Inputs
• 44V Maximum Power Supply Rating
• High Latch-Up Immunity
• Alternate Source
• Pb-free Available
Applications
• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing
• Audio Signal Multiplexing
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
16 Ld CERDIP
PKG.
DWG. #
Truth Table
DG508A
DG508AAK
-55 to 125
F16.3
DG508ABK
-25 to 85
16 Ld CERDIP
F16.3
A2
A1
A0
EN
ON SWITCH
DG508ACJ
0 to 70
16 Ld PDIP
E16.3
X
X
X
0
None
DG508ACJZ
(See Note)
0 to 70
16 Ld PDIP
(Pb-free)
E16.3
0
0
0
1
1
0
0
1
1
2
0
1
0
1
3
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
DG508A (PDIP, CERDIP)
TOP VIEW
1
16 A1
EN 2
15 A2
A0
V- 3
A0 , A1 , A2 , EN
Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V
14 GND
S1
4
13 V+
S2
5
12 S5
S3
6
11 S6
S4
7
10 S7
D 8
9 S8
1
1-888-INTERSIL or 321-724-7143
|
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001, 2004
DG508A
Functional Diagram
DG508A
S1
S2
S3
S4
S5
D
ADDRESS DECODER
1 OF 8
S6
S7
S8
A0
A1
A2
EN (ENABLE INPUT)
3 Line Binary Address Inputs
(1 0 1) and EN = 1
Above example shows channel 6 turned ON.
Schematic Diagram
V+
LOGIC TRIP
POINT REF
DECODER
+
-
V+
SX
AX
GND
DX
LOGIC AX
INPUT OR EN
VLOGIC INTERFACE
AND LEVEL SHIFTER
2
TYPICAL
SWITCH
DG508A
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . .(V- -2V) To (V+ +2V)
Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA
Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Thermal Resistance (Typical, Note 2)
Operating Conditions
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
θJA (oC/W)
θJC (oC/W)
16 Ld CERDIP Package. . . . . . . . . . . .
75
20
16 Ld PDIP Package . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature
“A” and “B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 125oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on SX , D, EN, or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified
Electrical Specifications
“A” SUFFIX
PARAMETER
TEST CONDITIONS
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANSITION
See Figure 1
-
0.6
1
-
0.6
-
µs
Break-Before-Make
Interval, tOPEN
See Figure 3
-
0.2
-
-
0.2
-
µs
Enable Turn-ON Time,
tON(EN)
See Figure 2
-
1
1.5
-
1
-
µs
Enable Turn-OFF Time,
tOFF(EN)
See Figure 2
-
0.4
1.0
-
0.4
-
µs
OFF Isolation, OIRR
VEN = 0V, RL = 1kΩ, CL = 15pF,
VS = 7VRMS , f = 500kHz (Note 5)
-
68
-
-
68
-
dB
Source OFF Capacitance,
CS(OFF)
VS = 0V, VEN = 0V, f = 140kHz
-
5
-
-
5
-
pF
Drain OFF Capacitance,
CD(OFF)
VD = 0V, VEN = 0V, f = 140kHz
-
25
-
-
25
-
pF
Charge Injection, Q
See Figure 4
-
4
-
-
4
-
pC
-10
-0.002
-
-10
-0.002
-
µA
DIGITAL INPUT CHARACTERISTICS
Address Input Current,
Input Voltage High, IAH
VA = 2.4V
VA = 15V
Address Input Current Input VEN = 2.4V
Voltage Low, IAL
VEN = 0V
VA = 0V
-
0.006
10
-
0.006
10
µA
-10
-0.002
-
-10
-0.002
-
µA
-10
-0.002
-
-10
-0.0002
-
µA
-15
-
+15
-15
-
+15
V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
(Note 7)
Drain-Source ON
Resistance, rDS(ON)
Sequence Each IS = -200µA, VD = +10V
Switch ON
IS = -200µA, VD = -10V
VAL = 0.8V,
VAH = 2.4V
-
270
400
-
270
450
Ω
-
230
400
-
230
450
Ω
rDS(ON) Matching
Between Channels
-10V ≤ VS ≤ +10V
-
6
-
-
6
-
%
r DS(ON)MAX – r DS ( ON )MIN
∆r DS ( ON ) = ----------------------------------------------------------------------r DS ( ON )AVG
3
DG508A
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued)
Electrical Specifications
“A” SUFFIX
PARAMETER
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TEST CONDITIONS
Source OFF Leakage
Current, IS(OFF)
VEN = 0V
VS = +10V, VD = -10V
-1
0.002
1
-5
0.002
VS = -10V, VD = +10V
-1
Drain OFF Leakage
Current, ID(OFF)
VEN = 0V
VS = -10V, VD = +10V
-
VS = +10V, VD = -10V
-10
Drain ON Leakage Current,
ID(ON)
(Note 6)
VD = VS(ALL) = +10V
Sequence Each V = V
D
S(ALL) = -10V
Switch ON
VAL = 0.8V,
VAH = 2.4V
-10
5
nA
-0.005
1
-5
-0.005
5
nA
0.01
10
-
0.01
20
nA
-0.015
-
-20
-0.015
-
nA
0.015
10
-
0.015
20
nA
-0.03
-
-20
-0.03
-
nA
-
1.3
2.4
-
1.3
2.4
mA
-1.5
-0.7
-
-1.5
-0.7
-
mA
POWER SUPPLY CHARACTERISTICS
VEN = 5.0V (Enabled) or
Negative Supply Current, I- VEN = 0V (Standby), VA = 0V
Positive Supply Current, I+
Electrical Specifications
TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V,
Unless Otherwise Specified
“A” SUFFIX
PARAMETER
TEST CONDITIONS
MIN
(NOTE 3)
TYP
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Address Input Current, Input Voltage
High, IAH
VA = 2.4V
-30
-
-
µA
VA = 15V
-
-
30
µA
Address Input Current Input Voltage
Low, IAL
VEN = 2.4V
-30
-
-
µA
-30
-
-
µA
-15
-
+15
V
VA = 0V
VEN = 0V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
(Note 7)
Drain-Source ON Resistance, rDS(ON)
Sequence Each Switch ON
VAL = 0.8V, VAH = 2.4V
IS = -200µA, VD = +10V
-
-
500
Ω
IS = -200µA, VD = -10V
-
-
500
Ω
VEN = 0V
VS = +10V, VD = -10V
-
-
50
nA
VS = -10V, VD = +10V
-50
-
-
nA
VS = -10V, VD = +10V
-
-
200
nA
VS = +10V, VD = -10V
-200
-
-
nA
Source OFF Leakage Current, IS(OFF)
Drain OFF Leakage Current, ID(OFF)
Drain ON Leakage Current, ID(ON)
VEN = 0V
(Note 6) Sequence Each Switch ON VD = VS(ALL) = +10V
VAL = 0.8V, VAH = 2.4V
VD = VS(ALL) = -10V
-
-
200
nA
-200
-
-
nA
VEN = 5.0V, VA = 0V
-3.2
-
4.5
mA
-3.2
-
4.5
mA
VEN = 0V, VA = 0V
-3.2
-
4.5
mA
-3.2
-
4.5
mA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, IPositive Standby Supply Current, I+
Negative Standby Supply Current, INOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet.
5. Off isolation = 20Log |VS |/|VD |, where VS = input to Off switch, and VD = output due to VS .
6. ID(ON) is leakage from driver into “ON” switch.
7. Parameter not tested. Parameter guaranteed by design or characterization.
4
DG508A
Test Circuits and Waveforms
+15V
+2.4V
3V
EN
DG508A
0
+10V
S1
VS1 S1 ON
0.8VS1
S2 THRU S7
A2
S8
A1
A0
LOGIC
INPUT
SWITCH
OUTPUT
VO
-10V
SWITCH
OUTPUT
VO
D
GND
tr < 20ns
tf < 20ns
50%
LOGIC INPUT
V+
0.8VS8
VS8
V1MΩ
50Ω
0
S8 ON
35pF
TRANSITION
TIME
-15V
FIGURE 1A. TEST CIRCUIT
TRANSITION
TIME
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIME
+15V
V+
EN
tr < 20ns
tf < 20ns
50%
3V
-5V
S1
50%
EN
DG508A
0V
tON (EN)
S2 THRU S8
tOFF (EN)
0V
A2
0.1VO
A1
A0
EN
50Ω
SWITCH
OUTPUT
VO
D
GND
V-
1kΩ
SWITCH
OUTPUT
VO
35pF
VO
0.9VO
-15V
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2A. TEST CIRCUIT
FIGURE 2. ENABLE TIMES
+15V
+2.4V
V+
EN
A0
+5V (VS)
S1 THRU S8
tr < 20ns
tf < 20ns
3V
LOGIC
INPUT
DG508A
0V
A1
VS
A2
SWITCH
OUTPUT
VO
D
LOGIC
INPUT
GND
V-
50Ω
SWITCH
OUTPUT
VO
50%
50%
0V
1kΩ
35pF
tOPEN
-15V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
5
DG508A
Test Circuits and Waveforms
(Continued)
+15V
V+
EN
3V
DG508A
EN
S1
0
A2
A1
∆VO
VO
A0
LOGIC
INPUT
D
GND
VO
V1000pF
∆VO is the measured voltage error due to charge injection.
The charge transfer error in Coulombs is Q = CL x ∆VO .
-15V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. CHARGE INJECTION WAVEFORMS
FIGURE 4. CHARGE INJECTION
Typical Performance Curves
550
400
V+ = +15V, V- = -15V
V+ = +10V, V- = -10V
450 V+ = +12V, V- = -12V
V+ = +7.5V, V- = -7.5V
400
V+ = +15V V- = -15V
VEN = 2.4V
IO = -200µA
+10V SIGNALS
300
350
rDS(ON) (Ω)
rDS(ON) (Ω)
500
300
250
-10V SIGNALS
200
200
150
100
100
50
0
-15
-10
-5
0
5
10
ANALOG SIGNAL VOLTAGE (V)
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs
SUPPLY VOLTAGE
6
15
0
-55
-25
0
20
45
70
100
125
TEMPERATURE (oC)
FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
DG508A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG508A
EN
A0
A1
A2
GND
VV+
S1
S5
S2
S6
S3
S7
S4
7
D
S8
DG508A
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
18.66
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
N
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
8
5
E
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
0.355
19.68
D1
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.204
16
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
16
6
7
4
9
Rev. 0 12/93
DG508A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
9
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