Fairchild CD4541BC Programmable timer Datasheet

Revised May 2002
CD4541BC
Programmable Timer
General Description
Features
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special features of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
■ Available division ratios 28, 210, 213, or 216
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC network. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
■ Increments on positive edge clock transitions
■ Built-in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over processing @ < 10 kHz)
■ Oscillator frequency range ≈ DC to 100 kHz
■ Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
■ Automatic reset initializes all counters when power turns
on
■ External master reset totally independent of automatic
reset operation
■ Operates at 2n frequency divider or single transition
timer
■ Q/Q select provides output logic level flexibility
■ Reset (auto or master) disables oscillator during resetting to provide no active power dissipation
■ Clock conditioning circuit permits operation with very
slow clock rise and fall times
■ Wide supply voltage range—3.0V to 15V
■ High noise immunity—0.45 VDD (typ.)
■ 5V–10V–15V parameter ratings
■ Symmetrical output characteristics
■ Maximum input leakage 1 µA at 15V over full temperature range
■ High output drive (pin 8) min. one TTL load
Ordering Code:
Order Number
Package Number
Package Description
CD4541BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4541BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
N.C.—Not connected
Top View
© 2002 Fairchild Semiconductor Corporation
DS006001
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CD4541BC Programmable Timer
October 1987
CD4541BC
Truth Table
Division Ratio Table
Pin
State
0
1
A
B
Number of
Count
Counter Stages
2n
5
Auto Reset Operating
Auto Reset Disabled
6
Timer Operational
Master Reset On
0
0
13
8192
9
Output Initially Low
Output Initially High
0
1
10
1024
after Reset
after Reset
1
0
8
256
Single Cycle Mode
Recycle Mode
1
1
16
65536
10
n
Operating Characteristics
With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a “1”. Both types of reset will result in synchronously resetting all counter stages independent of counter state.
However, when B is “0”, normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q output
is a “1”.
The RC oscillator frequency is determined by the external
RC network, i.e.:
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2n−1 counts the RS flip-flop sets which causes the output to
and RS ≈ 2 Rtc where RS ≥ 10 kΩ
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (28, 210, 213, and
216). The 2n counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B.
change state. Hence, after another 2n−1 counts the output
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
Typical RC Oscillator
Characteristics
RC Oscillator Frequency as a
Function of RTC and C
Solid Line = RTC = 56 kΩ, RS = 1 kΩ and C = 1000 pF
f = 10.2 kHz @ VDD = 10V and TA = 25°
Line A: f as a function of C and (RTC = 56 kΩ; RS = 120k
Dashed Line = RTC = 56 kΩ, RS = 120 kΩ and C = 1000 pF
Line B: f as a function of RTC and (C = 100 pF; R S = 2 R TC
f = 7.75 kHz @ VDD = 10V and TA = 25°
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2
CD4541BC
Operating Characteristics
(Continued)
Oscillator Circuit Using RC Configuration
Logic Diagram
VDD = Pin 14
VSS = Pin 7
3
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CD4541BC
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
(Note 2)
−0.5V to +18V
Supply Voltage (VDD )
Input Voltage (VIN)
Supply Voltage (VDD)
−0.5V to VDD +0.5V
−65°C to +150 °C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Lead Temperature (TL)
DC Electrical Characteristics
Symbol
IDD
VOL
Parameter
Quiescent Device Current
LOW Level Output Voltage
Note 2: VSS = 0V unless otherwise specified.
260°C
(soldering, 10 seconds)
(Note 2)
−55°C
Conditions
Min
VIH
IOL
IOH
IIN
+125°C
Max
Min
0.005
5
150
0.010
10
300
VDD = 15V, VIN = V DD or VSS
20
0.015
20
600
0.05
0
0.05
0.05
0.05
0
0.05
0.05
0.05
0
0.05
0.05
VDD = 5V
|IO| < 1µA
VDD = 5V
|IO| < 1 µA
4.95
4.95
5
9.95
9.95
10
9.95
14.95
14.95
15
14.95
1.5
2
1.5
1.5
VDD = 10V, VO = 1.0V or 9.0V
3.0
4
3.0
3.0
VDD = 15V, VO = 1.5V or 13.5V
4.0
6
4.0
4.0
3.5
3.5
3
7.0
7.0
6
7.0
VDD = 15V, VO = 1.5V or 13.5V
11.0
11.0
9
11.0
LOW Level Output Current
VDD = 5V, VO = 0.4V
2.85
2.27
3.6
1.6
(Note 3)
VDD = 10V, VO = 0.5V
4.16
4.0
9.0
2.8
VDD = 15V, VO = 1.5V
19.3
15.6
34.0
10.9
HIGH Level Output Current
VDD = 5V, VO = 2.5V
7.96
6.42
130
4.49
(Note 3)
VDD = 10V, VO = 9.5V
4.19
3.38
8.0
2.37
VDD = 15V, VO = 13.5V
16.3
13.2
30.0
9.24
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V
V
mA
mA
−0.1
−10−5
−0.1
−1.0
VDD = 15V, VIN = 15V
0.1
10−5
0.1
1.0
4
V
3.5
VDD = 15V, VIN = 0V
Note 3: IOH and IOL are tested one output at a time.
µA
V
VDD = 5V, VO = 0.5V or 4.5V
VDD = 10V, VO = 1.0V or 9.0V
Input Current
Units
4.95
VDD = 5V, VO = 0.5V or 4.5V
HIGH Level Input Voltage
Max
5
VDD = 15V
LOW Level Input Voltage
Typ
10
VDD = 10V
VIL
Min
VDD = 5V, VIN = VDD or VSS
VDD = 15V
HIGH Level Output Voltage
+25°C
Max
VDD = 10V, VIN = V DD or VSS
VDD = 10V
VOH
0 to VDD
−55°C to +125°C
Operating Temperature Range
Power Dissipation (PD)
Dual-In-Line
3V to 15V
Input Voltage (VIN)
µA
(Note 4)
TA = 25°C, CL = 50 pF (refer to test circuits)
Symbol
tTLH
tTHL
tPLH, tPHL
tPHL, tPLH
tWH(CL)
fCL
tWH(R)
Parameter
Output Rise Time
Output Fall Time
Typ
Max
VDD = 5V
Conditions
Min
50
200
VDD = 10V
30
100
VDD = 15V
25
80
VDD = 5V
50
200
VDD = 10V
30
100
VDD = 15V
25
80
Turn-Off, Turn-On Propagation Delay,
VDD = 5V
1.8
4.0
Clock to Q (28 Output)
VDD = 10V
0.6
1.5
VDD = 15V
0.4
1.0
Turn-On, Turn-Off Propagation Delay,
VDD = 5V
3.2
8.0
Clock to Q (216 Output)
VDD = 10V
1.5
3.0
VDD = 15V
1.0
2.0
Clock Pulse Width
Clock Pulse Frequency
MR Pulse Width
CI
Average Input Capacitance
CPD
Power Dissipation Capacitance (Note 5)
VDD = 5V
400
200
VDD = 10V
200
100
VDD = 15V
150
70
2.5
1.0
VDD = 10V
6.0
3.0
VDD = 15V
8.5
4.0
VDD = 5V
400
170
200
75
VDD = 15V
150
50
Any Input
5.0
100
ns
ns
µs
µs
ns
VDD = 5V
VDD = 10V
Units
MHz
ns
7.5
pF
pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note:
AN-90.
5
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CD4541BC
AC Electrical Characteristics
CD4541BC
Test Circuits and Waveforms
Power Dissipation Test
Circuit and Waveforms
Switching Time Test
Circuit and Waveforms
(Rtc and Ctc outputs are left open)
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CD4541BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
7
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CD4541BC Programmable Timer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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