Sony CXD2043 Digital comb filter (ntsc) Datasheet

CXD2043Q
Digital Comb Filter (NTSC)
For the availability of this product, please contact the sales office.
Description
The CXD2043Q is an adaptive comb filter compatible
with NTSC system, and can provide high-precision Y/C
separation with a single-chip.
80 pin QFP (Plastic)
Features
• Y/C separation by adaptive processing
• Horizontal aperture compensation circuit
• 8-bit A/D converter (1-channel)
• 8-bit D/A converter (2-channel)
• Two 1H delay lines
• 4-PLL
Recommended Operating Conditions
• Supply voltage DVDD
5.0 ± 0.25
YVDD
5.0 ± 0.25
CVDD
5.0 ± 0.25
PVDD
5.0 ± 0.25
• Operating temperature
Topr
–20 to +75
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
• Supply voltage DVDD
VSS – 0.5 to +7.0
V
YVDD
VSS – 0.5 to +7.0
V
CVDD
VSS – 0.5 to +7.0
V
PVDD
VSS – 0.5 to +7.0
V
• Input voltage
VI
VSS – 0.5 to VDD + 0.5 V
• Output voltage VO
VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
V
V
V
V
°C
Structure
Silicon gate CMOS IC
Applications
Y/C separation for color TVs and VCRs
Block Diagram
DL
ADIN 27
A/D
1HDL
BPF
71
VI8 to VI1 to
78
1HDL
BPF
DAC
43
to
48 Y8 to Y1
·
51
·
52
BPF
Adaptive
Filter
Operation
4FSC
DAC
41 ACO
54
to C8 to C1
61
Logic Operation
Phase Comparison
31 AYO
VCO
1/4
9
10
12
FIN
CPO
VCV
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95812-ST
CXD2043Q
ACO
CVSS
Y8
Y7
Y6
Y5
Y4
Y3
DVSS
DVDD
Y2
Y1
XYOE
C8
C7
C6
C5
C4
C3
C2
C1
XCOE
APCN
TST
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
DVSS 65
DVDD
40 CVDD
66
39 CVG
TEST 67
38 CVRF
TEST 68
37 CIRF
TEST 69
36 VB
BPF 70
35 YIRF
VI8 71
34 YVRF
VI7
72
33 YVG
VI6 73
32 YVDD
VI5 74
31 AYO
VI4 75
30 YVSS
VI3 76
29 RT
VI2 77
28 AAVD
VI1 78
27 ADIN
ADCO 79
26 AAVS
INSL 80
GR
CRV
ICP
ADVS
ADVD
CPON
CLPI
PVDD
TEST
VCEN
TEST
TEST
VCV
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PVSS
8
FIN
7
CPO
6
TEST
CLKO
5
CK4
4
MCK
3
ADCK
2
DVDD
OCLK
1
DVSS
25 RB
Pin Description
Pin
No.
Symbol
I/O
Description
Clock amplifier input.
Input at 0.8Vp-p or more by eliminating DC components with a capacitor.
1
OCLK
I
2
DVSS
—
Digital ground
3
DVDD
—
Digital power supply
4
CLKO
O
Clock amplifier output.
Left open when the clock amplifier is not used.
5
MCK
I
Master clock input
6
ADCK
I
Clock input for A/D converter. Input the same clock signal as for Pin 5.
7
CK4
O
4FSC clock output. Generated from the built-in 4-PLL.
8
TEST
I
Test. Fix to Low.
9
FIN
I
FSC clock input. Input FSC which is burst-locked.
Connect to DVss when the PLL is not used.
10
CPO
O
Phase comparison output for the built-in PLL.
Left open when the PLL is not used.
11
PVSS
—
PLL analog ground
–2–
CXD2043Q
Pin
No.
Symbol
12
VCV
I
Control voltage input for the built-in VCO oscillation.
Connect to PVss when the PLL is not used.
13
TEST
I
Test. Fix to Low.
14
TEST
I
Test. Fix to Low.
15
VCEN
I
Built-in VCO oscillation enable. Connect to PVDD when using the PLL.
Connect to PVss when the PLL is not used.
16
TEST
O
Test. Left open.
17
PVDD
—
PLL analog power supply
18
CLPI
I
Clamp pulse input for A/D converter (negative polarity).
Connect to DVDD when the clamp is off.
19
CPON
I
High: Clamp function is set to off, and only the normal A/D converter function is enabled.
Low: Clamp function is enabled.
20
ADVD
—
Digital power supply for A/D converter
21
ADVS
—
Digital ground for A/D converter
22
ICP
I
Clamp control voltage
23
CRV
I
Clamp reference voltage input
24
GR
—
Connect to analog ground.
25
RB
O
A/D converter reference voltage (bottom)
26
AAVS
—
Analog ground for A/D converter
27
ADIN
I
28
AAVD
—
Analog power supply for A/D converter
29
RT
O
A/D converter reference voltage (top)
30
YVSS
—
Analog ground for Y-D/A converter
31
AYO
O
Analog luminance signal output
32
YVDD
—
Analog power supply for Y-D/A converter
33
YVG
O
Connect to YVDD via a capacitor of approximately 0.1µF.
34
YVRF
I
VRF for Y. Sets the output full-scale value for Y.
35
YIRF
I
Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin.
36
VB
O
Connect to YVss via a capacitor of approximately 0.1µF.
37
CIRF
O
Connect a resistor of 16 times (16R) that of the output resistor "R" of ACO pin.
38
CVRF
I
VRF for C. Sets the output full-scale value for C.
39
CVG
O
Connect to CVDD via a capacitor of approximately 0.1µF.
40
CVDD
—
Analog power supply for C-D/A converter
41
ACO
O
Analog chroma signal output
42
CVSS
—
Analog ground for C-D/A converter
43
Y8
O
Digital luminance signal output (MSB)
44
Y7
O
Digital luminance signal output
45
Y6
O
Digital luminance signal output
I/O
Description
Comb filter analog input (A/D converter input)
–3–
CXD2043Q
Pin
No.
Symbol
I/O
46
Y5
O
Digital luminance signal output
47
Y4
O
Digital luminance signal output
48
Y3
O
Digital luminance signal output
49
DVSS
—
Digital ground
50
DVDD
—
Digital power supply
51
Y2
O
Digital luminance signal output
52
Y1
O
Digital luminance signal output (LSB)
53
XYOE
I
Digital luminance signal output control
High: High impedance
Low: Standard output
54
C8
O
Digital chroma signal output (MSB)
55
C7
O
Digital chroma signal output
56
C6
O
Digital chroma signal output
57
C5
O
Digital chroma signal output
58
C4
O
Digital chroma signal output
59
C3
O
Digital chroma signal output
60
C2
O
Digital chroma signal output
61
C1
O
Digital chroma signal output (LSB)
62
XCOE
I
Digital chroma signal output control.
High: High impedance
Low: Standard output
63
APCN
I
Aperture compensation switching.
High: Aperture compensation ON
Low: Aperture compensation OFF
Y output through mode.
High: Outputs the input composite video signal from the Y output. At this time,
there is 1H + 18 clock delay from the input.
Low: Y/C separation mode
Description
64
TST
I
65
DVSS
—
Digital ground
66
DVDD
—
Digital power supply
67
TEST
I
Test. Fix to Low.
68
TEST
I
Test. Fix to Low.
69
TEST
I
Test. Fix to Low.
70
BPF
I
High: Fixed to BPF separation
Low: Standard mode
71
VI8
I
Digital composite video input (MSB)
72
VI7
I
Digital composite video input
73
VI6
I
Digital composite video input
74
VI5
I
Digital composite video input
75
VI4
I
Digital composite video input
76
VI3
I
Digital composite video input
–4–
CXD2043Q
Pin
No.
Symbol
77
VI2
I
Digital composite video input
78
VI1
I
Digital composite video input (LSB)
79
ADCO
I
High: Video signals taken in form A/D converter are output from the Y output pins
(Y8 to Y1) as 8-bit digital data with a 3.5 clock delay.
Low: Normal mode
80
INSL
I
Input switching.
High: Digital input
Low: Analog input.
I/O
Description
–5–
CXD2043Q
Electrical Characteristics
DC Characteristics
Item
(VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
—
4.75
5.0
5.25
V
—
–20
—
+75
°C
—
—
80
mA
DVDD
AAVD
Supply voltage
ADVD
YVDD
CVDD
Operating temperature
Topr
Supply current
IDD
Clock 14MHz
High level input voltage
VIH
CMOS level
VDD × 0.7
—
VDD
V
Low level input voltage
VIL
CMOS level
VSS
—
VDD × 0.3
V
High level output voltage
VOH
VDD – 0.8
—
VDD
IOH = –4mA (Pins 4, 7)
Low level output voltage
VOL
Logical Vth
LVth
Input voltage
VIN
Feedback resistor
RFB
Symbol
Data hold time
Propagation delay time
tpd
Clock frequency
f
OCLK (Pin 1)
Conditions
VSS
—
0.4
—
VDD/2
—
V
0.8
—
VDD
Vp-p
250k
1M
2.5M
Ω
Min.
Typ.
Max.
Unit
MCK → VI [8 : 1]
15.0
—
—
ns
MCK → VI [8 : 1]
10.0
—
—
ns
MCK → Y [A : 1]
MCK → C [A : 1]
—
—
40
ns
14
4fsc
15
MHz
—
Pin Capacitance
Item
V
(VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C, CL = 20pF)
tdsu
tdh
Data setup time
IOL = 4mA
IOL = 8mA (Pins 4, 7)
AC Characteristics
Item
IOH = –2mA
(Ta = 25°C, f = 1MHz, VIN = VOUT = 0V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
CIN
—
—
—
9
pF
Output capacitance
COUT
—
—
—
11
pF
–6–
CXD2043Q
ADC Characteristics
(VDD = 5V, Ta = 25°C, f = 10MHz)
Item
Symbol
Min.
Typ.
Max.
Unit
—
8
—
bit
14.3
—
—
MSPS
—
18
—
MHz
VRB
0.48
0.52
0.56
V
VRT – VRB
1.96
2.08
2.22
V
Resolution
n
Max. conversion speed
fmax
Analog input band width
BW
Self bias
Conditions
–3dB
Propagation delay time
tpd
—
—
45
ns
Differential linearity error
ED
–1.0
—
+1.0
LSB
Integral linearity error
EL
–3.0
—
+3.0
LSB
Clamp offset voltage
EOC
VREF = VRB
–20
0
+20
mV
VREF = VRT
–30
–10
+10
mV
(VDD = 5V, VRF = 2V, IRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz)
DAC Characteristics
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Resolution
n
—
—
8
—
bit
Max. conversion speed
fmax
—
14.3
—
—
MSPS
Differential linearity error
ED
—
–0.5
—
+0.5
LSB
Integral linearity error
EL
—
–1.5
—
+1.5
LSB
Output full-scale voltage
VFS
—
1.805
1.90
1.995
V
Output full-scale current
IFS
—
—
9.5
15
mA
Output offset voltage
VOS
—
—
—
1.0
mV
Precision guaranteed output voltage
VOC
range
—
1.8
—
2.1
V
—
30
—
pV-s
Glitch energy
GE
∗1
∗1 R = 75Ω, 1Vp-p output
–7–
CXD2043Q
Application Circuit for A/D Converter
(1) In the case of input clamp pulse directly.
0.01µ
ADC Input
29 RT
Clamp Pulse
CLPI 18
75
27
ADIN
CPON 19
10p
47µ
25 RB
ADC Clock
ADCK 6
0.01µ
23 CRV
20k
22 ICP
0.01µ
24 GR
28 AAVD
0.1µ
ADVD 20
AAVS
ADVS 21
26
0.1µ
(2) In the case of not using the internal clamp circuit
0.01µ
ADC Input
29 RT
CLPI 18
75
27 ADIN
CPON 19
25 RB
ADCK
10p
0.01µ
ADC Clock
6
23 CRV
22 ICP
24 GR
28 AAVD
0.1µ
ADVD 20
26 AAVS
ADVS 21
–8–
0.1µ
CXD2043Q
Application Circuit for D/A Converter
Y OUTPUT
AYO 31
200 (R)
0.1µ
32 YVDD
0.1µ
30
YVSS
YVG 33
1k
YVRF 34
CLOCK
5
MCK
YIRF 35
DVDD
VB 36
3.3k (R')
0.1µ
DVSS
C OUTPUT
ACO 41
200 (R)
0.1µ
0.1µ
40 CVDD
CVG 39
42 CVSS
CVRF 38
1k
CIRF 37
3.3k (R')
• Method of Selecting Output Resistance
The CXD2043Q has a built-in current output-type D/A converter. To obtain the output voltages, connect
resistances to AYO and ACO pins.
The voltage and current specifications are:
Output full-scale voltage: VFS = 0.5 to 2.0V
Output full-scale current: IFS = 0 to 15mA
Calculate the output resistance using the relationship VFS = IFS × R. In addition, connect a resistance of 16
times the output resistance to the reference current pin (YIRF, CIRF). In the case where the value comes to
be impractical, use a value of resistance as close to the value calculated as possible.
Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF).
R is the resistance connected to AYO/ACO, and R' is the resistance connected to YIRF/CIRF. Power
consumption can be reduced by using higher resistance values, but then glitch energy and data settling time
increase contrastingly. Select optimum resistance values according to the system applications.
• VDD, VSS
Separate the analog and digital systems around the device to reduce noise effect. YVDD and CVDD are
respectively by-passed to YVSS and CVSS as close to each other as possible through ceramic capacitor of
approximately 0.1µF.
–9–
0.01µ
XCOE
Y1
Y2
XYOE
C8
Y8
Y6
Y5
Y3
Y4
DVSS
DVDD
73 VI6
APCN
2
OCLK
1
fsc IN
0.001µ
80 INSL
DVSS
79 ADCO
78 VI1
77 VI2
76 VI3
75 VI4
74 VI5
C1
CLKO
4
D5V
0.01µ
3
C2
7
6
5
C5
TEST
8
C7
C6
FIN
CPO
220
CVG 39
CVDD 40
A5V
56k
0.022µ
560k
10µ
220
0.1µ
VREF
5k
0.1µ
0.1µ
A5V
Clamp Pulse IN
D5V
0.1µ
0.01µ
0.1µ
3.3k
0.1µ
3.3k
0.1µ
0.01µ
A5V
47µ
A5V
YVVRF
10k
CVRF
10k
2
A5V
A5V
IN
IN
IN
3
GND
1
3
GND
OUT
LPF
3
GND
OUT
LPF
OUT
LPF
1
1
Y OUT
C OUT
VIDEO IN
NPN
A5V
2
2
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
0.01µ
0.01µ
RB 25
AAVS 26
ADIN 27
AAVD 28
RT 29
YVSS 30
AYO 31
YVDD 32
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VCV
YVG 33
PVSS
72 VI7
TEST
YVRF 34
TEST
71 VI8
VCEN
YIRF 35
TEST
70 BPF
CLPI
VB 36
PVDD
69 TEST
CPON
CIRF 37
ADVD
68 TEST
ICP
CVRF 38
CXD2043Q
IC1
Y7
ADVS
ACO
67 TEST
DVDD
TST
66 DVDD
CRV
65 DVSS
C4
MCK
D5V
D5V
CVSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
C3
CK4
ADCK
– 10 –
GR
0.01µ
Application Circuit
CXD2043Q
CXD2043Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 11 –
0.8 ± 0.2
80
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