ON BSR58LT1G Jfet chopper transistor n−channel − depletion Datasheet

BSR58LT1
JFET Chopper Transistor
N−Channel − Depletion
Features
• Pb−Free Package is Available
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MAXIMUM RATINGS
Rating
2 SOURCE
Symbol
Value
Unit
Drain −Gate Voltage
VDG
−40
Vdc
Gate −Source Voltage
VGS
−35
Vdc
Gate Current
IG
50
mAdc
Total Device Dissipation
@ TA = 25°C
Derate above 25°C
PD
350
2.8
mW
mW/°
C
Lead Temperature
TL
300
°C
TJ, Tstg
−65 to +150
°C
Operating and Storage Junction
Temperature Range
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
3
GATE
1 DRAIN
3
SOT−23
CASE 318
STYLE 10
1
2
MARKING DIAGRAM
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
V(BR)GSS
40
−
Vdc
IGSS
−
− 1.0
nAdc
VGS(off)
−0.8
−4.0
Vdc
ID(off)
−
1.0
nAdc
M6
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
IDSS
8.0
80
mAdc
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
Static Drain−Source On Resistance
(VDS = 0.1 Vdc)
rDS(on)
−
60
W
Drain Gate and Source Gate
On−Capacitance
(VDS = VGS = 0, f = 1.0 MHz)
Cdg(on)
+
Csg(on)
−
28
pF
Drain Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
Cdg(off)
−
5.0
pF
Source Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
Csg(off)
−
5.0
pF
OFF CHARACTERISTICS
Gate −Source Breakdown Voltage
(IG = −1.0 mAdc)
Gate Reverse Current
(VGS = −15 Vdc)
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 mAdc)
Drain−Cutoff Current
(VDS = 5.0 Vdc, VGS = −10 Vdc)
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current (Note
1)
(VDS = 15 Vdc)
August, 2005 − Rev. 1
ORDERING INFORMATION
Device
BSR58LT1
BSR58LT1G
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
© Semiconductor Components Industries, LLC, 2005
M6M G
G
1
Package
Shipping†
SOT−23
3000/Tape & Reel
SOT−23
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
BSR58LT1/D
BSR58LT1
TYPICAL SWITCHING CHARACTERISTICS
1000
TJ = 25°C
500
RK = RD′
200
J111
J112
J113
100
500
VGS(off) = 12 V
= 7.0 V
= 5.0 V
50
20
10
RK = 0
5.0
RK = RD′
200
t r , RISE TIME (ns)
t d(on), TURN−ON DELAY TIME (ns)
1000
TJ = 25°C
VGS(off) = 12 V
= 7.0 V
= 5.0 V
100
50
20
10
RK = 0
5.0
2.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.5 0.7 1.0
50
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
1000
1000
TJ = 25°C
500
J111
J112
J113
200
100
VGS(off) = 12 V
= 7.0 V
= 5.0 V
RK = RD′
200
20
10
RK = 0
5.0
30
50
TJ = 25°C
500
RK = RD′
50
20
Figure 2. Rise Time
t f , FALL TIME (ns)
t d(off) , TURN−OFF DELAY TIME (ns)
J111
J112
J113
100
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
50
20
RK = 0
10
5.0
2.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.5 0.7 1.0
50
Figure 3. Turn−Off Delay Time
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
Figure 4. Fall Time
NOTE 1
+VDD
RD
SET VDS(off) = 10 V
INPUT
RK
RGEN
50 W
INPUT PULSE
tr ≤ 0.25 ns
tf ≤ 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
During the turn−on interval, Gate−Source Capacitance (Cgs) discharges
OUTPUT through the series combination of RGen and RK. Cgd must discharge to
50 W
VGEN
RT
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval, the
gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source Voltage
(VDS) is slightly lower than Drain Supply Voltage (VDD) due to the
voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate−Drain
Capacitance (Cgd) is charged to VGG + VDS.
RGG
50 W
VGG
RGG & RK
RD(RT ) 50)
RDȀ +
RD ) RT ) 50
Figure 5. Switching Time Test Circuit
VDS(on) through RG and RK in series with the parallel combination of
effective load impedance (R′D) and Drain−Source Resistance (rds).
During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistance
rds is a function of the gate−source voltage. While Cgs discharges, VGS
approaches zero and rds decreases. Since Cgd discharges through rds,
turn−on time is non−linear. During turn−off, the situation is reversed with
rds increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK is
equal to RD, which simulates the switching behavior of cascaded stages
where the driving source impedance is normally the load impedance of
the previous stage, and 2) RK = 0 (low impedance) the driving source
impedance is that of the generator.
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2
50
20
15
J112
10
J111
10
J113
7.0
5.0
Cgs
C, CAPACITANCE (pF)
y fs, FORWARD TRANSFER ADMITTANCE (mmhos)
BSR58LT1
Tchannel = 25°C
VDS = 15 V
7.0
5.0
Cgd
3.0
2.0
3.0
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
1.5
2.0
0.5 0.7
1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.03 0.05 0.1
50
Figure 6. Typical Forward Transfer Admittance
IDSS
= 10
160 mA
25
mA
50mA
75mA 100mA
80
0
Tchannel = 25°C
0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
7.0
8.0
ID = 1.0 mA
VGS = 0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
−70
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
90
9.0
8.0
7.0
rDS(on) @ VGS = 0
60
50
−10
20
50
80
110
Tchannel, CHANNEL TEMPERATURE (°C)
140
170
10
Tchannel = 25°C
80
70
−40
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
6.0
VGS(off)
5.0
40
4.0
30
3.0
20
2.0
10
1.0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
VGS, GATE−SOURCE VOLTAGE (VOLTS)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
100
30
2.0
125mA
120
40
10
Figure 7. Typical Capacitance
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (NORMALIZED)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
200
0.3 0.5
1.0
3.0 5.0
VR, REVERSE VOLTAGE (VOLTS)
NOTE 2
The Zero−Gate−Voltage Drain Current (IDSS), is the principle
determinant of other J-FET characteristics. Figure 10 shows the
relationship of Gate−Source Off Voltage (VGS(off) and Drain−
Source On Resistance (rds(on)) to IDSS. Most of the devices will
be within ±10% of the values shown in Figure 10. This data will
be useful in predicting the characteristic variations for a given
part number.
For example:
Unknown
rds(on) and VGS range for an J112
The electrical characteristics table indicates that an J112 has
an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 W
for IDSS = 25 mA and 30 W for IDSS = 75 mA.
The corresponding VGS values are 2.2 V and 4.8 V.
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
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3
BSR58LT1
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. 318−01 THRU −07 AND −09 OBSOLETE, NEW
STANDARD 318−08.
D
3
1
E
2
HE
DIM
A
A1
b
c
D
E
e
L
HE
e
A
b
A1
C
L
MIN
0.89
0.01
0.37
0.09
2.80
1.20
1.78
0.35
2.10
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.13
0.18
2.90
3.04
1.30
1.40
1.90
2.04
0.54
0.69
2.40
2.64
MIN
0.035
0.001
0.015
0.003
0.110
0.047
0.070
0.014
0.083
INCHES
NOM
0.040
0.002
0.018
0.005
0.114
0.051
0.075
0.021
0.094
MAX
0.044
0.004
0.020
0.007
0.120
0.055
0.081
0.029
0.104
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
0.8
0.031
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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BSR58LT1/D
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